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REJ09B0098-0300
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16
H8S/2114RGroup
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2114R R4F2114R
Rev.3.00 Revision Date: Jul. 14, 2005
Rev. 3.00 Jul. 14, 2005 Page ii of xlviii
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev. 3.00 Jul. 14, 2005 Page iii of xlviii
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 3.00 Jul. 14, 2005 Page iv of xlviii
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) Product code, Package dimensions, etc. The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 3.00 Jul. 14, 2005 Page v of xlviii
Preface
This H8S/2114R Group is a series of microcomputers (MCUs) made up of the H8S/2000 CPU with Renesas Technology's original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU. This LSI is equipped with ROM, RAM, two kinds of PWM timers (PWM and PWMX), a 16-bit free running timer (FRT), a 16-bit timer pulse unit (TPU), 8-bit timers (TMR), watchdog timer (WDT), serial communication interface (SCI), I2C bus interface (IIC), a LPC interface (LPC), a keyboard buffer control units (KBU), an A/D converter, and I/O ports as on-chip peripheral modules required for system configuration. A data transfer controller (DTC) and LPC interface (LPC) are included as bus masters. A flash memory (F-ZTATTM*) is available for this LSI's 1 Mbyte ROM. The CPU and ROM are connected to a 16-bit bus, enabling byte data and word data to be accessed in a single state. This improves the instruction fetch and process speeds. Note: * F-ZTATTM is a trademark of Renesas Technology. Corp. Target Users: This manual was written for users who use the H8S/2114R in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2114R Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read this manual in the order of the table of contents. This manual can be roughly categorized into the descriptions on the CPU, system control functions, peripheral functions and electrical characteristics.
Rev. 3.00 Jul. 14, 2005 Page vi of xlviii
* In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. * In order to understand the detailed function of a register whose name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 25, List of Registers. Rules: Register name: The following notation is used for cases when the same or a similar function, e.g., serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/
H8S/2114R Group manuals:
Document Title H8S/2114R Group Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual Document No. This manual REJ09B0139
User's manuals for development tools:
Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Microcomputer Development Environment System H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual Document No. REJ10B0058 ADE-702-282 REJ10B0024 REJ10B0026
Rev. 3.00 Jul. 14, 2005 Page vii of xlviii
Rev. 3.00 Jul. 14, 2005 Page viii of xlviii
Main Revisions and Additions in this Edition
Item All pages Page Revisions (See Manual for Details) Suffix R is added to group name and product code. * * Appendix C. Package Dimensions Figure C.1 Package Dimensions (TFP-144) 977 H8S/2114 Group R4F2114 H8S/2114R Group R4F2114R
Replaced.
Rev. 3.00 Jul. 14, 2005 Page ix of xlviii
Rev. 3.00 Jul. 14, 2005 Page x of xlviii
Contents
Section 1 Overview................................................................................................1
1.1 1.2 1.3 Overview................................................................................................................................ 1 Internal Block Diagram.......................................................................................................... 3 Pin Description....................................................................................................................... 4 1.3.1 Pin Arrangement ....................................................................................................... 4 1.3.2 Pin Arrangement in Each Operating Mode............................................................... 5 1.3.3 Pin Functions .......................................................................................................... 10
Section 2 CPU......................................................................................................19
2.1 Features................................................................................................................................ 19 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 20 2.1.2 Differences from H8/300 CPU ............................................................................... 21 2.1.3 Differences from H8/300H CPU............................................................................. 21 CPU Operating Modes......................................................................................................... 22 2.2.1 Normal Mode.......................................................................................................... 22 2.2.2 Advanced Mode...................................................................................................... 24 Address Space...................................................................................................................... 26 Register Configuration......................................................................................................... 27 2.4.1 General Registers.................................................................................................... 28 2.4.2 Program Counter (PC) ............................................................................................ 29 2.4.3 Extended Control Register (EXR) .......................................................................... 29 2.4.4 Condition-Code Register (CCR)............................................................................. 30 2.4.5 Initial Register Values............................................................................................. 31 Data Formats........................................................................................................................ 32 2.5.1 General Register Data Formats ............................................................................... 32 2.5.2 Memory Data Formats ............................................................................................ 34 Instruction Set ...................................................................................................................... 35 2.6.1 Table of Instructions Classified by Function .......................................................... 36 2.6.2 Basic Instruction Formats ....................................................................................... 47 Addressing Modes and Effective Address Calculation........................................................ 48 2.7.1 Register Direct--Rn ............................................................................................... 48 2.7.2 Register Indirect--@ERn ....................................................................................... 48 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn)................. 49 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn..... 49 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32....................................... 49 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32.................................................................... 50
2.2
2.3 2.4
2.5
2.6
2.7
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2.8 2.9
2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) ...................................... 50 2.7.8 Memory Indirect--@@aa:8 ................................................................................... 51 2.7.9 Effective Address Calculation ................................................................................ 52 Processing States.................................................................................................................. 54 Usage Notes ......................................................................................................................... 56 2.9.1 Note on TAS Instruction Usage.............................................................................. 56 2.9.2 Note on STM/LDM Instruction Usage ................................................................... 56 2.9.3 Note on Bit Manipulation Instructions ................................................................... 56 2.9.4 EEPMOV Instruction.............................................................................................. 57
Section 3 MCU Operating Modes ....................................................................... 59
3.1 3.2 Operating Mode Selection ................................................................................................... 59 Register Descriptions........................................................................................................... 60 3.2.1 Mode Control Register (MDCR) ............................................................................ 60 3.2.2 System Control Register (SYSCR)......................................................................... 61 3.2.3 Serial Timer Control Register (STCR) ................................................................... 63 3.2.4 System Control Register 3 (SYSCR3) .................................................................... 66 Operating Mode Descriptions .............................................................................................. 67 3.3.1 Mode 2.................................................................................................................... 67 3.3.2 Mode 3.................................................................................................................... 67 Address Map ........................................................................................................................ 67
3.3
3.4
Section 4 Exception Handling ............................................................................. 69
4.1 4.2 4.3 Exception Handling Types and Priority............................................................................... 69 Exception Sources and Exception Vector Table .................................................................. 70 Reset .................................................................................................................................... 74 4.3.1 Reset Exception Handling ...................................................................................... 74 4.3.2 Interrupts Immediately after Reset.......................................................................... 75 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................... 75 Interrupt Exception Handling .............................................................................................. 76 Trap Instruction Exception Handling................................................................................... 76 Stack Status after Exception Handling................................................................................. 77 Usage Note........................................................................................................................... 78
4.4 4.5 4.6 4.7
Section 5 Interrupt Controller.............................................................................. 79
5.1 5.2 5.3 Features................................................................................................................................ 79 Input/Output Pins................................................................................................................. 81 Register Descriptions........................................................................................................... 82 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD).............................................. 83 5.3.2 Address Break Control Register (ABRKCR) ......................................................... 85
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5.3.3 5.3.4 5.3.5 5.3.6 5.3.7
5.4
5.5 5.6
5.7
5.8
Break Address Registers A to C (BARA to BARC)............................................... 86 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................... 87 IRQ Enable Registers (IER16, IER) ....................................................................... 90 IRQ Status Registers (ISR16, ISR) ......................................................................... 91 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR, WUEMRB)........................................ 93 5.3.8 IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR) ..................................................................................................................... 97 Interrupt Sources.................................................................................................................. 99 5.4.1 External Interrupt Sources ...................................................................................... 99 5.4.2 Internal Interrupt Sources ..................................................................................... 102 Interrupt Exception Handling Vector Tables ..................................................................... 102 Interrupt Control Modes and Interrupt Operation .............................................................. 109 5.6.1 Interrupt Control Mode 0 ...................................................................................... 112 5.6.2 Interrupt Control Mode 1 ...................................................................................... 114 5.6.3 Interrupt Exception Handling Sequence ............................................................... 117 5.6.4 Interrupt Response Times ..................................................................................... 119 5.6.5 DTC Activation by Interrupt................................................................................. 120 Address Breaks .................................................................................................................. 122 5.7.1 Features................................................................................................................. 122 5.7.2 Block Diagram...................................................................................................... 122 5.7.3 Operation .............................................................................................................. 123 5.7.4 Usage Notes .......................................................................................................... 123 Usage Notes ....................................................................................................................... 125 5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 125 5.8.2 Instructions for Disabling Interrupts ..................................................................... 126 5.8.3 Interrupts during Execution of EEPMOV Instruction........................................... 126 5.8.4 Vector Address Switching .................................................................................... 126 5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode.................... 127 5.8.6 Noise Canceller Switching.................................................................................... 127 5.8.7 IRQ Status Register (ISR)..................................................................................... 127
Section 6 Bus Controller (BSC).........................................................................129
6.1 6.2 Features.............................................................................................................................. 129 Register Descriptions ......................................................................................................... 130 6.2.1 Bus Control Register (BCR) ................................................................................. 130 6.2.2 Wait State Control Register (WSCR) ................................................................... 131 Bus Arbitration................................................................................................................... 132 6.3.1 Priority of Bus Masters ......................................................................................... 132 6.3.2 Bus Transfer Timing............................................................................................. 132
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6.3
Section 7 Data Transfer Controller (DTC)........................................................ 135
7.1 7.2 Features.............................................................................................................................. 136 Register Descriptions......................................................................................................... 137 7.2.1 DTC Mode Register A (MRA) ............................................................................. 138 7.2.2 DTC Mode Register B (MRB).............................................................................. 139 7.2.3 DTC Source Address Register (SAR)................................................................... 139 7.2.4 DTC Destination Address Register (DAR)........................................................... 140 7.2.5 DTC Transfer Count Register A (CRA) ............................................................... 140 7.2.6 DTC Transfer Count Register B (CRB)................................................................ 140 7.2.7 DTC Enable Registers (DTCER).......................................................................... 141 7.2.8 DTC Vector Register (DTVECR)......................................................................... 142 Activation Sources............................................................................................................. 143 Location of Register Information and DTC Vector Table ................................................. 144 Operation ........................................................................................................................... 147 7.5.1 Normal Mode........................................................................................................ 148 7.5.2 Repeat Mode......................................................................................................... 149 7.5.3 Block Transfer Mode ............................................................................................ 150 7.5.4 Chain Transfer ...................................................................................................... 151 7.5.5 Interrupt Sources................................................................................................... 152 7.5.6 Operation Timing.................................................................................................. 152 7.5.7 Number of DTC Execution States ........................................................................ 154 Procedures for Using DTC................................................................................................. 155 7.6.1 Activation by Interrupt.......................................................................................... 155 7.6.2 Activation by Software ......................................................................................... 155 Examples of Use of the DTC ............................................................................................. 156 7.7.1 Normal Mode........................................................................................................ 156 7.7.2 Software Activation .............................................................................................. 157 Usage Notes ....................................................................................................................... 158 7.8.1 Module Stop Mode Setting ................................................................................... 158 7.8.2 On-Chip RAM ...................................................................................................... 158 7.8.3 DTCE Bit Setting.................................................................................................. 158 7.8.4 Setting Required on Entering Subactive Mode or Watch Mode........................... 158 7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter ......... 158
7.3 7.4 7.5
7.6
7.7
7.8
Section 8 I/O Ports............................................................................................. 159
8.1 Port 1.................................................................................................................................. 164 8.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 164 8.1.2 Port 1 Data Register (P1DR) ................................................................................ 165 8.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)................................................... 165 8.1.4 Pin Functions ........................................................................................................ 166
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8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.1.5 Port 1 Input Pull-Up MOS .................................................................................... 166 Port 2.................................................................................................................................. 167 8.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 167 8.2.2 Port 2 Data Register (P2DR)................................................................................. 168 8.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)................................................... 168 8.2.4 Pin Functions ........................................................................................................ 169 8.2.5 Port 2 Input Pull-Up MOS .................................................................................... 170 Port 3.................................................................................................................................. 171 8.3.1 8.3.1 Port 3 Data Direction Register (P3DDR)..................................................... 171 8.3.2 Port 3 Data Register (P3DR)................................................................................. 172 8.3.3 Port 3 Pull-Up MOS Control Register (P3PCR)................................................... 172 8.3.4 Pin Functions ........................................................................................................ 173 8.3.5 Port 3 Input Pull-Up MOS .................................................................................... 173 Port 4.................................................................................................................................. 174 8.4.1 Port 4 Data Direction Register (P4DDR).............................................................. 174 8.4.2 Port 4 Data Register (P4DR)................................................................................. 175 8.4.3 Pin Functions ........................................................................................................ 175 Port 5.................................................................................................................................. 178 8.5.1 Port 5 Data Direction Register (P5DDR).............................................................. 178 8.5.2 Port 5 Data Register (P5DR)................................................................................. 178 8.5.3 Pin Functions ........................................................................................................ 179 Port 6.................................................................................................................................. 180 8.6.1 Port 6 Data Direction Register (P6DDR).............................................................. 180 8.6.2 Port 6 Data Register (P6DR)................................................................................. 181 8.6.3 Pull-Up MOS Control Register (KMPCR) ........................................................... 181 8.6.4 Noise Canceller Enable Register (P6NCE)........................................................... 182 8.6.5 Noise Canceller Mode Control Register (P6NCMC)............................................ 182 8.6.6 Noise Cancel Cycle Setting Register (P6NCCS) .................................................. 183 8.6.7 System Control Register 2 (SYSCR2) .................................................................. 185 8.6.8 Pin Functions ........................................................................................................ 185 8.6.9 Port 6 Input Pull-Up MOS .................................................................................... 188 Port 7.................................................................................................................................. 189 8.7.1 Port 7 Input Data Register (P7PIN) ...................................................................... 189 8.7.2 Pin Functions ........................................................................................................ 190 Port 8.................................................................................................................................. 191 8.8.1 Port 8 Data Direction Register (P8DDR).............................................................. 191 8.8.2 Port 8 Data Register (P8DR)................................................................................. 192 8.8.3 Pin Functions ........................................................................................................ 193 Port 9.................................................................................................................................. 196 8.9.1 Port 9 Data Direction Register (P9DDR).............................................................. 196
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8.10
8.11
8.12
8.13
8.14
8.15
8.9.2 Port 9 Data Register (P9DR) ................................................................................ 197 8.9.3 Port 9 Pull-Up MOS Control Register (P9PCR)................................................... 197 8.9.4 Pin Functions ........................................................................................................ 198 8.9.5 Port 9 Input Pull-Up MOS .................................................................................... 200 Port A................................................................................................................................. 201 8.10.1 Port A Data Direction Register (PADDR)............................................................ 201 8.10.2 Port A Output Data Register (PAODR)................................................................ 202 8.10.3 Port A Input Data Register (PAPIN) .................................................................... 202 8.10.4 Pin Functions ........................................................................................................ 203 Port B ................................................................................................................................. 204 8.11.1 Port B Data Direction Register (PBDDR) ............................................................ 204 8.11.2 Port B Output Data Register (PBODR) ................................................................ 205 8.11.3 Port B Input Data Register (PBPIN)..................................................................... 205 8.11.4 Pin Functions ........................................................................................................ 206 8.11.5 Port B Input Pull-Up MOS ................................................................................... 208 Port C ................................................................................................................................. 209 8.12.1 Port C Data Direction Register (PCDDR) ............................................................ 209 8.12.2 Port C Output Data Register (PCODR) ................................................................ 210 8.12.3 Port C Input Data Register (PCPIN)..................................................................... 210 8.12.4 Noise Canceller Enable Register (PCNCE) .......................................................... 211 8.12.5 Noise Canceller Mode Control Register (PCNCMC)........................................... 211 8.12.6 Noise Cancel Cycle Setting Register (PCNCCS) ................................................. 212 8.12.7 Pin Functions ........................................................................................................ 212 8.12.8 Port C Nch-OD control register (PCNOCR)......................................................... 215 8.12.9 Pin Functions ........................................................................................................ 215 8.12.10 Port C Input Pull-Up MOS ................................................................................... 216 Port D................................................................................................................................. 217 8.13.1 Port D Data Direction Register (PDDDR)............................................................ 217 8.13.2 Port D Output Data Register (PDODR)................................................................ 218 8.13.3 Port D Input Data Register (PDPIN) .................................................................... 218 8.13.4 Pin Functions ........................................................................................................ 219 8.13.5 Port D Nch-OD control register (PDNOCR) ........................................................ 223 8.13.6 Pin Functions ........................................................................................................ 223 8.13.7 Port D Input Pull-Up MOS ................................................................................... 224 Port E ................................................................................................................................. 225 8.14.1 Port E Input Pull-Up MOS Control Register (PEPCR) ........................................ 225 8.14.2 Port E Input Data Register (PEPIN) ..................................................................... 225 8.14.3 Pin Functions ........................................................................................................ 226 8.14.4 Port E Input Pull-Up MOS.................................................................................... 226 Port F ................................................................................................................................. 227
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8.15.1 Port F Data Direction Register (PFDDR) ............................................................. 227 8.15.2 Port F Output Data Register (PFODR) ................................................................. 228 8.15.3 Port F Input Data Register (PFPIN)...................................................................... 228 8.15.4 Pin Functions ........................................................................................................ 229 8.15.5 Port F Nch-OD control register (PFNOCR).......................................................... 231 8.15.6 Pin Functions ........................................................................................................ 231 8.15.7 Port F Input Pull-Up MOS.................................................................................... 232 8.16 Port G................................................................................................................................. 233 8.16.1 Port G Data Direction Register (PGDDR) ............................................................ 233 8.16.2 Port G Output Data Register (PGODR) ................................................................ 234 8.16.3 Port G Input Data Register (PGPIN)..................................................................... 234 8.16.4 Noise Canceller Enable Register (PGNCE).......................................................... 235 8.16.5 Noise Canceller Mode Control Register (PGNCMC)........................................... 235 8.16.6 Noise Cancel Cycle Setting Register (PGNCCS) ................................................. 236 8.16.7 Pin Functions ........................................................................................................ 237 8.16.8 Port G Nch-OD control register (PGNOCR) ........................................................ 242 8.16.9 Pin Functions ........................................................................................................ 242 8.17 Change of Peripheral Function Pins................................................................................... 243 8.17.1 Port Control Register 0 (PTCNT0) ....................................................................... 243 8.17.2 Port Control Register 1 (PTCNT1) ....................................................................... 244 8.17.3 Port Control Register 2 (PTCNT2) ....................................................................... 245
Section 9 8-Bit PWM Timer (PWM).................................................................247
9.1 9.2 9.3 Features.............................................................................................................................. 247 Input/Output Pins ............................................................................................................... 249 Register Descriptions ......................................................................................................... 249 9.3.1 PWM Register Select (PWSL).............................................................................. 250 9.3.2 PWM Data Registers 15 to 8 (PWDR15 to PWDR8)........................................... 251 9.3.3 PWM Data Polarity Register B (PWDPRB)......................................................... 252 9.3.4 PWM Output Enable Register B (PWOERB)....................................................... 252 9.3.5 Peripheral Clock Select Register (PCSR) ............................................................. 253 Operation ........................................................................................................................... 254 9.4.1 PWM Setting Example ......................................................................................... 256 9.4.2 Diagram of PWM Used as D/A Converter ........................................................... 256 Usage Notes ....................................................................................................................... 257 9.5.1 Module Stop Mode Setting ................................................................................... 257
9.4
9.5
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Section 10 14-Bit PWM Timer (PWMX) ......................................................... 259
10.1 Features.............................................................................................................................. 259 10.2 Input/Output Pins............................................................................................................... 260 10.3 Register Descriptions......................................................................................................... 260 10.3.1 PWMX (D/A) Counter (DACNT) ........................................................................ 261 10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) ......................... 262 10.3.3 PWMX (D/A) Control Register (DACR) ............................................................. 264 10.3.4 Peripheral Clock Select Register (PCSR) ............................................................. 265 10.4 Bus Master Interface.......................................................................................................... 266 10.5 Operation ........................................................................................................................... 269 10.6 Usage Notes ....................................................................................................................... 276 10.6.1 Module Stop Mode Setting ................................................................................... 276
Section 11 16-Bit Free-Running Timer (FRT).................................................. 277
11.1 Features.............................................................................................................................. 277 11.2 Input/Output Pins............................................................................................................... 279 11.3 Register Descriptions......................................................................................................... 279 11.3.1 Free-Running Counter (FRC) ............................................................................... 280 11.3.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 280 11.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................. 280 11.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) .......................... 281 11.3.5 Output Compare Register DM (OCRDM)............................................................ 281 11.3.6 Timer Interrupt Enable Register (TIER)............................................................... 282 11.3.7 Timer Control/Status Register (TCSR)................................................................. 283 11.3.8 Timer Control Register (TCR).............................................................................. 286 11.3.9 Timer Output Compare Control Register (TOCR) ............................................... 287 11.4 Operation ........................................................................................................................... 289 11.4.1 Pulse Output ......................................................................................................... 289 11.5 Operation Timing............................................................................................................... 290 11.5.1 FRC Increment Timing......................................................................................... 290 11.5.2 Output Compare Output Timing........................................................................... 291 11.5.3 FRC Clear Timing ................................................................................................ 291 11.5.4 Input Capture Input Timing .................................................................................. 292 11.5.5 Buffered Input Capture Input Timing ................................................................... 293 11.5.6 Timing of Input Capture Flag (ICF) Setting ......................................................... 294 11.5.7 Timing of Output Compare Flag (OCF) setting.................................................... 295 11.5.8 Timing of FRC Overflow Flag Setting ................................................................. 295 11.5.9 Automatic Addition Timing.................................................................................. 296 11.5.10 Mask Signal Generation Timing........................................................................... 297
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11.6 Interrupt Sources................................................................................................................ 298 11.7 Usage Notes ....................................................................................................................... 299 11.7.1 Conflict between FRC Write and Clear ................................................................ 299 11.7.2 Conflict between FRC Write and Increment......................................................... 300 11.7.3 Conflict between OCR Write and Compare-Match .............................................. 301 11.7.4 Switching of Internal Clock and FRC Operation .................................................. 302 11.7.5 Module Stop Mode Setting ................................................................................... 304
Section 12 16-Bit Timer Pulse Unit (TPU) .......................................................305
12.1 Features.............................................................................................................................. 305 12.2 Input/Output Pins ............................................................................................................... 309 12.3 Register Descriptions ......................................................................................................... 310 12.3.1 Timer Control Register (TCR).............................................................................. 311 12.3.2 Timer Mode Register (TMDR) ............................................................................. 315 12.3.3 Timer I/O Control Register (TIOR) ...................................................................... 317 12.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 326 12.3.5 Timer Status Register (TSR)................................................................................. 328 12.3.6 Timer Counter (TCNT)......................................................................................... 331 12.3.7 Timer General Register (TGR) ............................................................................. 331 12.3.8 Timer Start Register (TSTR) ................................................................................ 331 12.3.9 Timer Synchro Register (TSYR) .......................................................................... 332 12.4 Interface to Bus Master ...................................................................................................... 333 12.4.1 16-Bit Registers .................................................................................................... 333 12.4.2 8-Bit Registers ...................................................................................................... 333 12.5 Operation ........................................................................................................................... 335 12.5.1 Basic Functions..................................................................................................... 335 12.5.2 Synchronous Operation......................................................................................... 341 12.5.3 Buffer Operation ................................................................................................... 343 12.5.4 PWM Modes ......................................................................................................... 347 12.5.5 Phase Counting Mode........................................................................................... 352 12.6 Interrupts............................................................................................................................ 357 12.6.1 Interrupt Source and Priority ................................................................................ 357 12.6.2 DTC Activation..................................................................................................... 359 12.6.3 A/D Converter Activation..................................................................................... 359 12.7 Operation Timing............................................................................................................... 360 12.7.1 Input/Output Timing ............................................................................................. 360 12.7.2 Interrupt Signal Timing......................................................................................... 364 12.8 Usage Notes ....................................................................................................................... 368 12.8.1 Input Clock Restrictions ....................................................................................... 368 12.8.2 Caution on Period Setting ..................................................................................... 368
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12.8.3 Conflict between TCNT Write and Clear Operations........................................... 369 12.8.4 Conflict between TCNT Write and Increment Operations ................................... 369 12.8.5 Conflict between TGR Write and Compare Match............................................... 370 12.8.6 Conflict between Buffer Register Write and Compare Match.............................. 371 12.8.7 Conflict between TGR Read and Input Capture ................................................... 372 12.8.8 Conflict between TGR Write and Input Capture .................................................. 373 12.8.9 Conflict between Buffer Register Write and Input Capture.................................. 374 12.8.10 Conflict between Overflow/Underflow and Counter Clearing ............................. 375 12.8.11 Conflict between TCNT Write and Overflow/Underflow .................................... 376 12.8.12 Multiplexing of I/O Pins ....................................................................................... 376 12.8.13 Module Stop Mode Setting ................................................................................... 376
Section 13 8-Bit Timer (TMR).......................................................................... 377
13.1 Features.............................................................................................................................. 377 13.2 Input/Output Pins............................................................................................................... 381 13.3 Register Descriptions......................................................................................................... 382 13.3.1 Timer Counter (TCNT)......................................................................................... 383 13.3.2 Time Constant Register A (TCORA) ................................................................... 383 13.3.3 Time Constant Register B (TCORB).................................................................... 384 13.3.4 Timer Control Register (TCR).............................................................................. 384 13.3.5 Timer Control/Status Register (TCSR)................................................................. 389 13.3.6 Time Constant Register C (TCORC).................................................................... 394 13.3.7 Input Capture Registers R and F (TICRR and TICRF)......................................... 394 13.3.8 Timer Input Select Register (TISR)...................................................................... 395 13.3.9 Timer Connection Register I (TCONRI) .............................................................. 395 13.3.10 Timer Connection Register S (TCONRS) ............................................................ 396 13.3.11 Timer XY Control Register (TCRXY) ................................................................. 396 13.4 Operation ........................................................................................................................... 397 13.4.1 Pulse Output ......................................................................................................... 397 13.5 Operation Timing............................................................................................................... 398 13.5.1 TCNT Count Timing ............................................................................................ 398 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 399 13.5.3 Timing of Timer Output at Compare-Match......................................................... 399 13.5.4 Timing of Counter Clear at Compare-Match........................................................ 400 13.5.5 TCNT External Reset Timing............................................................................... 400 13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 401 13.6 TMR_0 and TMR_1 Cascaded Connection....................................................................... 402 13.6.1 16-Bit Count Mode ............................................................................................... 402 13.6.2 Compare-Match Count Mode ............................................................................... 402 13.7 TMR_Y and TMR_X Cascaded Connection ..................................................................... 403
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13.7.1 16-Bit Count Mode ............................................................................................... 403 13.7.2 Compare-Match Count Mode ............................................................................... 403 13.7.3 Input Capture Operation ....................................................................................... 404 13.8 Interrupt Sources................................................................................................................ 406 13.9 Usage Notes ....................................................................................................................... 407 13.9.1 Conflict between TCNT Write and Counter Clear................................................ 407 13.9.2 Conflict between TCNT Write and Count-Up ...................................................... 408 13.9.3 Conflict between TCOR Write and Compare-Match............................................ 409 13.9.4 Conflict between Compare-Matches A and B ...................................................... 410 13.9.5 Switching of Internal Clocks and TCNT Operation.............................................. 410 13.9.6 Mode Setting with Cascaded Connection ............................................................. 412 13.9.7 Module Stop Mode Setting ................................................................................... 412
Section 14 Watchdog Timer (WDT)..................................................................413
14.1 Features.............................................................................................................................. 413 14.2 Input/Output Pins ............................................................................................................... 415 14.3 Register Descriptions ......................................................................................................... 415 14.3.1 Timer Counter (TCNT)......................................................................................... 415 14.3.2 Timer Control/Status Register (TCSR)................................................................. 416 14.4 Operation ........................................................................................................................... 420 14.4.1 Watchdog Timer Mode ......................................................................................... 420 14.4.2 Interval Timer Mode............................................................................................. 421 14.4.3 RESO Signal Output Timing ................................................................................ 422 14.5 Interrupt Sources................................................................................................................ 423 14.6 Usage Notes ....................................................................................................................... 424 14.6.1 Notes on Register Access...................................................................................... 424 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 425 14.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 426 14.6.4 Changing Value of PSS Bit................................................................................... 426 14.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................. 426 14.6.6 System Reset by RESO Signal ............................................................................. 426
Section 15 Serial Communication Interface (SCI, IrDA)..................................427
15.1 Features.............................................................................................................................. 427 15.2 Input/Output Pins ............................................................................................................... 430 15.3 Register Descriptions ......................................................................................................... 431 15.3.1 Receive Shift Register (RSR) ............................................................................... 431 15.3.2 Receive Data Register (RDR) ............................................................................... 431 15.3.3 Transmit Data Register (TDR).............................................................................. 432 15.3.4 Transmit Shift Register (TSR) .............................................................................. 432
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15.4
15.5
15.6
15.7
15.8 15.9
15.10
15.3.5 Serial Mode Register (SMR) ................................................................................ 432 15.3.6 Serial Control Register (SCR) .............................................................................. 436 15.3.7 Serial Status Register (SSR) ................................................................................. 439 15.3.8 Smart Card Mode Register (SCMR)..................................................................... 444 15.3.9 Bit Rate Register (BRR) ....................................................................................... 445 15.3.10 Keyboard Comparator Control Register (KBCOMP)........................................... 453 Operation in Asynchronous Mode ..................................................................................... 455 15.4.1 Data Transfer Format............................................................................................ 455 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode..................................................................................................................... 457 15.4.3 Clock..................................................................................................................... 458 15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 459 15.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 460 15.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 462 Multiprocessor Communication Function.......................................................................... 466 15.5.1 Multiprocessor Serial Data Transmission ............................................................. 468 15.5.2 Multiprocessor Serial Data Reception .................................................................. 469 Operation in Clocked Synchronous Mode ......................................................................... 472 15.6.1 Clock..................................................................................................................... 472 15.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 473 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 474 15.6.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 477 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) .............................................................................. 479 Smart Card Interface Description ...................................................................................... 481 15.7.1 Sample Connection............................................................................................... 481 15.7.2 Data Format (Except in Block Transfer Mode) .................................................... 481 15.7.3 Block Transfer Mode ............................................................................................ 483 15.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 483 15.7.5 Initialization.......................................................................................................... 484 15.7.6 Serial Data Transmission (Except in Block Transfer Mode) ................................ 485 15.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 488 15.7.8 Clock Output Control............................................................................................ 490 IrDA Operation .................................................................................................................. 492 Interrupt Sources................................................................................................................ 496 15.9.1 Interrupts in Normal Serial Communication Interface Mode ............................... 496 15.9.2 Interrupts in Smart Card Interface Mode .............................................................. 497 Usage Notes ....................................................................................................................... 498 15.10.1 Module Stop Mode Setting ................................................................................... 498 15.10.2 Break Detection and Processing ........................................................................... 498
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15.10.3 Mark State and Break Sending.............................................................................. 498 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..................................................................... 498 15.10.5 Relation between Writing to TDR and TDRE Flag .............................................. 498 15.10.6 Restrictions on Using DTC................................................................................... 499 15.10.7 SCI Operations during Mode Transitions ............................................................. 499 15.10.8 Notes on Switching from SCK Pins to Port Pins .................................................. 503
Section 16 I2C Bus Interface (IIC) .....................................................................505
16.1 Features.............................................................................................................................. 505 16.2 Input/Output Pins ............................................................................................................... 509 16.3 Register Descriptions ......................................................................................................... 510 16.3.1 I2C Bus Data Register (ICDR) .............................................................................. 510 16.3.2 Slave Address Register (SAR).............................................................................. 511 16.3.3 Second Slave Address Register (SARX) .............................................................. 512 16.3.4 I2C Bus Mode Register (ICMR)............................................................................ 514 16.3.5 I2C Bus Control Register (ICCR).......................................................................... 517 16.3.6 I2C Bus Status Register (ICSR)............................................................................. 526 16.3.7 DDC Switch Register (DDCSWR) ....................................................................... 530 16.3.8 I2C Bus Extended Control Register (ICXR).......................................................... 531 16.4 Operation ........................................................................................................................... 535 16.4.1 I2C Bus Data Format ............................................................................................. 535 16.4.2 Initialization .......................................................................................................... 537 16.4.3 Master Transmit Operation ................................................................................... 537 16.4.4 Master Receive Operation..................................................................................... 541 16.4.5 Slave Receive Operation....................................................................................... 551 16.4.6 Slave Transmit Operation ..................................................................................... 559 16.4.7 IRIC Setting Timing and SCL Control ................................................................. 562 16.4.8 Operation by Using DTC ...................................................................................... 565 16.4.9 Noise Canceller..................................................................................................... 567 16.4.10 Initialization of Internal State ............................................................................... 568 16.5 Interrupt Sources................................................................................................................ 569 16.6 Usage Notes ....................................................................................................................... 570 16.6.1 Module Stop Mode Setting ................................................................................... 580
Section 17 Keyboard Buffer Control Unit (KBU).............................................581
17.1 Features.............................................................................................................................. 581 17.2 Input/Output Pins ............................................................................................................... 584 17.3 Register Descriptions ......................................................................................................... 585 17.3.1 Keyboard Control Register 1 (KBCR1)................................................................ 585
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17.3.2 Keyboard Buffer Control Register 2 (KBCR2) .................................................... 587 17.3.3 Keyboard Control Register H (KBCRH) .............................................................. 588 17.3.4 Keyboard Control Register L (KBCRL)............................................................... 590 17.3.5 Keyboard Data Buffer Register (KBBR) .............................................................. 592 17.3.6 Keyboard Buffer Transmit Data Register (KBTR)............................................... 592 17.4 Operation ........................................................................................................................... 593 17.4.1 Receive Operation ................................................................................................ 593 17.4.2 Transmit Operation............................................................................................... 595 17.4.3 Receive Abort ....................................................................................................... 597 17.4.4 KCLKI and KDI Read Timing ............................................................................. 600 17.4.5 KCLKO and KDO Write Timing ......................................................................... 601 17.4.6 KBF Setting Timing and KCLK Control.............................................................. 602 17.4.7 Receive Timing..................................................................................................... 603 17.4.8 Operation during Data Reception ......................................................................... 604 17.4.9 KCLK Fall Interrupt Operation ............................................................................ 605 17.4.10 First KCLK Falling Interrupt................................................................................ 606 17.5 Usage Notes ....................................................................................................................... 611 17.5.1 KBIOE Setting and KCLK Falling Edge Detection ............................................. 611 17.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission .................... 612 17.5.3 Module Stop Mode Setting ................................................................................... 612 17.5.4 Medium Speed Mode............................................................................................ 612 17.5.5 Transmit Completion Flag (KBTE) ...................................................................... 612
Section 18 LPC Interface (LPC)........................................................................ 613
18.1 Features.............................................................................................................................. 613 18.2 Input/Output Pins............................................................................................................... 616 18.3 Register Descriptions......................................................................................................... 617 18.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 619 18.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 625 18.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 628 18.3.4 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)................ 629 18.3.5 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)................ 631 18.3.6 Input Data Registers 1 to 4 (IDR1 to IDR4) ......................................................... 632 18.3.7 Output Data Registers 1 to 4 (ODR1 to ODR4) ................................................... 633 18.3.8 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 633 18.3.9 Status Registers 1 to 4 (STR1 to STR4) ............................................................... 634 18.3.10 SERIRQ Control Register 0 (SIRQCR0).............................................................. 640 18.3.11 SERIRQ Control Register 1 (SIRQCR1).............................................................. 644 18.3.12 SERIRQ Control Register 2 (SIRQCR2).............................................................. 649 18.3.13 Host Interface Select Register (HISEL)................................................................ 653
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18.3.14 RAM Buffer Address Register (RBUFAR) .......................................................... 654 18.3.15 Flash Memory Programming Address Registers H and L (FLWARH and FLARL)....................................................................................... 655 18.3.16 Manufacture ID Code Register (LMCMIDCR) and Device ID Code Register (LMCDIDCR)....................................................................................................... 656 18.3.17 Erase Block Register (EBLKR) ............................................................................ 657 18.3.18 LMC Status Registers 1 and 2 (LMCST1 and LMCST2)..................................... 658 18.3.19 LMC Control Registers 1 and 2 (LMCCR1 and LMCCR2) ................................. 662 18.3.20 Host Base Address Registers 1H and 1L (HBAR1H and HBAR1L).................... 665 18.3.21 Host Base Address Registers 2H and 2L (HBAR2H and HBAR2L).................... 666 18.3.22 On-Chip RAM Host Base Address Registers H and L (RAMBARH and RAMBARL) ............................................................................ 667 18.3.23 Address Space Set Register (ASSR)..................................................................... 668 18.3.24 On-Chip RAM Address Space Set Register (RAMASSR) ................................... 669 18.3.25 Slave Address Register 1 (SAR1)......................................................................... 670 18.3.26 Slave Address Register 2 (SAR2)......................................................................... 671 18.3.27 On-Chip RAM Slave Address Register (RAMAR) .............................................. 671 18.3.28 Flash Memory Write Protect Registers H, M, and L (FWPRH, FWPRM, and FWPRL)........................................................................ 672 18.3.29 Flash Memory Read Protect Registers H, M, and L (FRPRH, FRPRM, and FRPRL) ........................................................................... 674 18.3.30 On-Chip RAM Protect Control Register (MPCR) ................................................ 676 18.3.31 User Command Register (UCMDTR) .................................................................. 676 18.4 Operation ........................................................................................................................... 677 18.4.1 LPC interface Activation ...................................................................................... 677 18.4.2 LPC I/O Cycles..................................................................................................... 677 18.4.3 Gate A20............................................................................................................... 680 18.4.4 LPC Interface Shutdown Function (LPCPD)........................................................ 683 18.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) ..................................... 687 18.4.6 LPC Interface Clock Start Request ....................................................................... 689 18.4.7 LPC/FW Memory Cycle ....................................................................................... 689 18.4.8 LPC/FW Memory Access Command ................................................................... 692 18.4.9 Flash Memory Address Translation (Host Slave) ............................................ 700 18.4.10 On-Chip RAM Address Translation (Host Slave) ........................................... 701 18.4.11 Address Space Priority.......................................................................................... 702 18.4.12 Example 1 of Address Space Priority ................................................................... 703 18.4.13 Example 2 of Address Space Priority ................................................................... 704 18.4.14 Flash Memory Protection...................................................................................... 705 18.4.15 On-Chip RAM Protection ..................................................................................... 707 18.4.16 Flash Memory Programming ................................................................................ 707
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18.4.17 Flash Memory Erasing.......................................................................................... 709 18.5 Interrupt Sources................................................................................................................ 710 18.5.1 IBFI1, IBFI2, IBFI3, IBFI4, LMC, LMCUI, and ERRI ....................................... 710 18.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 ........................ 711 18.6 Usage Note......................................................................................................................... 714 18.6.1 Data Conflict......................................................................................................... 714 18.6.2 Module Stop Mode Setting ................................................................................... 715 18.6.3 Operating Mode in LPC/FW Memory Write Cycle.............................................. 715
Section 19 A/D Converter ................................................................................. 717
19.1 Features.............................................................................................................................. 717 19.2 Input/Output Pins............................................................................................................... 719 19.3 Register Descriptions......................................................................................................... 720 19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 720 19.3.2 A/D Control/Status Register (ADCSR) ................................................................ 721 19.3.3 A/D Control Register (ADCR) ............................................................................. 722 19.4 Operation ........................................................................................................................... 723 19.4.1 Single Mode.......................................................................................................... 723 19.4.2 Scan Mode ............................................................................................................ 723 19.4.3 Input Sampling and A/D Conversion Time .......................................................... 724 19.4.4 External Trigger Input Timing.............................................................................. 726 19.5 Interrupt Source ................................................................................................................. 727 19.6 A/D Conversion Accuracy Definitions .............................................................................. 727 19.7 Usage Notes ....................................................................................................................... 729 19.7.1 Permissible Signal Source Impedance .................................................................. 729 19.7.2 Influences on Absolute Accuracy ......................................................................... 729 19.7.3 Setting Range of Analog Power Supply and Other Pins....................................... 730 19.7.4 Notes on Board Design ......................................................................................... 730 19.7.5 Notes on Noise Countermeasures ......................................................................... 730 19.7.6 Module Stop Mode Setting ................................................................................... 731
Section 20 RAM ................................................................................................ 733 Section 21 Flash Memory (0.18-m F-ZTAT Version).................................... 735
21.1 Features.............................................................................................................................. 735 21.1.1 Mode Transitions .................................................................................................. 737 21.1.2 Mode Comparison ................................................................................................ 738 21.1.3 Flash Memory MAT Configuration...................................................................... 739 21.1.4 Block Division ...................................................................................................... 739 21.1.5 Programming/Erasing Interface ............................................................................ 742
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21.2 Input/Output Pins ............................................................................................................... 744 21.3 Register Descriptions ......................................................................................................... 744 21.3.1 Programming/Erasing Interface Registers ............................................................ 746 21.3.2 Programming/Erasing Interface Parameters ......................................................... 753 21.4 On-Board Programming..................................................................................................... 764 21.4.1 Boot Mode ............................................................................................................ 764 21.4.2 User Program Mode.............................................................................................. 768 21.4.3 User Boot Mode.................................................................................................... 779 21.4.4 Storable Areas for Procedure Program and Program Data ................................... 783 21.5 Protection ........................................................................................................................... 791 21.5.1 Hardware Protection ............................................................................................. 791 21.5.2 Software Protection............................................................................................... 793 21.5.3 Error Protection..................................................................................................... 793 21.6 Switching between User MAT and User Boot MAT ......................................................... 795 21.7 Programmer Mode ............................................................................................................. 796 21.8 Serial Communication Interface Specifications for Boot Mode ........................................ 797 21.9 Usage Notes ....................................................................................................................... 824
Section 22 Boundary Scan (JTAG) ...................................................................827
22.1 Features.............................................................................................................................. 827 22.2 Input/Output Pins ............................................................................................................... 829 22.3 Register Descriptions ......................................................................................................... 830 22.3.1 Instruction Register (SDIR) .................................................................................. 830 22.3.2 Bypass Register (SDBPR) .................................................................................... 832 22.3.3 Boundary Scan Register (SDBSR) ....................................................................... 832 22.3.4 ID Code Register (SDIDR)................................................................................... 842 22.4 Operation ........................................................................................................................... 842 22.4.1 TAP Controller State Transitions.......................................................................... 842 22.4.2 JTAG Reset........................................................................................................... 843 22.5 Boundary Scan ................................................................................................................... 844 22.5.1 Supported Instructions .......................................................................................... 844 22.5.2 Notes ..................................................................................................................... 846 22.6 Usage Notes ....................................................................................................................... 846
Section 23 Clock Pulse Generator .....................................................................849
23.1 Oscillator............................................................................................................................ 850 23.1.1 Connecting Crystal Resonator .............................................................................. 850 23.1.2 External Clock Input Method................................................................................ 851 23.2 Duty Correction Circuit ..................................................................................................... 854 23.3 Medium-Speed Clock Divider ........................................................................................... 854
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23.4 23.5 23.6 23.7 23.8 23.9
Bus Master Clock Select Circuit........................................................................................ 854 Subclock Input Circuit ....................................................................................................... 855 Subclock Waveform Forming Circuit................................................................................ 856 Clock Select Circuit ........................................................................................................... 856 Handling of X1 and X2 Pins.............................................................................................. 857 Usage Notes ....................................................................................................................... 857 23.9.1 Notes on Resonator............................................................................................... 857 23.9.2 Notes on Board Design ......................................................................................... 857
Section 24 Power-Down Modes........................................................................ 859
24.1 Register Descriptions......................................................................................................... 860 24.1.1 Standby Control Register (SBYCR) ..................................................................... 860 24.1.2 Low-Power Control Register (LPWRCR) ............................................................ 862 24.1.3 Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA) ................................................................ 864 24.2 Mode Transitions and LSI States ....................................................................................... 866 24.3 Medium-Speed Mode ........................................................................................................ 870 24.4 Sleep Mode ........................................................................................................................ 871 24.5 Software Standby Mode..................................................................................................... 872 24.6 Hardware Standby Mode ................................................................................................... 874 24.7 Watch Mode....................................................................................................................... 875 24.8 Subsleep Mode................................................................................................................... 876 24.9 Subactive Mode ................................................................................................................. 877 24.10 Module Stop Mode ............................................................................................................ 878 24.11 Direct Transitions .............................................................................................................. 878 24.12 Usage Notes ....................................................................................................................... 879 24.12.1 I/O Port Status....................................................................................................... 879 24.12.2 Current Consumption when Waiting for Oscillation Stabilization ....................... 879 24.12.3 DTC Module Stop Mode ...................................................................................... 879
Section 25 List of Registers............................................................................... 881
25.1 25.2 25.3 25.4 25.5 Register Addresses (Address Order).................................................................................. 883 Register Bits....................................................................................................................... 897 Register States in Each Operating Mode ........................................................................... 909 Register Selection Condition ............................................................................................. 920 Register Addresses (Classification by Type of Module) ................................................... 933
Section 26 Electrical Characteristics ................................................................. 947
26.1 Absolute Maximum Ratings .............................................................................................. 947 26.2 DC Characteristics ............................................................................................................. 948
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26.3 AC Characteristics ............................................................................................................. 955 26.3.1 Clock Timing ........................................................................................................ 956 26.3.2 Control Signal Timing .......................................................................................... 958 26.3.3 Timing of On-Chip Peripheral Modules ............................................................... 959 26.3.4 A/D Conversion Characteristics ........................................................................... 971 26.4 Flash Memory Characteristics ........................................................................................... 972 26.5 Usage Notes ....................................................................................................................... 973
Appendix
A. B. C.
.........................................................................................................975
I/O Port States in Each Pin State........................................................................................ 975 Product Lineup................................................................................................................... 976 Package Dimensions .......................................................................................................... 977
Index
.........................................................................................................979
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Figures
Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Overview H8S/2114R Group Internal Block Diagram .................................................................. 3 H8S/2114R Group Pin Arrangement (TFP-144)........................................................... 4 Sample Design of Reset Signals with no Affection Each Other.................................. 17
Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 23 Figure 2.2 Stack Structure in Normal Mode ................................................................................. 23 Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 24 Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 25 Figure 2.5 Memory Map............................................................................................................... 26 Figure 2.6 CPU Internal Registers ................................................................................................ 27 Figure 2.7 Usage of General Registers ......................................................................................... 28 Figure 2.8 Stack............................................................................................................................ 29 Figure 2.9 General Register Data Formats (1).............................................................................. 32 Figure 2.9 General Register Data Formats (2).............................................................................. 33 Figure 2.10 Memory Data Formats............................................................................................... 34 Figure 2.11 Instruction Formats (Examples) ................................................................................ 47 Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ...................... 51 Figure 2.13 State Transitions ........................................................................................................ 55 Section 3 MCU Operating Modes Figure 3.1 Address Map ............................................................................................................... 68 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Exception Handling Reset Sequence (Mode 2)............................................................................................ 75 Stack Status after Exception Handling ........................................................................ 77 Operation when SP Value Is Odd................................................................................ 78
Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 80 Figure 5.2 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB (H8S/2140B Group Compatible Vector Mode: EIVS = 0).......................................... 95 Figure 5.3 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB (Extended Vector Mode: EIVS = 1) ............................................................................ 96 Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0 ............................................................ 100
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Figure 5.5 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE0 (Example of WUE15 to WUE8)................................................................................ 101 Figure 5.6 Block Diagram of Interrupt Control Operation ......................................................... 110 Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 .... 113 Figure 5.8 State Transition in Interrupt Control Mode 1 ............................................................ 114 Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 .... 116 Figure 5.10 Interrupt Exception Handling.................................................................................. 118 Figure 5.11 Interrupt Control for DTC ....................................................................................... 120 Figure 5.12 Block Diagram of Address Break Function ............................................................ 122 Figure 5.13 Examples of Address Break Timing........................................................................ 124 Figure 5.14 Conflict between Interrupt Generation and Disabling............................................. 125 Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of BSC ............................................................................................. 129 Section 7 Data Transfer Controller (DTC) Figure 7.1 Block Diagram of DTC ............................................................................................. 136 Figure 7.2 Block Diagram of DTC Activation Source Control .................................................. 143 Figure 7.3 DTC Register Information Location in Address Space............................................. 144 Figure 7.4 DTC Operation Flowchart......................................................................................... 147 Figure 7.5 Memory Mapping in Normal Mode .......................................................................... 148 Figure 7.6 Memory Mapping in Repeat Mode ........................................................................... 149 Figure 7.7 Memory Mapping in Block Transfer Mode .............................................................. 150 Figure 7.8 Chain Transfer Operation.......................................................................................... 151 Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ..................... 152 Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) ..................................... 153 Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 153 Section 8 I/O Ports Figure 8.1 Noise Cancel Circuit ................................................................................................. 184 Figure 8.2 Noise Cancel Operation ............................................................................................ 184 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 8-Bit PWM Timer (PWM) Block Diagram of PWM Timer................................................................................. 248 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ..... 255 Example of PWM Setting.......................................................................................... 256 Example when PWM is Used as D/A Converter....................................................... 256
Section 10 14-Bit PWM Timer (PWMX) Figure 10.1 PWMX (D/A) Block Diagram ................................................................................ 259 Figure 10.2 (1) DACNT Access Operation (1) [CPU DACNT(H'AA57) Writing] .............. 267 Figure 10.2 (2) DACNT Access Operation (2) [DACNT CPU(H'AA57) Reading].............. 268
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Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7
PWMX (D/A) Operation ......................................................................................... 269 Output Waveform (OS = 0, DADR corresponds to TL) .......................................... 272 Output Waveform (OS = 1, DADR corresponds to TH) .......................................... 273 D/A Data Register Configuration when CFS = 1 .................................................... 273 Output Waveform when DADR = H'0207 (OS = 1) ............................................... 274
Section 11 16-Bit Free-Running Timer (FRT) Figure 11.1 Block Diagram of 16-Bit Free-Running Timer ....................................................... 278 Figure 11.2 Example of Pulse Output......................................................................................... 289 Figure 11.3 Increment Timing with Internal Clock Source ........................................................ 290 Figure 11.4 Increment Timing with External Clock Source ....................................................... 290 Figure 11.5 Timing of Output Compare A Output ..................................................................... 291 Figure 11.6 Clearing of FRC by Compare-Match A Signal ....................................................... 291 Figure 11.7 Input Capture Input Signal Timing (Usual Case) .................................................... 292 Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read)....................... 292 Figure 11.9 Buffered Input Capture Timing ............................................................................... 293 Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) ...................................................... 294 Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting .................. 294 Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................. 295 Figure 11.13 Timing of Overflow Flag (OVF) Setting............................................................... 296 Figure 11.14 OCRA Automatic Addition Timing ...................................................................... 296 Figure 11.15 Timing of Input Capture Mask Signal Setting....................................................... 297 Figure 11.16 Timing of Input Capture Mask Signal Clearing .................................................... 297 Figure 11.17 Conflict between FRC Write and Clear................................................................. 299 Figure 11.18 Conflict between FRC Write and Increment ......................................................... 300 Figure 11.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Not Used) ............................................... 301 Figure 11.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Used) ...................................................... 302 Section 12 16-Bit Timer Pulse Unit (TPU) Figure 12.1 Block Diagram of TPU............................................................................................ 306 Figure 12.2 16-Bit Register Access Operation [Bus Master TCNT (16 Bits)] ...................... 333 Figure 12.3 8-Bit Register Access Operation [Bus Master TCR (Upper 8 Bits)].................. 334 Figure 12.4 8-Bit Register Access Operation [Bus Master TMDR (Lower 8 Bits)].............. 334 Figure 12.5 8-Bit Register Access Operation [Bus Master TCR and TMDR (16 Bits)] ....... 334 Figure 12.6 Example of Counter Operation Setting Procedure .................................................. 335 Figure 12.7 Free-Running Counter Operation ............................................................................ 336 Figure 12.8 Periodic Counter Operation..................................................................................... 337 Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match.............. 337 Figure 12.10 Example of 0 Output/1 Output Operation ............................................................. 338
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Figure 12.11 Figure 12.12 Figure 12.13 Figure 12.14 Figure 12.15 Figure 12.16 Figure 12.17 Figure 12.18 Figure 12.19 Figure 12.20 Figure 12.21 Figure 12.22 Figure 12.23 Figure 12.24 Figure 12.25 Figure 12.26 Figure 12.27 Figure 12.28 Figure 12.29 Figure 12.30 Figure 12.31 Figure 12.32 Figure 12.33 Figure 12.34 Figure 12.35 Figure 12.36 Figure 12.37 Figure 12.38 Figure 12.39 Figure 12.40 Figure 12.41 Figure 12.42 Figure 12.43 Figure 12.44 Figure 12.45 Figure 12.46 Figure 12.47 Figure 12.48 Figure 12.49 Figure 12.50
Example of Toggle Output Operation ................................................................... 338 Example of Input Capture Operation Setting Procedure ....................................... 339 Example of Input Capture Operation .................................................................... 340 Example of Synchronous Operation Setting Procedure ........................................ 341 Example of Synchronous Operation...................................................................... 342 Compare Match Buffer Operation......................................................................... 343 Input Capture Buffer Operation............................................................................. 343 Example of Buffer Operation Setting Procedure................................................... 344 Example of Buffer Operation (1) .......................................................................... 345 Example of Buffer Operation (2) .......................................................................... 346 Example of PWM Mode Setting Procedure .......................................................... 348 Example of PWM Mode Operation (1) ................................................................. 349 Example of PWM Mode Operation (2) ................................................................. 350 Example of PWM Mode Operation (3) ................................................................. 351 Example of Phase Counting Mode Setting Procedure........................................... 352 Example of Phase Counting Mode 1 Operation .................................................... 353 Example of Phase Counting Mode 2 Operation .................................................... 354 Example of Phase Counting Mode 3 Operation .................................................... 355 Example of Phase Counting Mode 4 Operation .................................................... 356 Count Timing in Internal Clock Operation............................................................ 360 Count Timing in External Clock Operation .......................................................... 360 Output Compare Output Timing ........................................................................... 361 Input Capture Input Signal Timing........................................................................ 361 Counter Clear Timing (Compare Match) .............................................................. 362 Counter Clear Timing (Input Capture) .................................................................. 362 Buffer Operation Timing (Compare Match) ......................................................... 363 Buffer Operation Timing (Input Capture) ............................................................. 363 TGI Interrupt Timing (Compare Match) ............................................................... 364 TGI Interrupt Timing (Input Capture) ................................................................... 365 TCIV Interrupt Setting Timing.............................................................................. 366 TCIU Interrupt Setting Timing.............................................................................. 366 Timing for Status Flag Clearing by CPU .............................................................. 367 Timing for Status Flag Clearing by DTC Activation ............................................ 367 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 368 Conflict between TCNT Write and Clear Operations ........................................... 369 Conflict between TCNT Write and Increment Operations.................................... 370 Conflict between TGR Write and Compare Match ............................................... 370 Conflict between Buffer Register Write and Compare Match .............................. 371 Conflict between TGR Read and Input Capture.................................................... 372 Conflict between TGR Write and Input Capture................................................... 373
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Figure 12.51 Conflict between Buffer Register Write and Input Capture .................................. 374 Figure 12.52 Conflict between Overflow and Counter Clearing ................................................ 375 Figure 12.53 Conflict between TCNT Write and Overflow ....................................................... 376 Section 13 8-Bit Timer (TMR) Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 379 Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) .......................................... 380 Figure 13.3 Pulse Output Example ............................................................................................. 397 Figure 13.4 Count Timing for Internal Clock Input.................................................................... 398 Figure 13.5 Count Timing for External Clock Input (Both Edges) ............................................ 398 Figure 13.6 Timing of CMF Setting at Compare-Match ............................................................ 399 Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal............................. 399 Figure 13.8 Timing of Counter Clear by Compare-Match ......................................................... 400 Figure 13.9 Timing of Counter Clear by External Reset Input................................................... 400 Figure 13.10 Timing of OVF Flag Setting.................................................................................. 401 Figure 13.11 Timing of Input Capture Operation ....................................................................... 404 Figure 13.12 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) ............................. 405 Figure 13.13 Conflict between TCNT Write and Clear.............................................................. 407 Figure 13.14 Conflict between TCNT Write and Count-Up....................................................... 408 Figure 13.15 Conflict between TCOR Write and Compare-Match ............................................ 409 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Watchdog Timer (WDT) Block Diagram of WDT .......................................................................................... 414 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 421 Interval Timer Mode Operation............................................................................... 421 OVF Flag Set Timing .............................................................................................. 422 Output Timing of RESO signal ............................................................................... 422 Writing to TCNT and TCSR (WDT_0)................................................................... 424 Conflict between TCNT Write and Increment ........................................................ 425 Sample Circuit for Resetting the System by the RESO Signal................................ 426
Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.1 Block Diagram of SCI............................................................................................. 429 Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 455 Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 457 Figure 15.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) ............................................................................................. 458 Figure 15.5 Sample SCI Initialization Flowchart ....................................................................... 459 Figure 15.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 460
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Figure 15.7 Sample Serial Transmission Flowchart ................................................................... 461 Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 462 Figure 15.9 Sample Serial Reception Flowchart (1)................................................................... 464 Figure 15.9 Sample Serial Reception Flowchart (2)................................................................... 465 Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) .......................................... 467 Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 468 Figure 15.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 469 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 470 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 471 Figure 15.14 Data Format in Synchronous Communication (LSB-First)................................... 472 Figure 15.15 Sample SCI Initialization Flowchart ..................................................................... 473 Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode .................. 475 Figure 15.17 Sample Serial Transmission Flowchart ................................................................. 476 Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode .................... 477 Figure 15.19 Sample Serial Reception Flowchart ...................................................................... 478 Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 480 Figure 15.21 Pin Connection for Smart Card Interface .............................................................. 481 Figure 15.22 Data Formats in Normal Smart Card Interface Mode ........................................... 482 Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 482 Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1) .................................................... 482 Figure 15.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate)............................................. 484 Figure 15.26 Data Re-transfer Operation in SCI Transmission Mode........................................ 486 Figure 15.27 TEND Flag Set Timings during Transmission ...................................................... 486 Figure 15.28 Sample Transmission Flowchart ........................................................................... 487 Figure 15.29 Data Re-transfer Operation in SCI Reception Mode............................................. 488 Figure 15.30 Sample Reception Flowchart................................................................................. 489 Figure 15.31 Clock Output Fixing Timing ................................................................................. 490 Figure 15.32 Clock Stop and Restart Procedure......................................................................... 491 Figure 15.33 IrDA Block Diagram............................................................................................. 492 Figure 15.34 IrDA Transmission and Reception ........................................................................ 493 Figure 15.35 Sample Transmission using DTC in Clocked Synchronous Mode........................ 499 Figure 15.36 Sample Flowchart for Mode Transition during Transmission............................... 500 Figure 15.37 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ 501 Figure 15.38 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock) ..................................................................................................... 501 Figure 15.39 Sample Flowchart for Mode Transition during Reception .................................... 502
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Figure 15.40 Switching from SCK Pins to Port Pins.................................................................. 503 Figure 15.41 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins.......... 504 I2C Bus Interface (IIC) Block Diagram of I2C Bus Interface........................................................................ 507 I2C Bus Interface Connections (Example: This LSI as Master) .............................. 508 I2C Bus Data Format (I2C Bus Format)................................................................... 535 I2C Bus Data Format (Serial Format) ...................................................................... 535 I2C Bus Timing........................................................................................................ 536 Sample Flowchart for IIC Initialization................................................................... 537 Sample Flowchart for Operations in Master Transmit Mode .................................. 538 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)....... 540 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ................................................................................................. 541 Figure 16.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) ............. 542 Figure 16.11 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) ............................................................................ 544 Figure 16.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) ............................................................................ 544 Figure 16.13 Sample Flowchart for Operations in Master Receive Mode (receiving multiple bytes) (WAIT = 1).................................................................. 546 Figure 16.14 Sample Flowchart for Operations in Master Receive Mode (receiving a single byte) (WAIT = 1) .................................................................... 547 Figure 16.15 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) ............................................................................ 550 Figure 16.16 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1) ............................................................................ 550 Figure 16.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) ............... 552 Figure 16.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1) ... 554 Figure 16.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) ... 555 Figure 16.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) ............... 556 Figure 16.21 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0)............................................................................ 558 Figure 16.22 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0)............................................................................ 558 Figure 16.23 Sample Flowchart for Slave Transmit Mode......................................................... 559 Figure 16.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) ......................... 561 Figure 16.25 IRIC Setting Timing and SCL Control (1) ............................................................ 562 Figure 16.26 IRIC Setting Timing and SCL Control (2) ............................................................ 563 Figure 16.27 IRIC Setting Timing and SCL Control (3) ............................................................ 564 Figure 16.28 Block Diagram of Noise Canceller........................................................................ 567 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 Figure 16.9
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Figure 16.29 Notes on Reading Master Receive Data ................................................................ 573 Figure 16.30 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing................................................................................................................... 574 Figure 16.31 Stop Condition Issuance Timing ........................................................................... 575 Figure 16.32 IRIC Flag Clearing Timing when WAIT = 1 ........................................................ 576 Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode........................... 577 Figure 16.34 TRS Bit Set Timing in Slave Mode....................................................................... 578 Figure 16.35 Diagram of Erroneous Operation when Arbitration is Lost .................................. 580 Section 17 Keyboard Buffer Control Unit (KBU) Figure 17.1 Block Diagram of KBU........................................................................................... 582 Figure 17.2 KBU Connection ..................................................................................................... 583 Figure 17.3 Sample Receive Processing Flowchart.................................................................... 594 Figure 17.4 Receive Timing ....................................................................................................... 595 Figure 17.5 Sample Transmit Processing Flowchart .................................................................. 596 Figure 17.6 Transmit Timing...................................................................................................... 597 Figure 17.7 (1) Sample Receive Abort Processing Flowchart.................................................... 598 Figure 17.7 (2) Sample Receive Abort Processing Flowchart.................................................... 599 Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover) Timing..................................................................................................................... 599 Figure 17.9 KCLKI and KDI Read Timing ................................................................................ 600 Figure 17.10 KCLKO and KDO Write Timing .......................................................................... 601 Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing ..................... 602 Figure 17.12 Receive Counter and KBBR Data Load Timing ................................................... 603 Figure 17.13 Receive Timing and KCLK................................................................................... 604 Figure 17.14 Example of KCLK Input Fall Interrupt Operation ................................................ 605 Figure 17.15 Timing of First KCLK Interrupt............................................................................ 606 Figure 17.16 First KCLK Interrupt Path..................................................................................... 608 Figure 17.17 Interrupt Timing in Software Standby Mode, Watch Mode, and Subsleep Mode. 609 Figure 17.18 Internal Flag of First KCLK Falling Interrupt in Software Standby mode, Watch mode, and Subsleep mode.......................................................................... 610 Figure 17.19 KBIOE Setting and KCLK Falling Edge Detection Timing ................................. 611 Figure 17.20 KDO Output .......................................................................................................... 612 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 LPC Interface (LPC) Block Diagram of LPC............................................................................................ 615 Typical LFRAME Timing....................................................................................... 679 Abort Mechanism.................................................................................................... 679 GA20 Output........................................................................................................... 681 Power-Down State Termination Timing ................................................................. 686 SERIRQ Timing...................................................................................................... 687
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Figure 18.7 Clock Start Request Timing .................................................................................... 689 Figure 18.8 Example of Command Space Setting ...................................................................... 692 Figure 18.9 Example of Flash Memory Address Translation ..................................................... 700 Figure 18.10 Example of On-Chip RAM Address Translation .................................................. 701 Figure 18.11 Example 1 of Address Space Priority.................................................................... 703 Figure 18.12 Example 2 of Address Space Priority.................................................................... 704 Figure 18.13 Flash Memory Protection ...................................................................................... 706 Figure 18.14 Protected Address Space in On-Chip RAM .......................................................... 707 Figure 18.15 Example of Programming Flash Memory ............................................................. 708 Figure 18.16 Example of Erasing Flash Memory ....................................................................... 709 Figure 18.17 HIRQ Flowchart (Example of Channel 1)............................................................. 713 Section 19 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.5 Figure 19.6 Figure 19.7 Figure 19.8 A/D Converter Block Diagram of A/D Converter ........................................................................... 718 A/D Conversion Timing .......................................................................................... 725 External Trigger Input Timing ................................................................................ 726 A/D Conversion Accuracy Definitions.................................................................... 728 A/D Conversion Accuracy Definitions.................................................................... 728 Example of Analog Input Circuit ............................................................................ 729 Example of Analog Input Protection Circuit ........................................................... 731 Analog Input Pin Equivalent Circuit ....................................................................... 731
Section 21 Flash Memory (0.18-m F-ZTAT Version) Figure 21.1 Block Diagram of Flash Memory............................................................................ 736 Figure 21.2 Mode Transition for Flash Memory ........................................................................ 737 Figure 21.3 Flash Memory Configuration .................................................................................. 739 Figure 21.4 Block Division of User MAT (1) ............................................................................ 740 Figure 21.4 Block Division of User MAT (2) ............................................................................ 741 Figure 21.5 Overview of User Procedure Program..................................................................... 742 Figure 21.6 System Configuration in Boot Mode....................................................................... 765 Figure 21.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 765 Figure 21.8 Overview of Boot Mode State Transition Diagram................................................. 767 Figure 21.9 Programming/Erasing Overview Flow.................................................................... 768 Figure 21.10 RAM Map when Programming/Erasing is Executed ............................................ 769 Figure 21.11 Programming Procedure........................................................................................ 770 Figure 21.12 Erasing Procedure.................................................................................................. 776 Figure 21.13 Repeating Procedure of Erasing and Programming............................................... 778 Figure 21.14 Procedure for Programming User MAT in User Boot Mode ................................ 780 Figure 21.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 782 Figure 21.16 Transitions to Error-Protection State..................................................................... 794 Figure 21.17 Switching between User MAT and User Boot MAT ............................................ 795
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Figure 21.18 Figure 21.19 Figure 21.20 Figure 21.21 Figure 21.22 Figure 21.23 Figure 21.24 Section 22 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Figure 22.5
Memory Map in Programmer Mode...................................................................... 796 Boot Program States.............................................................................................. 798 Bit-Rate-Adjustment Sequence ............................................................................. 799 Communication Protocol Format .......................................................................... 800 Sequence of New Bit Rate Selection..................................................................... 811 Programming Sequence......................................................................................... 814 Erasure Sequence .................................................................................................. 818 Boundary Scan (JTAG) JTAG Block Diagram.............................................................................................. 828 TAP Controller State Transitions ............................................................................ 843 Reset Signal Circuit without Reset Signal Interference .......................................... 847 Serial Data Input/Output (1).................................................................................... 848 Serial Data Input/Output (2).................................................................................... 848
Section 23 Clock Pulse Generator Figure 23.1 Block Diagram of Clock Pulse Generator ............................................................... 849 Figure 23.2 Typical Connection to Crystal Resonator................................................................ 850 Figure 23.3 Equivalent Circuit of Crystal Resonator.................................................................. 850 Figure 23.4 Example of External Clock Input ............................................................................ 851 Figure 23.5 External Clock Input Timing................................................................................... 852 Figure 23.6 Timing of External Clock Output Stabilization Delay Time................................... 853 Figure 23.7 Subclock Input from EXCL Pin and ExEXCL Pin ................................................. 855 Figure 23.8 Subclock Input Timing............................................................................................ 856 Figure 23.9 Handling of X1 and X2 Pins ................................................................................... 857 Figure 23.10 Note on Board Design of Oscillator Section ......................................................... 857 Section 24 Figure 24.1 Figure 24.2 Figure 24.3 Figure 24.4 Section 26 Figure 26.1 Figure 26.2 Figure 26.3 Figure 26.4 Figure 26.5 Figure 26.6 Figure 26.7 Figure 26.8 Power-Down Modes Mode Transition Diagram ....................................................................................... 867 Medium-Speed Mode Timing ................................................................................. 871 Software Standby Mode Application Example ....................................................... 873 Hardware Standby Mode Timing ............................................................................ 874 Electrical Characteristics Darlington Transistor Drive Circuit (Example)....................................................... 954 LED Drive Circuit (Example) ................................................................................. 954 Output Load Circuit ................................................................................................ 955 System Clock Timing.............................................................................................. 956 Oscillation Stabilization Timing.............................................................................. 957 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 957 Reset Input Timing.................................................................................................. 958 Interrupt Input Timing............................................................................................. 959
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Figure 26.9 I/O Port Input/Output Timing.................................................................................. 961 Figure 26.10 FRT Input/Output Timing ...................................................................................... 961 Figure 26.11 FRT Clock Input Timing ....................................................................................... 961 Figure 26.12 TPU Input/Output Timing ..................................................................................... 962 Figure 26.13 TPU Clock Input Timing....................................................................................... 962 Figure 26.14 8-Bit Timer Output Timing ................................................................................... 962 Figure 26.15 8-Bit Timer Clock Input Timing ........................................................................... 962 Figure 26.16 8-Bit Timer Reset Input Timing ............................................................................ 963 Figure 26.17 PWM, PWMX Output Timing .............................................................................. 963 Figure 26.18 SCK Clock Input Timing....................................................................................... 963 Figure 26.19 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 963 Figure 26.20 A/D Converter External Trigger Input Timing...................................................... 964 Figure 26.21 WDT Output Timing (RESO) ............................................................................... 964 Figure 26.22 Keyboard Buffer Control Unit Timing .................................................................. 965 Figure 26.23 I2C Bus Interface Input/Output Timing ................................................................. 967 Figure 26.24 LPC Interface Timing............................................................................................ 968 Figure 26.25 Test Conditions for Tester ..................................................................................... 968 Figure 26.26 JTAG ETCK Timing ............................................................................................. 969 Figure 26.27 Reset Hold Timing ................................................................................................ 970 Figure 26.28 JTAG Input/Output Timing................................................................................... 970 Figure 26.29 Connection of VCL Capacitor............................................................................... 973 Appendix Figure C.1 Package Dimensions (TFP-144) ............................................................................... 977
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Tables
Section 1 Overview Table 1.1 H8S/2114R Group Pin Arrangement in Each Operating Mode ................................ 5 Table 1.2 Pin Functions .......................................................................................................... 10 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 35 Table 2.2 Operation Notation ................................................................................................. 36 Table 2.3 Data Transfer Instructions....................................................................................... 37 Table 2.4 Arithmetic Operations Instructions (1) ................................................................... 38 Table 2.4 Arithmetic Operations Instructions (2) ................................................................... 39 Table 2.5 Logic Operations Instructions................................................................................. 40 Table 2.6 Shift Instructions..................................................................................................... 41 Table 2.7 Bit Manipulation Instructions (1)............................................................................ 42 Table 2.7 Bit Manipulation Instructions (2)............................................................................ 43 Table 2.8 Branch Instructions ................................................................................................. 44 Table 2.9 System Control Instructions.................................................................................... 45 Table 2.10 Block Data Transfer Instructions ............................................................................ 46 Table 2.11 Addressing Modes .................................................................................................. 48 Table 2.12 Absolute Address Access Ranges ........................................................................... 50 Table 2.13 Effective Address Calculation (1)........................................................................... 52 Table 2.13 Effective Address Calculation (2)........................................................................... 53 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection ............................................................................ 59 Section 4 Exception Handling Table 4.1 Exception Types and Priority.................................................................................. 69 Table 4.2 Exception Handling Vector Table (H8S/2140B Group Compatible Vector Mode) ...................................................... 70 Table 4.3 Exception Handling Vector Table (Extended Vector Mode).................................. 72 Table 4.4 Status of CCR after Trap Instruction Exception Handling ..................................... 76 Section 5 Interrupt Controller Table 5.1 Pin Configuration.................................................................................................... 81 Table 5.2 Correspondence between Interrupt Source and ICR (H8S/2140B Group Compatible Vector Mode: EIVS = 0) ..................................... 83 Table 5.3 Correspondence between Interrupt Source and ICR (Extended Vector Mode: EIVS = 1) ....................................................................... 84
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Table 5.4 Table 5.5 Table 5.6 Table 5.7 Table 5.8 Table 5.9 Table 5.10
Interrupt Sources, Vector Addresses, and Interrupt Priorities (H8S/2140B Group Compatible Vector Mode) .................................................... 103 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode) ...................................................................................... 106 Interrupt Control Modes ....................................................................................... 109 Interrupts Selected in Each Interrupt Control Mode ............................................. 111 Operations and Control Signal Functions in Each Interrupt Control Mode.......... 112 Interrupt Response Times ..................................................................................... 119 Interrupt Source Selection and Clearing Control .................................................. 121
Section 7 Data Transfer Controller (DTC) Table 7.1 Correspondence between Interrupt Sources and DTCER ..................................... 141 Table 7.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 145 Table 7.3 Register Functions in Normal Mode..................................................................... 148 Table 7.4 Register Functions in Repeat Mode...................................................................... 149 Table 7.5 Register Functions in Block Transfer Mode ......................................................... 150 Table 7.6 DTC Execution Status .......................................................................................... 154 Table 7.7 Number of States Required for Each Execution Status ........................................ 154 Section 8 I/O Ports Table 8.1 Port Functions....................................................................................................... 159 Table 8.2 Port 1 Input Pull-Up MOS States.......................................................................... 166 Table 8.3 Port 2 Input Pull-Up MOS States.......................................................................... 170 Table 8.4 Port 3 Input Pull-Up MOS States.......................................................................... 173 Table 8.5 Port 6 Input Pull-Up MOS States.......................................................................... 188 Table 8.6 Port 9 Input Pull-Up MOS States.......................................................................... 200 Table 8.7 Port B Input Pull-Up MOS States......................................................................... 208 Table 8.8 Port C Input Pull-Up MOS States......................................................................... 216 Table 8.9 Port D Input Pull-Up MOS States......................................................................... 224 Table 8.10 Port E Input Pull-Up MOS States ......................................................................... 226 Table 8.11 Port F Input Pull-Up MOS States ......................................................................... 232 Section 9 8-Bit PWM Timer (PWM) Table 9.1 Pin Configuration.................................................................................................. 249 Table 9.2 Internal Clock Selection........................................................................................ 251 Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency when = 20 MHz ...................................................................................................................... 251 Table 9.4 Duty Cycle of Basic Pulse .................................................................................... 254 Table 9.5 Position of Pulses Added to Basic Pulses ............................................................. 255
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Section 10 14-Bit PWM Timer (PWMX) Table 10.1 Pin Configuration.................................................................................................. 260 Table 10.2 Clock Select of PWMX ........................................................................................ 265 Table 10.3 Reading/Writing to 16-bit Registers ..................................................................... 267 Table 10.4 Settings and Operation (Examples when = 20 MHz)......................................... 270 Table 10.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)................ 275 Section 11 16-Bit Free-Running Timer (FRT) Table 11.1 Pin Configuration.................................................................................................. 279 Table 11.2 FRT Interrupt Sources .......................................................................................... 298 Table 11.3 Switching of Internal Clock and FRC Operation .................................................. 303 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.1 TPU Functions ...................................................................................................... 307 Table 12.2 Pin Configuration.................................................................................................. 309 Table 12.3 CCLR2 to CCLR0 (channel 0) ............................................................................. 312 Table 12.4 CCLR2 to CCLR0 (channels 1 and 2) .................................................................. 312 Table 12.5 TPSC2 to TPSC0 (channel 0) ............................................................................... 313 Table 12.6 TPSC2 to TPSC0 (channel 1) ............................................................................... 313 Table 12.7 TPSC2 to TPSC0 (channel 2) ............................................................................... 314 Table 12.8 MD3 to MD0 ........................................................................................................ 316 Table 12.9 TIORH_0 (channel 0) ........................................................................................... 318 Table 12.10 TIORH_0 (channel 0) ....................................................................................... 319 Table 12.11 TIORL_0 (channel 0)........................................................................................ 320 Table 12.12 TIORL_0 (channel 0)........................................................................................ 321 Table 12.13 TIOR_1 (channel 1) .......................................................................................... 322 Table 12.14 TIOR_1 (channel 1) .......................................................................................... 323 Table 12.15 TIOR_2 (channel 2) .......................................................................................... 324 Table 12.16 TIOR_2 (channel 2) .......................................................................................... 325 Table 12.17 Register Combinations in Buffer Operation ..................................................... 343 Table 12.18 PWM Output Registers and Output Pins .......................................................... 348 Table 12.19 Phase Counting Mode Clock Input Pins ........................................................... 352 Table 12.20 Up/Down-Count Conditions in Phase Counting Mode 1.................................. 353 Table 12.21 Up/Down-Count Conditions in Phase Counting Mode 2.................................. 354 Table 12.22 Up/Down-Count Conditions in Phase Counting Mode 3.................................. 355 Table 12.23 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 356 Table 12.24 TPU Interrupts .................................................................................................. 358 Section 13 8-Bit Timer (TMR) Table 13.1 Pin Configuration.................................................................................................. 381 Table 13.2 Clock Input to TCNT and Count Condition (1) .................................................... 386
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Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 13.6 Table 13.7
Clock Input to TCNT and Count Condition (2).................................................... 387 Registers Accessible by TMR_X/TMR_Y ........................................................... 396 Input Capture Signal Selection ............................................................................. 405 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ....... 406 Timer Output Priorities......................................................................................... 410 Switching of Internal Clocks and TCNT Operation ............................................. 411
Section 14 Watchdog Timer (WDT) Table 14.1 Pin Configuration.................................................................................................. 415 Table 14.2 WDT Interrupt Source .......................................................................................... 423 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.1 Pin Configuration.................................................................................................. 430 Table 15.2 Relationships between N Setting in BRR and Bit Rate B..................................... 445 Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 446 Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 448 Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 450 Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 450 Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 451 Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 452 Table 15.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372) ........................................................ 452 Table 15.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372).................................................................. 452 Table 15.10 Serial Transfer Formats (Asynchronous Mode)................................................ 456 Table 15.11 SSR Status Flags and Receive Data Handling .................................................. 463 Table 15.12 IrCKS2 to IrCKS0 Bit Settings......................................................................... 495 Table 15.13 SCI Interrupt Sources........................................................................................ 496 Table 15.14 SCI Interrupt Sources........................................................................................ 497 Section 16 I2C Bus Interface (IIC) Table 16.1 Pin Configuration.................................................................................................. 509 Table 16.2 Communication Format ........................................................................................ 513 Table 16.3 I2C Transfer Rate .................................................................................................. 516 Table 16.4 Flags and Transfer States (Master Mode) ............................................................. 522 Table 16.5 Flags and Transfer States (Slave Mode) ............................................................... 524 Table 16.6 I2C Bus Data Format Symbols.............................................................................. 536 Table 16.7 Operation by Using DTC...................................................................................... 566 Table 16.8 IIC Interrupt Sources ............................................................................................ 569 Table 16.9 I2C Bus Timing (SCL and SDA Outputs)............................................................. 570 Table 16.10 Permissible SCL Rise Time (tsr) Values ........................................................... 571 Table 16.11 I2C Bus Timing (with Maximum Influence of tSr/tSf)........................................ 572
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Section 17 Keyboard Buffer Control Unit (KBU) Table 17.1 Pin Configuration.................................................................................................. 584 Section 18 LPC Interface (LPC) Table 18.1 Pin Configuration.................................................................................................. 616 Table 18.2 LPC I/O Cycle ...................................................................................................... 678 Table 18.3 GA20 (P81) Setting/Clearing Timing ................................................................... 680 Table 18.4 Fast Gate A20 Output Signals............................................................................... 682 Table 18.5 Scope of LPC Interface Pin Shutdown ................................................................. 684 Table 18.6 Scope of Initialization in Each LPC interface Mode............................................. 685 Table 18.7 Serialized Interrupt Transfer Cycle Frame Configuration .................................... 688 Table 18.8 LPC Memory Cycle .............................................................................................. 690 Table 18.9 FW Memory Cycle (Byte Transfer)...................................................................... 691 Table 18.10 List of LPC/FW Memory Access Commands .................................................. 693 Table 18.11 List of Factors that Prevents SYNC Field being Sent Back.............................. 697 Table 18.12 Receive Complete Interrupts and Error Interrupt.............................................. 710 Table 18.13 HIRQ Setting and Clearing Conditions............................................................. 712 Table 18.14 Host Address Example...................................................................................... 715 Section 19 A/D Converter Table 19.1 Pin Configuration.................................................................................................. 719 Table 19.2 Analog Input Channels and Corresponding ADDR.............................................. 720 Table 19.3 A/D Conversion Time (Single Mode)................................................................... 726 Table 19.4 A/D Converter Interrupt Source............................................................................ 727 Section 21 Flash Memory (0.18-m F-ZTAT Version) Table 21.1 Comparison of Programming Modes.................................................................... 738 Table 21.2 Pin Configuration.................................................................................................. 744 Table 21.3 Register/Parameter and Target Mode ................................................................... 745 Table 21.4 Parameters and Target Modes............................................................................... 754 Table 21.5 On-Board Programming Mode Setting ................................................................. 764 Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI......... 766 Table 21.7 Executable MAT................................................................................................... 784 Table 21.8 (1) Usable Area for Programming in User Program Mode................................. 785 Table 21.8 (2) Usable Area for Erasure in User Program Mode .......................................... 787 Table 21.8 (3) Usable Area for Programming in User Boot Mode....................................... 788 Table 21.8 (4) Usable Area for Erasure in User Boot Mode ................................................ 790 Table 21.9 Hardware Protection ............................................................................................. 792 Table 21.10 Software Protection........................................................................................... 793 Table 21.11 Inquiry and Selection Commands ..................................................................... 801 Table 21.12 Programming/Erasing Commands .................................................................... 813 Table 21.13 Status Code ....................................................................................................... 823
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Table 21.14
Error Code ........................................................................................................ 823
Section 22 Boundary Scan (JTAG) Table 22.1 Pin Configuration.................................................................................................. 829 Table 22.2 JTAG Register Serial Transfer.............................................................................. 830 Table 22.3 Correspondence between Pins and Boundary Scan Register ................................ 832 Section 23 Clock Pulse Generator Table 23.1 Damping Resistor Values ..................................................................................... 850 Table 23.2 Crystal Resonator Parameters ............................................................................... 851 Table 23.3 External Clock Input Conditions .......................................................................... 852 Table 23.4 External Clock Output Stabilization Delay Time ................................................. 853 Table 23.5 Subclock Input Conditions.................................................................................... 855 Section 24 Power-Down Modes Operating Frequency and Wait Time.................................................................... 862 Table 24.1 Table 24.2 LSI Internal States in Each Operating Mode ........................................................ 868 Section 26 Electrical Characteristics Table 26.1 Absolute Maximum Ratings ................................................................................. 947 Table 26.2 DC Characteristics (1) .......................................................................................... 948 Table 26.2 DC Characteristics (2) .......................................................................................... 950 Table 26.2 DC Characteristics (3) Using LPC Function......................................................... 951 Table 26.3 Permissible Output Currents................................................................................. 952 Table 26.4 Bus Drive Characteristics ..................................................................................... 953 Table 26.5 Clock Timing ........................................................................................................ 956 Table 26.6 Control Signal Timing .......................................................................................... 958 Table 26.7 Timing of On-Chip Peripheral Modules ............................................................... 960 Table 26.8 KBU Bus Timing.................................................................................................. 964 Table 26.9 I2C Bus Timing ..................................................................................................... 966 Table 26.10 LPC Timing ...................................................................................................... 967 Table 26.11 JTAG Timing.................................................................................................... 969 Table 26.12 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) .............................................. 971 Table 26.13 Flash Memory Characteristics .......................................................................... 972 Appendix Table A.1 I/O Port States in Each Pin State........................................................................... 975
Rev. 3.00 Jul. 14, 2005 Page xlviii of xlviii
Section 1 Overview
Section 1 Overview
1.1 Overview
* 16-bit high-speed H8S/2000 CPU Upward-compatible with the H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions * Various peripheral functions Data transfer controller (DTC) 8-bit PWM timer (PWM) 14-bit PWM timer (PWMX) 16-bit timer pulse unit (TPU) 16-bit free-running timer (FRT) 8-bit timer (TMR) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI) I2C bus interface (IIC) Keyboard buffer control unit (KBU) LPC interface (LPC) 10-bit A/D converter Boundary scan (JTAG) Clock pulse generator * On-chip memory
ROM Type Flash memory version Model R4F2114R ROM 1 Mbyte RAM 8 kbytes Remarks Being developed
* General I/O ports I/O pins: 106 Input-only pins: 13 * Supports various power-down states * Compact package
Rev. 3.00 Jul. 14, 2005 Page 1 of 986 REJ09B0098-0300
Section 1 Overview
Package TQFP-144
Code TFP-144
Body Size 16.0 x 16.0 mm
Pin Pitch 0.4 mm
Rev. 3.00 Jul. 14, 2005 Page 2 of 986 REJ09B0098-0300
Section 1 Overview
1.2
Internal Block Diagram
VCC VCC VCC VCL VSS VSS VSS VSS VSS X1 X2 RES XTAL EXTAL MD2 MD1 MD0 FWE NMI STBY RESO ETRST PE0/LID3 PE1*/ETCK PE2*/ETDI PE3*/ETDO PE4*/ETMS P90 /IRQ2/ADTRG P91/IRQ1 P92/IRQ0 P93/IRQ12 P94/IRQ13 P95/IRQ14 P96//EXCL P97/IRQ15/SDA0 P60/KIN0/FTCI/TMIX P61/KIN1/FTOA P62/KIN2/FTIA/TMIY P63/KIN3/FTIB P64/KIN4/FTIC P65/KIN5/FTID P66/IRQ6/KIN6/FTOB P67/IRQ7/KIN7/TMOX
Port E Port 9 Port 6
Clock pulse generator
H8S/2000CPU
PA0/KIN8 PA1/KIN9 PA2/KIN10/PS2AC PA3/KIN11/PS2AD PA4/KIN12/PS2BC PA5/KIN13/PS2BD PA6/KIN14/PS2CC PA7/KIN15/PS2CD P20/PW8 P21/PW9 P22/PW10 P23/PW11 P24/PW12 P25/PW13 P26/PW14 P27/PW15 P10 P11 P12 P13 P14 P15 P16 P17 P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37/SERIRQ PB0/WUE0/LSMI PB1/WUE1/LSCI PB2/WUE2 PB3/WUE3/DLFRAME PB4/WUE4/DLAD3 PB5/WUE5/DLAD2 PB6/WUE6/DLAD1 PB7/WUE7/DLAD0 P50/ExEXCL P51/TMOY P52/ExIRQ6/SCL0
DTC ROM (flash memory)
LPC RAM
Port 1 Port 5 Port B Port 3
Data bus
Interrupt controller
16-bit FRT
WDT x 2 channels
8-bit timer x 4 channels
KBU x 3 channels
SCI x 2 channels (IrDA x 1 channel)
8-bit PWM
P40/TMCI0/TxD2/DSERIRQ P41/TMO0/RxD2/DCLKRUN P42/ExIRQ7/TMRI0/SCK2/SDA1 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1/IrTxD P85/IRQ4/RxD1/IrRxD P86/IRQ5/SCK1/SCL1
IIC x 2 channels
Port 4
14-bit PWM x 2 channels
Port 2 Address bus
Port A
Bus controller
10-bit A/D converter
Boundary scan (JTAG)
TPU x 3 channels
Port F
Port D
Internal data bus
Internal address bus
PD0/TIOCA0 PD1/TIOCB0 PD2/TIOCC0/TCLKA PD3/TIOCD0/TCLKB PD4/TIOCA1 PD5/TIOCB1/TCLKC PD6/TIOCA2 PD7/TIOCB2/TCLKD PF0/IRQ8 PF1/IRQ9 PF2/IRQ10 PF3/IRQ11/ExTMOX PF4/ExPW12 PF5/ExPW13 PF6/ExPW14 PF7/ExPW15
Note: * Not supported by the system development tool (emulator).
Figure 1.1 H8S/2114R Group Internal Block Diagram
Rev. 3.00 Jul. 14, 2005 Page 3 of 986 REJ09B0098-0300
Port 8
Port 7
Port G
Port C
PC0/WUE8 PC1/WUE9 PC2/WUE10 PC3/WUE11 PC4/WUE12 PC5/WUE13 PC6/WUE14/LDRQ PC7/WUE15/DLDRQ
P70/ExIRQ0/AN0 P71/ExIRQ1/AN1 P72/ExIRQ2/AN2 P73/ExIRQ3/AN3 P74/ExIRQ4/AN4 P75/ExIRQ5/AN5 P76/AN6 P77/AN7
PG0/ExIRQ8/ExTMCI0 PG1/ExIRQ9/ExTMCI1 PG2/ExIRQ10/ExTMIX PG3/ExIRQ11/ExTMIY PG4/ExIRQ12/ExSDAA PG5/ExIRQ13/ExSCLA PG6/ExIRQ14/ExSDAB PG7/ExIRQ15/ExSCLB
AVref AVCC AVSS
Section 1 Overview
1.3
1.3.1
Pin Description
Pin Arrangement
P13 P14 P15 P16 P17 P20/PW8 P21/PW9 P22/PW10 P23/PW11 P24/PW12 P25/PW13 P26/PW14 P27/PW15 VSS PC0/WUE8 PC1/WUE9 PC2/WUE10 PC3/WUE11 PC4/WUE12 PC5/WUE13 PC6/WUE14/LDRQ PC7/WUE15/DLDRQ VCC P67/IRQ7/KIN7/TMOX P66/IRQ6/KIN6/FTOB P65/KIN5/FTID P64/KIN4/FTIC P63/KIN3/FTIB P62/KIN2/FTIA/TMIY P61/KIN1/FTOA P60/KIN0/FTCI/TMIX AVref AVCC P77/AN7 P76/AN6 P75/ExIRQ5/AN5
P12 P11 VSS P10 PB7/WUE7/DLAD0 PB6/WUE6/DLAD1 PB5/WUE5/DLAD2 PB4/WUE4/DLAD3 PB3/WUE3/DLFRAME PB2/WUE2 PB1/WUE1/LSCI PB0/WUE0/LSMI P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37/SERIRQ P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1/IrTxD P85/IRQ4/RxD1/IrRxD P86/IRQ5/SCK1/SCL1 P40/TMCI0/TxD2/DSERIRQ P41/TMO0/RxD2/DCLKRUN P42/ExIRQ7/TMRI0/SCK2/SDA1 VSS X1 X2 RESO XTAL EXTAL
108107 106 105 104103 102101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 72 110 71 111 70 112 69 113 68 114 67 115 66 116 65 117 64 118 63 119 62 120 61 121 60 122 59 123 58 124 57 125 56 TFP-144 126 55 127 54 (Top View) 128 53 52 129 130 51 131 50 132 49 133 48 134 47 135 46 136 45 137 44 138 43 139 42 140 41 141 40 142 39 143 38 144 37 1 2 3 4 5 6 7 8 9 10 11 12 1314 15 16 1718 19 20 21 22 2324 25 26 27 28 29 30 31 32 33 34 35 36 VCC P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VSS RES MD1 MD0 NMI STBY VCL P52/ExIRQ6/SCL0 P51/TMOY P50/ExEXCL P97/IRQ15/SDA0 P96//EXCL P95/IRQ14 P94/IRQ13 P93/IRQ12 P92/IRQ0 P91/IRQ1 P90 /IRQ2/ADTRG MD2 FWE ETRST PE4*/ETMS PE3*/ETDO PE2*/ETDI PE1*/ETCK PE0/LID3 PA7/KIN15/PS2CD PA6/KIN14/PS2CC PA5/KIN13/PS2BD VCC
P74/ExIRQ4/AN4 P73/ExIRQ3/AN3 P72/ExIRQ2/AN2 P71/ExIRQ1/AN1 P70/ExIRQ0/AN0 AVSS PD0/TIOCA0 PD1/TIOCB0 PD2/TIOCC0/TCLKA PD3/TIOCD0/TCLKB PD4/TIOCA1 PD5/TIOCB1/TCLKC PD6/TIOCA2 PD7/TIOCB2/TCLKD PG0/ExIRQ8/ExTMCI0 PG1/ExIRQ9/ExTMCI1 PG2/ExIRQ10/ExTMIX PG3/ExIRQ11/ExTMIY PG4/ExIRQ12/ExSDAA PG5/EXIRQ13/ExSCLA PG6/ExIRQ14/ExSDAB PG7/ExIRQ15/ExSCLB PF0/IRQ8 PF1/IRQ9 PF2/IRQ10 PF3/IRQ11/ExTMOX PF4/ExPW12 PF5/ExPW13 PF6/ExPW14 PF7/ExPW15 VSS PA0/KIN8 PA1/KIN9 PA2/KIN10/PS2AC PA3/KIN11/PS2AD PA4/KIN12/PS2BC
Note: * Not supported by the system development tool (emulator).
Figure 1.2 H8S/2114R Group Pin Arrangement (TFP-144)
Rev. 3.00 Jul. 14, 2005 Page 4 of 986 REJ09B0098-0300
Section 1 Overview
1.3.2 Table 1.1
Pin No.
Pin Arrangement in Each Operating Mode H8S/2114R Group Pin Arrangement in Each Operating Mode
Pin Name Single-Chip Mode
TFP-144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (N) 15 16 17 (N) 18 19 20 21 22 23 24 25 26 27
Mode 2 and Mode 3 (EXPE = 0) VCC P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PWX0 P47/PWX1 VSS RES MD1 MD0 NMI STBY VCL P52/ExIRQ6/SCL0 P51/TMOY P50/ExEXCL P97/IRQ15/SDA0 P96//EXCL P95/IRQ14 P94/IRQ13 P93/IRQ12 P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG MD2 FWE ETRST
Flash Memory Programmer Mode VCC NC NC NC NC NC VSS RES VSS VSS FA9 VCC VCL FA18 FA17 FA19 VCC NC FA16 FA15 WE VSS VCC VCC VSS FWE RES
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Section 1 Overview
Pin No. Single-Chip Mode TFP-144 28 29 30 31 32 33 (N) 34 (N) 35 (N) 36 37 (N) 38 (N) 39 (N) 40 (N) 41 (N) 42 43 44 45 46 47 48 49 50 51 (N) 52 (N) 53 (N) 54 (N) 55 (N) 56 (N) 57 (N) Mode 2 and Mode 3 (EXPE = 0) PE4*/ETMS PE3*/ETDO PE2*/ETDI PE1*/ETCK PE0/LID3 PA7/KIN15/PS2CD PA6/KIN14/PS2CC PA5/KIN13/PS2BD VCC PA4/KIN12/PS2BC PA3/KIN11/PS2AD PA2/KIN10/PS2AC PA1/KIN9 PA0/KIN8 VSS PF7/ExPW15 PF6/ExPW14 PF5/ExPW13 PF4/ExPW12 PF3/IRQ11/ExTMOX PF2/IRQ10 PF1/IRQ9 PF0/IRQ8 PG7/ExIRQ15/ExSCLB PG6/ExIRQ14/ExSDAB PG5/ExIRQ13/ExSCLA PG4/ExIRQ12/ExSDAA PG3/ExIRQ11/ExTMIY PG2/ExIRQ10/ExTMIX PG1/ExIRQ9/ExTMCI1
Pin Name
Flash Memory Programmer Mode NC NC NC NC NC NC NC NC VCC NC NC NC NC NC VSS NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
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Section 1 Overview
Pin No. Single-Chip Mode TFP-144 58 (N) 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Mode 2 and Mode 3 (EXPE = 0) PG0/ExIRQ8/ExTMCI0 PD7/TIOCB2/TCLKD PD6/TIOCA2 PD5/TIOCB1/TCLKC PD4/TIOCA1 PD3/TIOCD0/TCLKB PD2/TIOCC0/TCLKA PD1/TIOCB0 PD0/TIOCA0 AVSS P70/ExIRQ0/AN0 P71/ExIRQ1/AN1 P72/ExIRQ2/AN2 P73/ExIRQ3/AN3 P74/ExIRQ4/AN4 P75/ExIRQ5/AN5 P76/AN6 P77/AN7 AVCC AVref P60/FTCI/KIN0/TMIX P61/FTOA/KIN1 P62/FTIA/KIN2/TMIY P63/FTIB/KIN3 P64/FTIC/KIN4 P65/FTID/KIN5 P66/IRQ6/FTOB/KIN6 P67/IRQ7/TMOX/KIN7 VCC PC7/WUE15/DLDRQ
Pin Name
Flash Memory Programmer Mode NC NC NC NC NC NC NC NC NC VSS NC NC NC NC NC NC NC NC VCC VCC NC NC NC NC NC NC NC VSS VCC NC
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Section 1 Overview
Pin No. Single-Chip Mode TFP-144 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 Mode 2 and Mode 3 (EXPE = 0) PC6/WUE14/LDRQ PC5/WUE13 PC4/WUE12 PC3/WUE11 PC2/WUE10 PC1/WUE9 PC0/WUE8 VSS P27/PW15 P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8 P17 P16 P15 P14 P13 P12 P11 VSS P10 PB7/WUE7/DLAD0 PB6/WUE6/DLAD1 PB5/WUE5/DLAD2 PB4/WUE4/DLAD3 PB3/WUE3/DLFRAME
Pin Name
Flash Memory Programmer Mode NC NC NC NC NC NC NC VSS CE FA14 FA13 FA12 FA11 FA10 OE FA8 FA7 FA6 FA5 FA4 FA3 FA2 FA1 VSS FA0 NC NC NC NC NC
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Section 1 Overview
Pin No. Single-Chip Mode TFP-144 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 (N) 136 137 138 (N) 139 140 141 142 143 144 Mode 2 and Mode 3 (EXPE = 0) PB2/WUE2 PB1/WUE1/LSCI PB0/WUE0/LSMI P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37/SERIRQ P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1/IrTxD P85/IRQ4/RxD1/IrRxD P86/IRQ5/SCK1/SCL1 P40/TMCI0/TxD2/DSERIRQ P41/TMO0/RxD2/DCLKRUN P42/ExIRQ7/TMRI0/SCK2/SDA1 VSS X1 X2 RESO XTAL EXTAL
Pin Name
Flash Memory Programmer Mode NC NC NC FO0 FO1 FO2 FO3 FO4 FO5 FO6 FO7 NC NC NC NC NC NC NC NC NC NC VSS NC NC NC XTAL EXTAL
Notes: (N) indicates the pin is driven by NMOS push-pull/open drain. * Not supported by the system development tool (emulator).
Rev. 3.00 Jul. 14, 2005 Page 9 of 986 REJ09B0098-0300
Section 1 Overview
1.3.3 Table 1.2
Type Power supply
Pin Functions Pin Functions
Symbol VCC Pin No. 1, 36, 86 13 I/O Input Name and Function Power supply pins. Connect all these pins to the system power supply. Connect the bypass capacitor between VCC and VSS (near VCC). External capacitance pin for internal step-down power. Connect this pin to VSS through an external capacitor (that is located near this pin) to stabilize internal step-down power. Ground pins. Connect all these pins to the system power supply (0 V). For connection to a crystal resonator. An external clock can be supplied from the EXTAL pin. For an example of crystal resonator connection, see section 23, Clock Pulse Generator. Supplies the system clock to external devices. 32.768-kHz external clock for sub clock should be supplied. To which pin the external clock is input can be selected from the EXCL and ExEXCL pins. These pins should be left open. These pins set the operating mode. Inputs at these pins should not be changed during operation. Reset pin. When this pin is low, the chip is reset. Outputs a reset signal to an external device. When this pin is low, a transition is made to hardware standby mode. Control pin for use by flash memory
VCL
Input
VSS
7, 42, 95, 111, 139 143 144
Input
Clock
XTAL EXTAL
Input Input
EXCL ExEXCL
18 18 16
Output Input Input
X2 X1 Operating mode control System control MD2 MD1 MD0 RES RESO STBY FWE
141 140 25 9 10 8 142 12 26
Input Input
Input Output Input Input
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Section 1 Overview
Type Interrupts
Symbol NMI IRQ15 to IRQ0
Pin No. 11
I/O Input
Name and Function Nonmaskable interrupt request input pin These pins request a maskable interrupt. To which pin an IRQ interrupt is input can be selected from the IRQn and ExIRQn pins. (n = 15 to 0)
17, 19, Input 20, 21, 47 to 50, 85, 84, 135, 134, 133, 24, 23, 22
ExIRQ15 51 to ExIRQ0 to 58 138 14 73 to 68 Boundary scan (JTAG) ETRST*2 ETMS ETDO ETDI ETCK 27 28 29 30 31 Input Input Output Input Input Interface pins for boundary scan Reset by holding the ETRST pin to low regardless of the JTAG activation. At this time, the ETRST pin should be held low for 20 clocks of ETCK. For details, see section 26, Electrical Characteristics. Then, to activate the JTAG, the ETRST pin should be set to high and the pins ETCK, ETMS, and ETDI should be set appropriately. When in the normal operation without activating the JTAG, pins ETRST, ETCK, ETMS, and ETDI are set to high or highimpedance. As these pins are pulled up inside the chip, take care during standby state.
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Section 1 Overview
Type
Symbol
Pin No. 96 to 103
I/O Output
Name and Function PWM timer pulse output pins. From which pin pulses are output can be selected from the PWn and ExPWn pins. (n = 15 to 12) PWMX pulse output pins
PWM timer PW15 to (PWM) PW8
ExPW15 to 43 to 46 ExPW12 14-bit PWM PWX1 timer PWX0 (PWMX) 16-bit free FTCI running FTOA timer (FRT) FTOB FTIA to FTID 16-bit timer TCLKD pulse unit TCLKC (TPU) TCLKB TCLKA TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 8-bit timer (TMR_0, TMR_1, TMR_X, TMR_Y) TMO0 TMO1 TMOX ExTMOX TMOY TMCI0 TMCI1 ExTMCI0 ExTMCI1 6 5 78 79 84 80 to 83 59 61 63 64 66 65 64 63 62 61 60 59 137 3 85 47 15 136 2 58 57 Output
Input Output Input Input
External event input pin Output compare output pins Input capture input pins Timer external clock input/output pins
Input/ Output
Input capture input/output compare output/PWM output pins for TGRA_0 to TGRD_0
Input/ Output Input/ Output Output
Input capture input/output compare output/PWM output pins for TGRA_1 and TGRB_1 Input capture input/output compare output/PWM output pins for TGRA_2 and TGRB_2 Waveform output pins with output compare function. From which pin waveforms are output can be selected from the TMOX and ExTMOX pins. Input pins for the external clock input to the counter. To which pin the external clock is input can be selected from the TMCIn and ExTMCIn pins. (n = 1 or 0)
Input
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Section 1 Overview
Type 8-bit timer (TMR_0, TMR_1, TMR_X, TMR_Y)
Symbol TMRI0 TMRI1 TMIX TMIY ExTMIX ExTMIY TxD1 TxD2 RxD1 RxD2 SCK1 SCK2 IrTxD IrRxD SCL0 SCL1 ExSCLA ExSCLB
Pin No. 138 4 78 80 56 55 133 136 134 137 135 138 133 134 14 135 53 51
I/O Input Input
Name and Function External event input pin and counter reset input pin External event input pins and counter reset input pins. To which pin an external event or counter reset is input can be selected from the TMIn and ExTMIn pins. (n = X or Y) Transmit data output pins Receive data input pins Clock input/output pins. Output type is NMOS push-pull output. Encoded data output pin for IrDA Encoded data input pin for IrDA I2C clock input/output pins. These pins can drive a bus directly with the NMOS open drain output. 2 To which pin the I C clock is input or output can be selected from the SCLn, ExSCLA, and ExSCLB pins. (n = 1 or 0) I C data input/output pins. These pins can drive a bus directly with the NMOS open drain output. To 2 which pin the I C data is input or output can be selected from the SDAn, ExSDAA, and ExSDAB pins. (n = 1 or 0) Synchronous clock input/output pins for the keyboard buffer control unit
2
Serial communication interface (SCI_1, SCI_2) SCI with IrDA (SCI) I C bus interface (IIC)
2
Output Input Input/ Output Output Input Input/ Output
SDA0 SDA1 ExSDAA ExSDAB
17 138 54 52
Input/ Output
Keyboard PS2AC buffer PS2BC control unit PS2CC (KBU) PS2AD PS2BD PS2CD
39 37 34 38 35 33
Input/ Output
Input/ Output
Data input/output pins for the keyboard buffer control unit.
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Section 1 Overview
Type Keyboard control
Symbol KIN15 to KIN0
Pin No. 33 to 35, 37 to 41, 85 to 78
I/O Input
Name and Function Matrix keyboard input pins. All pins have a wakeup function. Normally, KIN0 to KIN15 function as key scan inputs, and P10 to P17 and P20 to P27 function as key scan outputs. Thus, composed with a maximum of 16 outputs x 16 inputs, a 256key matrix can be configured. Wake-up event input pins. Same wake up as key wake up can be performed with various sources.
WUE15 to WUE8 WUE7 to WUE0 A/D converter ADTRG AVCC
87 to 94 113 to 120
Input
AN7 to AN0 75 to 68 24 76
Input Input Input
Analog input pins External trigger input pin to start A/D conversion Analog power supply pin. When the A/D converter is not used, this pin should be connected to the system power supply (+3.3 V). Reference power supply pin for the A/D converter. When the A/D converter is not used, this pin should be connected to the system power supply (+3.3 V). Ground pin for the A/D converter. This pin should be connected to the system power supply (0 V).
AVref
77
Input
AVSS
67
Input
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Section 1 Overview
Type LPC Interface (LPC)
Symbol LAD3 to LAD0 LFRAME LRESET LCLK SERIRQ LSCI LSMI PME GA20 CLKRUN LPCPD LID3 DLAD3 to DLAD0
Pin No.
I/O
Name and Function Transfer cycle type, address, and data input/output pins Input pin indicating transfer cycle start and forced termination of an abnormal transfer cycle LPC reset pin. When this pin is low, a reset state is entered. LPC clock input pin LPC serial host interrupt (HIRQ1, SMI, HIRQ6, or HIRQ9 to HIRQ12) input/output pin General input/output ports of LSCI, LSMI, and PME GATE A20 control signal output pin LCLK operation start request input/output pin LPC module shutdown control input pin Input pin for setting host address 31 LAD input/output pins for the docking LPC LFRAME output pin for the docking LPC SERIRQ input/output pin for the docking LPC CLKRUN input/output pin for the docking LPC Encoded DMA request output pin for the docking LPC Encoded DMA request input pin for the docking LPC
124 to 121 Input/ Output 125 126 127 128 119 120 129 130 131 132 32 Input Input Input Input/ Output Input/ Output Output Input/ Output Input Input
116 to 113 Input/ Output Output Input/ Output Input/ Output Output Input
DLFRAME 117 DSERIRQ 136
DCLKRUN 137 LDRQ DLDRQ 88 87
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Section 1 Overview
Type I/O ports
Symbol P17 to P10 P27 to P20 P37 to P30 P47 to P40 P52 to P50 P67 to P60 P77 to P70 P86 to P80 P97 to P90
Pin No. 104 to 110, 112 96 to 103 128 to 121 6 to 2, 138 to 136 14 to 16 85 to 78 75 to 68 135 to 129 17 to 24
I/O Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input Input/ Output Input/ Output
Name and Function Eight input/output pins Eight input/output pins Eight input/output pins Eight input/output pins Three input/output pins Eight input/output pins Eight input pins Seven input/output pins Eight input/output pins Eight input/output pins Eight input/output pins Eight input/output pins Eight input/output pins Five input pins Eight input/output pins Eight input/output pins
PA7 to PA0 33 to 35, 37 to 41 PB7 to PB0 113 to 120 PC7 to PC0 87 to 94 PD7 to PD0 59 to 66 PE4 to PE0*1 28 to 32
PF7 to PF0 43 to 50 PG7 to PG0 51 to 58
Notes: 1. Pins PE4 to PE1 are not supported by the system development tool (emulator). 2. Following precautions are required on the power-on reset signal that is applied to the ETRST pin. The reset signal should be applied on power supply. Apart the power on reset circuit from this LSI to prevent the ETRST pin of the board tester from affecting the operation of this LSI. Apart the power on reset circuit from this LSI to prevent the system reset of this LSI from affecting the ETRST pin of the board tester.
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Section 1 Overview
Figure1.3 shows an example of design in which signals for reset do not affect each other.
Board edge pin This LSI System reset Power On Reset circuit ETRST ETRST RES
Figure 1.3 Sample Design of Reset Signals with no Affection Each Other
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Section 1 Overview
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Section 2 CPU
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16 Mbytes linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes.
2.1
Features
* Upward-compatibility with H8/300 and H8/300H CPUs Can execute H8/300 CPU and H8/300H CPU object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16 Mbytes address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions are executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B) 16 / 8-bit register-register divide: 12 states (DIVXU.B)
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Section 2 CPU
16 x 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 / 16-bit register-register divide: 20 states (DIVXU.W) * Two CPU operating modes Normal mode Advanced mode * Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * The number of execution states of the MULXU and MULXS instructions
Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21
In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model.
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Section 2 CPU
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. * Extended address space Normal mode supports the same 64 kbytes address space as the H8/300 CPU. Advanced mode supports a maximum 16 Mbytes address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16 Mbytes address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast. 2.1.3 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast.
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Section 2 CPU
2.2
CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64 kbytes address space. Advanced mode supports a maximum 16 Mbytes address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. * Address space Linear access to a maximum address space of 64 kbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. (If general register Rn is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or postincrement (@Rn+) and a carry or borrow occurs, the value in the corresponding extended register (En) will be affected.) * Instruction set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception vector table and memory indirect branch addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode, the operand is a 16-bit (word) operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. * Stack structure In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.
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Section 2 CPU
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Reset exception vector (Reserved for system use)
(Reserved for system use) Exception vector table Exception vector 1 Exception vector 2
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC (16 bits)
SP
CCR CCR* PC (16 bits)
(a) Subroutine Branch Note: * Ignored when returning.
(b) Exception Handling
Figure 2.2 Stack Structure in Normal Mode
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Section 2 CPU
2.2.2
Advanced Mode
* Address space Linear access to a maximum address space of 16 Mbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. * Instruction set All instructions and addressing modes can be used. * Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper eight bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3). For details of the exception vector table, see section 4, Exception Handling.
H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved for system use) H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved for system use)
H'00000010
Reserved Exception vector 1
Figure 2.3 Exception Vector Table (Advanced Mode)
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Section 2 CPU
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper eight bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the top area of this range is also used for the exception vector table. * Stack structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.
SP
Reserved PC (24-bit)
SP
CCR PC (24-bit)
(a) Subroutine Branch
(b) Exception Handling
Figure 2.4 Stack Structure in Advanced Mode
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Section 2 CPU
2.3
Address Space
Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64 kbytes address space in normal mode, and a maximum 16 Mbytes (architecturally 4 Gbytes) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes.
H'0000 64 kbytes H'FFFF H'00000000 16 Mbytes Program area
H'00FFFFFF
Data area
Not available in this LSI
H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode
Note: * Not available in this LSI.
Figure 2.5 Memory Map
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Section 2 CPU
2.4
Register Configuration
The H8S/2000 CPU has the internal registers shown in figure 2.6. These are classified into two types of registers: general registers and control registers. Control registers refer to a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).
General Registers (Rn) and Extended Registers (En)
15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers
23 PC 0
EXR* T
76543210 - - - - I2 I1 I0
76543210
CCR I UI H U N Z V C
Legend
SP PC EXR T I2 to I0 CCR I UI : Stack pointer : Program counter : Extended control register : Trace bit : Interrupt mask bits : Condition-code register : Interrupt mask bit : User bit or interrupt mask bit H U N Z V C : Half-carry flag : User bit : Negative flag : Zero flag : Overflow flag : Carry flag
Note: * Does not affect operation in this LSI.
Figure 2.6 CPU Internal Registers
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Section 2 CPU
2.4.1
General Registers
The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing sixteen 16-bit registers at the maximum. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing sixteen 8-bit registers at the maximum. The usage of each register can be selected independently. General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack.
* Address registers * 32-bit registers * 16-bit registers * 8-bit registers
E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H)
Figure 2.7 Usage of General Registers
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Section 2 CPU
Free area SP (ER7)
Stack area
Figure 2.8 Stack 2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR)
EXR does not affect operation in this LSI.
Bit 7 Bit Name T Initial Value R/W 0 All 1 1 1 1 R/W R R/W R/W R/W Description Trace Bit Does not affect operation in this LSI. 6 to 3 - 2 to 0 I2 I1 I0 Reserved These bits are always read as 1. Interrupt Mask Bits 2 to 0 Do not affect operation in this LSI.
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Section 2 CPU
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Bit 7 Bit Name I Initial Value 1 R/W Description R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, see section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 when data is zero, and cleared to 0 when data is not zero.
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Section 2 CPU
Bit 1
Bit Name V
Initial Value Undefined
R/W Description R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.
0
C
Undefined
R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
2.4.5
Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.
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Section 2 CPU
2.5
Data Formats
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats
Figure 2.9 shows the data formats of general registers.
Data Type
1-bit data
Register Number
RnH
Data Image
7 0 Don't care 76 54 32 10
7 1-bit data RnL Don't care
0
76 54 32 10
7 4-bit BCD data RnH Upper
43 Lower
0 Don't care
7 4-bit BCD data RnL Don't care Upper
43 Lower
0
7 Byte data RnH MSB
0 Don't care LSB 7 0 LSB
Byte data
RnL
Don't care MSB
Figure 2.9 General Register Data Formats (1)
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Section 2 CPU
Data Type Word data
Register Number Rn
Data Image
15
0
MSB
LSB
Word data
15
En
0
MSB
LSB
Longword data
31
ERn
16 15 0
MSB
En
Rn
LSB
Legend
ERn En Rn RnH RnL LSB : General register ER : General register E : General register R : General register RH : General register RL : Least significant bit
MSB : Most significant bit
Figure 2.9 General Register Data Formats (2)
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Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size.
Data Type Address
7 1-bit data Address L 7 6 5 4 3 2 1
Data Image
0 0
Byte data
Address L
MSB
LSB
Word data
Address 2M Address 2M + 1
MSB LSB
Longword data
Address 2N Address 2N + 1 Address 2N + 2 Address 2N + 3
MSB
LSB
Figure 2.10 Memory Data Formats
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Section 2 CPU
2.6
Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1
Function Data transfer
Instruction Classification
Instructions MOV POP* , PUSH* LDM* , STM*
5 5 1 1
Size B/W/L W/L L B B/W/L B B/W/L L B/W W/L B B/W/L B/W/L
Types 5
MOVFPE*3, MOVTPE*3 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS* Logic operations Shift Bit manipulation Branch System control
4
19
AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
4 8 14 5 9 1 Total: 65
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B BIAND, BOR, BIOR, BXOR, BIXOR BCC*2, JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP - - -
Block data transfer EEPMOV
Notes: B: Byte size; W: Word size; L: Longword size. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. BCC is the generic name for conditional branch instructions. 3. Cannot be used in this LSI. 4. To use the TAS instruction, use registers ER0, ER1, ER4, and ER5. 5. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot be used as an STM/LDM register.
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2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2
Symbol Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: *
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Instruction MOV
Data Transfer Instructions
Size*1 B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
MOVFPE MOVTPE POP
B B W/L
Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn
PUSH
W/L
Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
LDM*2 STM*
2
L L
@SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack.
Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Since register ER7 functions as the stack pointer in an STM/LDM instruction, it cannot be used as an STM/LDM register.
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Table 2.4
Arithmetic Operations Instructions (1)
Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.) B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register. B/W/L Rd 1 Rd, Rd 2 Rd Adds or subtracts the value 1 or 2 to or from data in a general register. (Only the value 1 can be added to or subtracted from byte operands.) L B Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8-bit x 8-bit 16-bit or 16-bit x 16-bit 32-bit.
Instruction Size* ADD SUB B/W/L
ADDX SUBX
INC DEC ADDS SUBS DAA DAS MULXU
MULXS
B/W
Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8bit x 8-bit 16-bit or 16-bit x 16-bit 32-bit.
DIVXU
B/W
Rd / Rs Rd Performs unsigned division on data in two general registers: either 16-bit / 8-bit 8-bit quotient and 8-bit remainder or 32-bit / 16-bit 16-bit quotient and 16-bit remainder.
Note:
*
Size refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.4
Arithmetic Operations Instructions (2)
Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
Instruction Size* DIVXS B/W
CMP
B/W/L
Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result.
NEG
B/W/L
0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register.
EXTU
W/L
Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left.
EXTS
W/L
Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit.
TAS*2
B
@ERd - 0, 1 ( of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1.
Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. To use the TAS instruction, use registers ER0, ER1, ER4, and ER5.
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Section 2 CPU
Table 2.5
Logic Operations Instructions
Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data.
Instruction Size* AND B/W/L
OR
B/W/L
Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data.
XOR
B/W/L
Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
NOT
B/W/L
Rd Rd Takes the one's complement (logical complement) of data in a general register.
Note:
*
Size refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.6
Shift Instructions
Function Rd (shift) Rd Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L Rd (shift) Rd Performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L B/W/L Rd (rotate) Rd Rotates data in a general register. 1-bit or 2 bit rotation is possible. Rd (rotate) Rd Rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. Size refers to the operand size. B: Byte W: Word L: Longword
Instruction Size* SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * B/W/L
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Section 2 CPU
Table 2.7
Bit Manipulation Instructions (1)
Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Instruction Size* BSET B
BCLR
B
0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BNOT
B
( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BTST
B
( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BAND
B
C ( of ) C Logically ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
BIAND
B
C ( of ) C Logically ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BOR
B
C ( of ) C Logically ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
BIOR
B
C ( of ) C Logically ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size. B: Byte
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Section 2 CPU
Table 2.7
Instruction BXOR
Bit Manipulation Instructions (2)
Size* B Function C ( of ) C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
BIXOR
B
C ( of ) C Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BLD
B
( of ) C Transfers a specified bit in a general register or memory operand to the carry flag.
BILD
B
( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data.
BST
B
C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand.
BIST
B
C (. of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size. B: Byte
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Section 2 CPU
Table 2.8
Instruction Bcc
Branch Instructions
Size - Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Condition Always Never CZ=0 CZ=1 C=0
JMP BSR JSR RTS
- - - -
Branches unconditionally to a specified address. Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine
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Section 2 CPU
Table 2.9
Instruction TRAPA RTE SLEEP LDC
System Control Instructions
Size* - - - B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper eight bits are valid.
STC
B/W
CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory operand. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper eight bits are valid.
ANDC ORC XORC NOP Note: *
B B B -
CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter.
Size refers to the operand size. B: Byte W: Word
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Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction EEPMOV.B Size - Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next: if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next: Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W -
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Section 2 CPU
2.6.2
Basic Instruction Formats
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register field Specifies a general register. Address registers are specified by 3-bit, and data registers by 3-bit or 4-bit. Some instructions have two register fields, and some have no register field. * Effective address extension 8-, 16-, or 32-bit specifying immediate data, an absolute address, or a displacement. * Condition field Specifies the branching condition of Bcc instructions.
(1) Operation field only op NOP, RTS
(2) Operation field and register fields op rn rm ADD.B Rn, Rm
(3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm
(4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16
Figure 2.11 Instruction Formats (Examples)
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Section 2 CPU
2.7
Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes
No. Addressing Mode 1 2 3 4 5 6 7 8 Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
2.7.1
Register Direct--Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect--@ERn
The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. If the address is a program instruction address, the lower 24 bits are valid and the upper eight bits are all assumed to be 0 (H00).
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2.7.3
Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn
Register Indirect with Post-Increment--@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. Register Indirect with Pre-Decrement--@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address, the entire address space is accessed. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper eight bits are all assumed to be 0 (H'00).
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Section 2 CPU
Table 2.12 Absolute Address Access Ranges
Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF
2.7.6
Immediate--#xx:8, #xx:16, or #xx:32
The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction code can be used directly as an operand. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC)
This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24-bit and added to the 24-bit address indicated by the PC value to generate a 24-bit branch address. Only the lower 24-bit of this branch address are valid; the upper eight bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128-byte (-63 to +64 words) or -32766 to +32768-byte (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number.
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Section 2 CPU
2.7.8
Memory Indirect--@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the top area of the address range in which the branch address is stored is also used for the exception vector area. For further details, see section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or the instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.)
Specified by @aa:8
Branch address
Specified by @aa:8
Reserved Branch address
(a) Normal Mode
(b) Advanced Mode
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
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Section 2 CPU
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper eight bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1)
No 1
Addressing Mode and Instruction Format
Register direct (Rn)
Effective Address Calculation
Effective Address (EA)
Operand is general register contents.
op 2
rm
rn 31
General register contents
Register indirect (@ERn)
0
31
24 23
0
Don't care
op 3
r
Register indirect with displacement @(d:16,ERn) or @(d:32,ERn)
31
General register contents
0 31 24 23 0
op
r
disp 31
Sign extension
Don't care 0 disp
4
Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+
31
General register contents
0
31
24 23
0
Don't care
op
r 31
1, 2, or 4
* Register indirect with pre-decrement @-ERn
0
General register contents
31
24 23
0
Don't care op r
Operand Size Byte Word Longword 1, 2, or 4
Offset 1 2 4
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Section 2 CPU
Table 2.13 Effective Address Calculation (2)
No 5
Addressing Mode and Instruction Format
Absolute address
Effective Address Calculation
Effective Address (EA)
@aa:8 op abs
31
24 23 H'FFFF
87
0
Don't care
@aa:16 op abs
31
24 23
16 15
0
Don't care Sign extension
@aa:24 op abs
31
24 23
0
Don't care
@aa:32 op abs 31 24 23 0
Don't care
6
Immediate
#xx:8/#xx:16/#xx:32 op IMM
Operand is immediate data.
7
Program-counter relative @(d:8,PC)/@(d:16,PC)
23
PC contents
0
op
disp
23
Sign extension
0 disp 31 24 23 0
Don't care
8
Memory indirect @@aa:8 * Normal mode
31 op abs H'000000 15
87 abs
0
0
Memory contents
31
24 23
16 15 H'00
0
Don't care
* Advanced mode
31 op abs 31
Memory contents
87 H'000000 abs
0 31 24 23 Don't care 0
0
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Section 2 CPU
2.8
Processing States
The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. * Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, see section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, see section 4, Exception Handling. * Program execution state In this state the CPU executes program instructions in sequence. * Bus-released state In a product which has a bus master other than the CPU, the bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. For details, see section 6, Bus Controller (BSC). * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details, see section 24, Power-Down Modes.
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Section 2 CPU
End of bus request
Bus request
Program execution state
End of bus request
Bus request
Bus-released state
End of exception handling
SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1
SLEEP instruction with LSON = 0, SSBY = 0
Request for exception handling
Sleep mode
Interrupt request
Exception-handling state
External interrupt request
RES = high
Software standby mode
Reset state*1
STBY = high, RES = low
Hardware standby mode*2 Power-down state*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details, refer to section 24, Power-Down Modes.
Figure 2.13 State Transitions
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Section 2 CPU
2.9
2.9.1
Usage Notes
Note on TAS Instruction Usage
To use the TAS instruction, use registers ER0, ER1, ER4, and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. When the TAS instruction is used as a user-defined intrinsic function, registers ER0, ER1, ER4, and ER5 should be used. 2.9.2 Note on STM/LDM Instruction Usage
Since the ER7 register is used as the stack pointer in an STM/LDM instruction, it cannot be used as a register that allows save (STM) or restore (LDM) operation. Two to four registers can be saved/restored by single STM/LDM instruction. Available registers are listed below. Two: ER0 and ER1, ER2 and ER3, ER4 and ER5 Three: ER0 to ER2, ER4 to ER6 Four: ER0 to ER3 The STM/LDM instruction with ER7 is not created by the Renesas Technology H8S or H8/300 series C/C++ compilers. 2.9.3 Note on Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read data in byte units, manipulate the data of the target bit, and write data in byte units. Special care is required when using these instructions in cases where a register containing a write-only bit is used or a bit is directly manipulated for a port. In addition, the BCLR instruction can be used to clear the flag of the internal I/O register. In this case, if the flag to be cleared has been set to 1 by an interrupt processing routine, the flag need not be read before executing the BCLR instruction.
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Section 2 CPU
2.9.4
EEPMOV Instruction
1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4*, which starts from the address indicated by ER5, to the address indicated by ER6.
ER5 ER6
ER5 + R4 ER6 + R4
2. Set R4 and ER6 so that the end address of the destination address (value of ER6 + R4) does not exceed H'00FFFFFF (the value of ER6 must not change from H'00FFFFFF to H'01000000 during execution).
ER5 ER6
ER5 + R4 Invalid H'FFFFFFF ER6 + R4
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Section 2 CPU
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1 Operating Mode Selection
This LSI supports five operating modes (modes 2 to 4, 6, and 7). The operating mode is determined by the setting of the mode pins (MD2, MD1, and MD0). Table 3.1 shows the MCU operating mode selection. Table 3.1 MCU Operating Mode Selection
Description Single-chip mode Single-chip mode Flash memory programming/erasing On-Chip ROM Enabled Enabled
MCU Operating CPU Operating Mode MD2 MD1 MD0 Mode 2 3 4 6 7 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 Advanced Normal Emulation Emulation
On-chip emulation mode Enabled On-chip emulation mode Enabled
Modes 2 and 3 are single-chip mode. Modes 0, 1, and 5 are not available in this LSI. Modes 4, 6, and 7 are operating modes for a special purpose. Thus, mode pins should be set to enable mode 2 or 3 in the normal program execution state. Mode pin settings should not be changed during operation. Mode 4 is a boot mode for programming or erasing the flash memory. For details, see section 21, Flash Memory (0.18-m F-ZTAT Version). Modes 6 and 7 are on-chip emulation modes. In these modes, this LSI is controlled by an on-chip emulator (E10A) via the JTAG, thus enabling on-chip emulation.
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Section 3 MCU Operating Modes
3.2
Register Descriptions
The following registers are related to the operating modes. For details on the bus control register (BCR), see section 6.2.1, Bus Control Register (BCR). * * * * Mode control register (MDCR) System control register (SYSCR) Serial timer control register (STCR) System control register 3 (SYSCR3) Mode Control Register (MDCR)
3.2.1
MDCR is used to set an operating mode and to monitor the current operating mode.
Bit 7 Bit Name Initial Value EXPE 0 All 0 --* --* --* R/W Description R/W Reserved The initial value should not be changed. 6 to 3 -- 2 1 0 MDS2 MDS1 MDS0 R R R R Reserved The initial value should not be changed. Mode Select 2 to 0 These bits indicate the input levels at mode pins (MD2, MD1, and MD0) (the current operating mode). The MDS2, MDS1, and MDS0 bits correspond to the MD2, MD1, and MD0 pins, respectively. These bits are readonly bits and cannot be written to. The input levels of the mode pins (MD2, MD1, and MD0) are latched into these bits when MDCR is read. These latches are canceled by a reset. Note: * The initial values are determined by the settings of the MD2, MD1, and MD0 pins.
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Section 3 MCU Operating Modes
3.2.2
System Control Register (SYSCR)
SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables the on-chip RAM address space.
Bit 7, 6 5 4 Bit Name -- INTM1 INTM0 Initial Value All 0 0 0 R/W Description R Reserved The initial value should not be changed. R Interrupt Control Select Mode 1, 0 R/W These bits select the interrupt control mode of the interrupt controller. For details on the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Interrupt control mode 1 10: Setting prohibited 11: Setting prohibited 3 XRST 1 R External Reset Indicates the reset source. A reset is caused by an external reset input, or when the watchdog timer overflows. 0: A reset is caused when the watchdog timer overflows 1: A reset is caused by an external reset 2 NMIEG 0 R/W NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input
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Section 3 MCU Operating Modes
Bit 1
Bit Name KINWUE
Initial Value 0
R/W Description R/W Keyboard Control Register Access Enable When the RELOCATE bit is cleared to 0, this bit enables or disables CPU access for the keyboard matrix interrupt registers (KMIMRA and KMIMR), pull-up MOS control register (KMPCR), and registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, TCORB_X, TCONRI, and CONRS) of 8-bit timers (TMR_X and TMR_Y) 0: Enables CPU access for registers of TMR_X and TMR_Y in areas from H'(FF)FFF0 to H'(FF)FFF7 and from H'(FF)FFFC to H'(FF)FFFF 1: Enables CPU access for the keyboard matrix interrupt registers and input pull-up MOS control register in areas from H'(FF)FFF0 to H'(FF)FFF7 and from H'(FF)FFFC to H'(FF)FFFF When the RELOCATE bit is set to 1, this bit is disabled. For details, see section 3.2.4, System Control Register 3 (SYSCR3) and section 25, List of Registers.
0
RAME
1
R/W RAM Enable Enables or disables on-chip RAM. 0: On-chip RAM is disabled 1: On-chip RAM is enabled
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Section 3 MCU Operating Modes
3.2.3
Serial Timer Control Register (STCR)
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter.
Bit 7 Bit Name IICS Initial Value 0 R/W Description R/W I2C Extra Buffer Select Sets bits 7 to 4 of port A to form an output buffer similar 2 to SCL and SDA. This function is used to realize the I C interface only by software. 0: PA7 to PA4 are normal I/O pins 1: PA7 to PA4 are I/O pins that can be bus driven 6 5 IICX1 IICX0 0 0 R/W I2C Transfer Rate Select 1, 0 R/W These bits control the IIC operation. These bits select the transfer rate in master mode together with bits 2 CKS2 to CKS0 in the I C bus mode register (ICMR). For details on the transfer rate, see table 16.3.
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Section 3 MCU Operating Modes
Bit 4
Bit Name IICE
Initial Value 0
R/W Description R/W I2C Master Enable When the RELOCATE bit is cleared to 0, enables or disables CPU access for IIC registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR, and DDCSWR), PWMX registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL), and SCI registers (SMR, BRR, and SCMR). 0: SCI_1 registers are accessed in areas from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. SCI_2 registers are accessed in areas from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. Access is prohibited in areas from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. 1: IIC_1 registers are accessed in areas from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. PWMX registers are accessed in areas from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. IIC_0 registers are accessed in areas from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. DDCSWR is accessed in areas of H'(FF)FEE6 When the RELOCATE bit is set to 1, this bit is disabled. For details, see section 3.2.4, System Control Register 3 (SYSCR3) and section 25, List of Registers.
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Section 3 MCU Operating Modes
Bit 3
Bit Name FLSHE
Initial Value 0
R/W R/W
Description Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FCCS, FPCS, FECS, FKEY, FMATS, and FTDAR), power-down state control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and on-chip peripheral module control registers (BCR2, WSCR, PCSR, and SYSCR2). 0: Control registers of power-down state and peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87. Area from H'(FF)FEA8 to H'(FF)FEAE is reserved. 1: Control registers of flash memory are accessed in an area from H'(FF)FEA8 to H'(FF)FEAE. Area from H'(FF)FF80 to H'(FF)FF87 is reserved.
2 1 0
-- ICKS1 ICKS0
0 0 0
R/(W) Reserved The initial value should not be changed. R/W R/W Internal Clock Source Select 1, 0 These bits select a clock to be input to the timer counter (TCNT) and a count condition together with bits CKS2 to CKS0 in the timer control register (TCR). For details, see section 13.3.4, Timer Control Register (TCR).
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Section 3 MCU Operating Modes
3.2.4
System Control Register 3 (SYSCR3)
SYSCR3 selects the register map and interrupt vector.
Bit 7 6 Bit Name -- EIVS* Initial Value 0 0 R/W Description R/W Reserved The initial value should not be changed. R/W Extended interrupt Vector Select* Selects compatible mode or extended mode for the interrupt vector table. 0: H8S/2140B Group compatible vector mode 1: Extended vector mode For details, see section 5, Interrupt Controller. 5 RELOCATE 0 R/W Register Address Map Select Selects compatible mode or extended mode for the register map. When extended mode is selected for the register map, CPU access for registers can be controlled without using the KINWUE bit in SYSCR or the IICE bit in STCR to switch the registers to be accessed. 0: H8S/2140B Group compatible register map mode 1: Extended register map mode For details, see section 25, List of Registers. 4 to 0 -- Note: * All 0 R/W Reserved The initial value should not be changed. Switch the modes when an interrupt occurrence is disabled.
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Section 3 MCU Operating Modes
3.3
3.3.1
Operating Mode Descriptions
Mode 2
The CPU can access a 16-Mbyte address space in either advanced mode or single-chip mode. The on-chip ROM is enabled. 3.3.2 Mode 3
The CPU can access a 64-kbyte address space in either normal mode or single-chip mode. The onchip ROM is enabled. The size of ROM and RAM that can be used in mode 3 is 56 kbytes and 4 kbytes, respectively.
3.4
Address Map
Figures 3.1 shows the address map in each operating mode.
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Section 3 MCU Operating Modes
Mode 2 (EXPE = 0) Advanced mode Single-chip mode ROM: 1 Mbyte RAM: 8 kbytes H'000000 H'0000
Mode 3 (EXPE = 0) Normal mode Single-chip mode ROM: 56 kbytes RAM: 4 kbytes
On-chip ROM
On-chip ROM
H'0FFFFF
H'DFFF
H'FF0000 Reserved area H'FFD07F H'FFD080 On-chip RAM 8064 bytes H'FFEFFF H'EFFF H'E080 On-chip RAM 3968 bytes
H'FFF800 Internal I/O registers 3 H'FFFE4F H'FFFE50 Internal I/O registers 2 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF
H'F800 Internal I/O registers 3 H'FE4F H'FE50 Internal I/O registers 2 H'FEFF H'FF00 H'FF7F H'FF80 Internal I/O registers 1 H'FFFF Internal I/O registers 1 On-chip RAM 128 bytes
On-chip RAM 128 bytes
Figure 3.1 Address Map
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Section 4 Exception Handling
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.1
Priority High
Exception Types and Priority
Exception Type Reset Interrupt Start of Exception Handling Starts immediately after a low-to-high transition of the RES pin, or when the watchdog timer overflows. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. Starts when a direct transition occurs as the result of SLEEP instruction execution. Started by execution of a trap (TRAPA) instruction. Trap instruction exception handling requests are accepted at all times in the program execution state.
Direct transition Trap instruction Low
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Section 4 Exception Handling
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to exception sources. Table 4.2 and table 4.3 list the exception sources and their vector addresses. The EIVS bit in the system control register 3 (SYSCR3) allows the selection of the H8S/2140B Group compatible vector mode or extended vector mode. Table 4.2 Exception Handling Vector Table (H8S/2140B Group Compatible Vector Mode)
Vector Number Normal Mode 0 1 5 6 7 8 9 10 11 Reserved for system use 12 15 16 17 18 19 20 21 22 23 Vector Addresses Advanced Mode H'000000 to H'000003 H'000004 to H'000007 | H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 | H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057 H'000058 to H'00005B H'00005C to H'00005F
Exception Source Reset Reserved for system use
H'0000 to H'0001 H'0002 to H'0003 | H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 | H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F
Direct transition External interrupt (NMI) Trap instruction (four sources)
External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 IRQ7, KIN15 to KIN8, WUE7 to WUE0 Internal interrupt*
24 29
H'0030 to H'0031 H'003A to H'003B
H'000060 to H'000063 H'000074 to H'000077
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Section 4 Exception Handling
Exception Source Reserved for system use Reserved for system use Reserved for system use External interrupt WUE15 to WUE8 Internal interrupt*
Vector Number Normal Mode 30 31 32 33 34 55 56 57 58 59 60 61 62 63 64 127 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
Vector Addresses Advanced Mode H'000078 to H'00007B H'00007C to H'00007F H'000080 to H'000083 H'000084 to H'000087 H'000088 to H'00008B H'0000DC to H'0000DF H'0000E0 to H'0000E3 H'0000E4 to H'0000E7 H'0000E8 to H'0000EB H'0000EC to H'0000EF H'0000F0 to H'0000F3 H'0000F4 to H'0000F7 H'0000F8 to H'0000FB H'0000FC to H'0000FF H'000100 to H'000103 H'0001FC to H'0001FF
H'003C to H'003D H'003E to H'003F H'0040 to H'0041 H'0042 to H'0043 H'0044 to H'0045 H'006E to H'006F H'0070 to H'0071 H'0072 to H'0073 H'0074 to H'0075 H'0076 to H'0077 H'0078 to H'0079 H'007A to H'007B H'007C to H'007D H'007E to H'007F H'0080 to H'0081 H'00FE to H'00FF
External interrupt IRQ8
Internal interrupt*
Note: *
For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table.
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Section 4 Exception Handling
Table 4.3
Exception Handling Vector Table (Extended Vector Mode)
Vector Number Normal Mode 0 1 5 6 7 8 9 10 11 Vector Addresses Advanced Mode H'000000 to H'000003 H'000004 to H'000007 | H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 | H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057 H'000058 to H'00005B H'00005C to H'00005F H'000060 to H'000063 H'000074 to H'000077 H'000078 to H'00007B H'00007C to H'00007F H'000080 to H'000083 H'000084 to H'000087
Exception Source Reset Reserved for system use
H'0000 to H'0001 H'0002 to H'0003 | H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 | H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'003A to H'003B H'003C to H'003D H'003E to H'003F H'0040 to H'0041 H'0042 to H'0043
Direct transition External interrupt (NMI) Trap instruction (four sources)
Reserved for system use
12 15 16 17 18 19 20 21 22 23 24 29
External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Internal interrupt*
External interrupt External interrupt External interrupt External interrupt
KIN7 to KIN0 KIN15 to KIN8 WUE7 to WUE0 WUE15 to WUE8
30 31 32 33
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Section 4 Exception Handling
Exception Source Internal interrupt*
Vector Number 34 55 56 57 58 59 60 61 62 63 64 127 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
Vector Addresses Normal Mode H'0044 to H'0045 H'006E to H'006F H'0070 to H'0071 H'0072 to H'0073 H'0074 to H'0075 H'0076 to H'0077 H'0078 to H'0079 H'007A to H'007B H'007C to H'007D H'007E to H'007F H'0080 to H'0081 H'00FE to H'00FF Advanced Mode H'000088 to H'00008B H'0000DC to H'0000DF H'0000E0 to H'0000E3 H'0000E4 to H'0000E7 H'0000E8 to H'0000EB H'0000EC to H'0000EF H'0000F0 to H'0000F3 H'0000F4 to H'0000F7 H'0000F8 to H'0000FB H'0000FC to H'0000FF H'000100 to H'000103 H'0001FC to H'0001FF
External interrupt IRQ8
Internal interrupt*
Note: *
For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table.
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Section 4 Exception Handling
4.3
Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog Timer (WDT). 4.3.1 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit in CCR is set to 1. 2. The reset exception handling vector address is read and transferred to the PC, and then program execution starts from the address indicated by the PC. Figure 4.1 shows an example of the reset sequence.
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Section 4 Exception Handling
Vector fetch
Internal processing
Prefetch of first program instruction
RES
Internal address bus
(1) U
(1) L
(3)
Internal read signal
Internal write signal
High
Internal data bus
(2) U
(2) L
(4)
(1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002 (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)U + (2)L) (4) First program instruction
Figure 4.1 Reset Sequence (Mode 2) 4.3.2 Interrupts Immediately after Reset
If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after a reset, make sure that this instruction initializes the SP (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled
After a reset is cancelled, the module stop control registers (MSTPCRH, MSTPCRL, and MSTPCRA) are initialized, and all modules except the DTC operate in module stop mode. Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read from and write to these registers, clear module stop mode. For details on module stop mode, see section 24, Power-Down Modes.
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Section 4 Exception Handling
4.4
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, see section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved in the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address.
4.5
Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved in the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR after execution of trap instruction exception handling. Table 4.4 Status of CCR after Trap Instruction Exception Handling
CCR Interrupt Control Mode 0 1 I Set to 1 Set to 1 UI Retains value prior to execution Set to 1
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Section 4 Exception Handling
4.6
Stack Status after Exception Handling
Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling.
Normal mode Advanced mode
SP
CCR CCR* PC (16 bits) SP CCR PC (24 bits)
Note: * Ignored on return.
Figure 4.2 Stack Status after Exception Handling
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Section 4 Exception Handling
4.7
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers:
PUSH.W PUSH.L Rn ERn
(or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W POP.L Rn ERn
(or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what occurs when the SP value is odd.
CCR SP PC SP
SP
R1L
H'FFEFFA H'FFEFFB H'FFEFFC
PC
H'FFEFFD H'FFEFFF
TRAPA instruction executed SP set to H'FFEFFF [Legend] CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer
MOV.B R1L, @-ER7 Contents of CCR lost
Data saved above SP
Note: This diagram illustrates an example in which interrupt control mode is 0 in advanced mode.
Figure 4.3 Operation when SP Value Is Odd
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1 Features
* Two interrupt control modes Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with ICR An interrupt control register (ICR) is provided for setting in each module interrupt priority levels for all interrupt requests excluding NMI and address breaks. * Three-level interrupt mask control By means of the interrupt control mode, I and UI bits in CCR and ICR, 3-level interrupt mask control is performed. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Forty-nine external interrupt pins NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level sensing, can be independently selected for IRQ15 to IRQ0. When the EIVS bit in the system control register 3 (SYSCR3) is cleared to 0, the IRQ6 interrupt is generated by IRQ6 or KIN7 to KIN0. The IRQ7 interrupt is generated by IRQ7, KIN15 to KIN8, or WUE7 to WUE0. When the EIVS bit in the system control register 3 (SYSCR3) is set to 1, an interrupt is requested at the falling edge of KIN15 to KIN0 and WUE15 to WUE0. * DTC control The DTC can be activated by an interrupt request. * Two interrupt vector addresses are selectable H8S/2140B Group compatible interrupt vector addresses or extended interrupt vector addresses are selected depending on the EIVS bit in system control register 3 (SYSCR3). In extended mode, independent vector addresses are assigned for the interrupt vector addresses of KIN7 to KIN0, KIN15 to KIN8, and WUE7 to WUE0 interrupts. * General ports for IRQ15 to IRQ0 input are selectable
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Section 5 Interrupt Controller
EIVS
SYSCR3
INTM1, INTM0
CPU
SYSCR
NMIEG
NMI input
IRQ input
NMI input IRQ input ISR ISCR IER
Priority level determination
Interrupt request Vector number
KMIMR WUEMR KIN input WUE input Internal interrupt sources SWDTEND to IBFI3
ICR Interrupt controller
KIN, WUE input
I, UI CCR
Legend: ICR ISCR IER ISR KMIMR WUEMR SYSCR SYSCR3
: Interrupt control register : IRQ sense control register : IRQ enable register : IRQ status register : Keyboard matrix interrupt mask register : Wake-up event interrupt mask register : System control register : System control register 3
Figure 5.1 Block Diagram of Interrupt Controller
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Section 5 Interrupt Controller
5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller. Table 5.1
Symbol NMI IRQ15 to IRQ0, ExIRQ15 to ExIRQ0
Pin Configuration
I/O Input Input Function Nonmaskable external interrupt pin Rising edge or falling edge can be selected Maskable external interrupt pins Rising-edge, falling-edge, or both-edge detection, or levelsensing, can be selected individually for each pin. To which pin the IRQ15 to IRQ0 interrupt is input can be selected from the IRQn and ExIRQn pins. (n = 15 to 0) Maskable external interrupt pins When EIVS = 0, falling-edge or level-sensing can be selected. When EIVS = 1, an interrupt is requested at the falling edge.
KIN15 to KIN0
Input
WUE15 to WUE8 WUE7 to WUE0
Input Input
Maskable external interrupt pins An interrupt is requested at the falling edge. Maskable external interrupt pins When EIVS = 0, falling-edge or level-sensing can be selected. When EIVS = 1, an interrupt is requested at the falling edge.
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Section 5 Interrupt Controller
5.3
Register Descriptions
The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). For details on system control register 3 (SYSCR3), see section 3.2.4, System Control Register 3 (SYSCR3). * * * * * * * * * Interrupt control registers A to D (ICRA to ICRD) Address break control register (ABRKCR) Break address registers A to C (BARA to BARC) IRQ sense control registers (ISCR16H, ISCR16L, ISCRH, ISCRL) IRQ enable registers (IER16, IER) IRQ status registers (ISR16, ISR) Keyboard matrix interrupt mask registers (KMIMRA, KMIMR) Wake-up event interrupt mask registers (WUEMR, WUEMRB) IRQ sense port select registers (ISSR16, ISSR)
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5.3.1
Interrupt Control Registers A to D (ICRA to ICRD)
The ICR registers set interrupt control levels for interrupts other than NMI. The correspondence between interrupt sources and ICRA to ICRD settings is shown in tables 5.2 and 5.3.
Bit 7 to 0 Bit Name ICRn7 to ICRn0 Initial Value All 0 R/W R/W Description Interrupt Control Level 0: Corresponding interrupt source is interrupt control level 0 (no priority) 1: Corresponding interrupt source is interrupt control level 1 (priority) Note: n: A to D
Table 5.2
Correspondence between Interrupt Source and ICR (H8S/2140B Group Compatible Vector Mode: EIVS = 0)
Register
Bit 7 6 5 4 3 2 1 0 Note:
Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0
ICRA IRQ0 IRQ1 IRQ2, IRQ3 IRQ4, IRQ5 IRQ6, IRQ7 DTC WDT_0 WDT_1
ICRB A/D converter FRT -- -- TMR_0 TMR_1 TMR_X, TMR_Y KBU
ICRC -- SCI_1 SCI_2 IIC_0 IIC_1 -- LPC --
ICRD IRQ8 to IRQ11 IRQ12 to IRQ15 -- WUE8 to WUE15 TPU_0 TPU_1 TPU_2 --
n: A to D : Reserved. The initial value should not be changed.
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Table 5.3
Correspondence between Interrupt Source and ICR (Extended Vector Mode: EIVS = 1)
Register
Bit 7 6 5 4 3 2 1 0 Note:
Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0
ICRA IRQ0 IRQ1 IRQ2, IRQ3 IRQ4, IRQ5 IRQ6, IRQ7 DTC WDT_0 WDT_1
ICRB A/D converter FRT -- -- TMR_0 TMR_1 TMR_X, TMR_Y KBU
ICRC -- SCI_1 SCI_2 IIC_0 IIC_1 -- LPC --
ICRD IRQ8 to IRQ11 IRQ12 to IRQ15 KIN0 to KIN15 WUE0 to WUE15 TPU channel 0 TPU channel 1 TPU channel 2 --
n: A to D : Reserved. The initial value should not be changed.
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5.3.2
Address Break Control Register (ABRKCR)
ABRKCR controls the address breaks. When both the CMF flag and BIE bit are set to 1, an address break is requested.
Bit 7 Bit Name CMF Initial Value Undefined R/W R Description Condition Match Flag Address break source flag. Indicates that an address specified by BARA to BARC is prefetched. [Clearing condition] When an exception handling is executed for an address break interrupt. [Setting condition] When an address specified by BARA to BARC is prefetched while the BIE bit is set to 1. 6 to 1 -- All 0 R Reserved These bits are always read as 0 and cannot be modified. 0 BIE 0 R/W Break Interrupt Enable Enables or disables address break. 0: Disabled 1: Enabled
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5.3.3
Break Address Registers A to C (BARA to BARC)
The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared. * BARA
Bit 7 to 0 Bit Name A23 to A16 Initial Value All 0 R/W R/W Description Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus.
* BARB
Bit 7 to 0 Bit Name A15 to A8 Initial Value All 0 R/W R/W Description Addresses 15 to 8 The A15 to A8 bits are compared with A15 to A8 in the internal address bus.
* BARC
Bit 7 to 1 Bit Name A7 to A1 Initial Value All 0 R/W R/W Description Addresses 7 to 1 The A7 to A1 bits are compared with A7 to A1 in the internal address bus. 0 -- 0 R Reserved This bit is always read as 0 and cannot be modified.
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5.3.4
IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ0. * ISCR16H
Bit 76 54 32 10 Bit Name IRQ15SCBIR Q15SCA IRQ14SCBIR Q14SCA IRQ13SCBIR Q13SCA IRQ12SCBIR Q12SCA Initial Value 00 00 00 00 R/W Description
R/WR IRQn Sense Control B IRQn Sense Control A /W R/WR BA /W 00: Interrupt request generated at low level of IRQn or ExIRQn input R/WR /W 01: Interrupt request generated at falling edge of IRQn or ExIRQn input R/WR /W 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 15 to 12) Note: The IRQn or ExIRQn pin is selected by IRQ sense port select register 16 (ISSR16).
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* ISCR16L
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB IRQ9SCA IRQ8SCB IRQ8SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A BA 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 11 to 8) Note: The IRQn or ExIRQn pin is selected by IRQ sense port select register 16 (ISSR16).
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* ISCRH
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A BA 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 7 to 4) Note: The IRQn or ExIRQn pin is selected by the IRQ sense port select register (ISSR).
* ISCRL
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W /W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A BA 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 3 to 0) Note: The IRQn or ExIRQn pin is selected by the IRQ sense port select register (ISSR).
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5.3.5
IRQ Enable Registers (IER16, IER)
The IER registers enable and disable interrupt requests IRQ15 to IRQ0. * IER16
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ15E IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Enable The IRQn interrupt request is enabled when this bit is 1. (n = 15 to 8)
* IER
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Enable The IRQn interrupt request is enabled when this bit is 1. (n = 7 to 0)
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5.3.6
IRQ Status Registers (ISR16, ISR)
The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. * ISR16
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F Initial Value 0 0 0 0 0 0 0 0 R/W Description
R/(W)* [Setting condition] R/(W)* When the interrupt source selected by the ISCR16 R/(W)* registers occurs R/(W)* [Clearing conditions] R/(W)* * When writing 0 to IRQnF flag after reading IRQnF = 1 R/(W)* * When interrupt exception handling is executed R/(W)* when low-level detection is set and IRQn or R/(W)* ExIRQn input is high * When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set
(n = 15 to 8) Note: The IRQn or ExIRQn pin is selected by IRQ sense port select register 16 (ISSR16). Note: * Only 0 can be written for clearing the flag.
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* ISR
Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 R/W Description
R/(W)* [Setting condition] R/(W)* When the interrupt source selected by the ISCR R/(W)* registers occurs R/(W)* [Clearing conditions] R/(W)* * When writing 0 to IRQnF flag after reading IRQnF = 1 R/(W)* * When interrupt exception handling is executed R/(W)* when low-level detection is set and IRQn or R/(W)* ExIRQn input is high * When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set
(n = 7 to 0) Note: The IRQn or ExIRQn pin is selected by the IRQ sense port select register (ISSR). Note: * Only 0 can be written for clearing the flag.
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5.3.7
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR, WUEMRB)
The KMIMR and WUEMR registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0) and wake-up event interrupt inputs (WUE15 to WUE0). * KMIMRA
Bit 7 6 5 4 3 2 1 0 Bit Name KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask These bits enable or disable a key-sensing input interrupt request (KIN15 to KIN8). 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request
* KMIMR
Bit 7 6 5 4 3 2 1 0 Bit Name KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial Value 1 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask These bits enable or disable a key-sensing input interrupt request (KIN7 to KIN0). 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request When the EIVS bit in SYSCR3 is cleared to 0, the KMIMR6 bit also simultaneously controls enabling and disabling of the IRQ6 interrupt request. In this case, the initial value of the KMIMR6 bit is 0. When the EIVS bit is set to 1, the initial value of the KMIMR6 bit becomes 1.
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* WUEMR
Bit 7 6 5 4 3 2 1 0 Bit Name WUEMR15 WUEMR14 WUEMR13 WUEMR12 WUEMR11 WUEMR10 WUEMR9 WUEMR8 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Wake-Up Event Interrupt Mask These bits enable or disable a wake-up event input interrupt request (WUE15 to WUE8). 0: Enables a wake-up event input interrupt request 1: Disables a wake-up event input interrupt request
* WUEMRB
Bit 7 6 5 4 3 2 1 0 Bit Name WUEMR7 WUEMR6 WUEMR5 WUEMR4 WUEMR3 WUEMR2 WUEMR1 WUEMR0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Wake-Up Event Interrupt Mask These bits enable or disable a wake-up event input interrupt request (WUE7 to WUE0). 0: Enables a wake-up event input interrupt request 1: Disables a wake-up event input interrupt request
Figure 5.2 shows the relation between the IRQ7 and IRQ6 interrupts, KIN15 to KIN0 interrupts, WUE7 to WUE0 interrupts, KMIMR, KMIMRA, and WUEMRB in H8S/2140B Group compatible vector mode. The relation in extended vector mode is shown in figure 5.3.
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KMIMR0 (Initial value of 1) P60/KIN0 KMIMR5 (Initial value of 1) P65/KIN5 KMIMR6 (Initial value of 0) P66/KIN6/IRQ6
IRQ6 internal signal
Edge-level selection enable/disable circuit
IRQ6 interrupt
KMIMR7 (Initial value of 1) P67/KIN7/IRQ7 P42/ExIRQ7
ISS7
KMIMR8 (Initial value of 1) PA0/KIN8 KMIMR9 (Initial value of 1) PA1/KIN9
IRQ7 internal signal
Edge-level selection enable/disable circuit
IRQ7 interrupt
WUEMR7 (Initial value of 1) PB7/WUE7
Note: The ISS7 bit is an external interrupt pin switch bit. For details, see section 5.3.8, IRQ Sence Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR).
Figure 5.2 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB (H8S/2140B Group Compatible Vector Mode: EIVS = 0) In H8S/2140B Group compatible vector mode, interrupt input from the IRQ7 pin is ignored when even one of the KMIMR15 to KMIMR8 and WUEMR7 to WUEMR0 bits is cleared to 0. If the KIN7 to KIN0 pins or KIN15 to KIN8 pins, and WUE7 to WUE0 pins are specified to be used as key-sensing interrupt input pins and wake-up event interrupt input pins, the interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7) must be set to low-level sensing or falling-edge sensing. Note that interrupt input cannot be made from the ExIRQ6 pin.
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KMIMR0 (Initial value of 1) P60/KIN0
KMIMR5 (Initial value of 1) P65/KIN5 KMIMR6 (Initial value of 1) P66/KIN6/IRQ6 P52/ExIRQ6 KMIMR7 (Initial value of 1) P67/KIN7/IRQ7 P42/ExIRQ7 KMIMR8 (Initial value of 1) PA0/KIN8 KMIMR15 (Initial value of 1) PA7/KIN15 WUEMR0 (Initial value of 1) PB0/WUE0 WUEMR7 (Initial value of 1) PB7/WUE7 WUEMR8 (Initial value of 1) PC0/WUE8 WUEMR15 (Initial value of 1) PC7/WUE15
ISS7
KIN internal signal
Falling-edge detection circuit Edge-level selection enable/disable circuit Edge-level selection enable/disable circuit
KIN interrupt (KIN7 to KIN0)
IRQ6 interrupt
IRQ7 interrupt
KINA internal signal
Falling-edge detection circuit
KINA interrupt (KIN15 to KIN8)
WUEB internal signal
Falling-edge detection circuit
WUEB interrupt (WUE7 to WUE0)
WUE internal signal
Falling-edge detection circuit
WUE interrupt (WUE15 to WUE8)
Note: The ISS7 bit is an external interrupt pin switch bit. For details, see section 5.3.8, IRQ Sence Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR).
Figure 5.3 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts, KMIMR, KMIMRA, and WUEMRB (Extended Vector Mode: EIVS = 1) In extended vector mode, the initial value of the KMIMR6 bit is 1. Accordingly, it does not enable of disable the IRQ6 pin interrupt. The interrupt input from the ExIRQ6 pin becomes the IRQ6 interrupt request.
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5.3.8
IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR)
ISSR16 and ISSR select the IRQ15 to IRQ0 interrupt external input from IRQ15 to IRQ0 pins and ExIRQ15 to ExIRQ0 pins. * ISSR16
Bit 7 6 5 4 3 2 1 0 Bit Name ISS15 ISS14 ISS13 ISS12 ISS11 ISS10 ISS9 ISS8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: P97/IRQ15 is selected 1: PG7/ExIRQ15 is selected 0: P95/IRQ14 is selected 1: PG6/ExIRQ14 is selected 0: P94/IRQ13 is selected 1: PG5/ExIRQ13 is selected 0: P93/IRQ12 is selected 1: PG4/ExIRQ12 is selected 0: PF3/IRQ11 is selected 1: PG3/ExIRQ11 is selected 0: PF2/IRQ10 is selected 1: PG2/ExIRQ10 is selected 0: PF1/IRQ9 is selected 1: PG1/ExIRQ9 is selected 0: PF0/IRQ8 is selected 1: PG0/ExIRQ8 is selected
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* ISSR
Bit 7 6 5 4 3 2 1 0 Bit Name ISS7 ISS5 ISS4 ISS3 ISS2 ISS1 ISS0 Initial Value 0 0 0 0 0 0 0 0 R/W Description R/W 0: P67/IRQ7 is selected 1: P42/ExIRQ7 is selected R/W Reserved The initial values should not be changed. R/W 0: P86/IRQ5 is selected 1: P75/ExIRQ5 is selected R/W 0: P85/IRQ4 is selected 1: P74/ExIRQ4 is selected R/W 0: P84/IRQ3 is selected 1: P73/ExIRQ3 is selected R/W 0: P90/IRQ2 is selected 1: P72/ExIRQ2 is selected R/W 0: P91/IRQ1 is selected 1: P71/ExIRQ1 is selected R/W 0: P92/IRQ0 is selected 1: P70/ExIRQ0 is selected
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5.4
5.4.1
Interrupt Sources
External Interrupt Sources
The interrupt sources of external interrupts are NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15 to WUE0. These interrupts can be used to restore this LSI from software standby mode. (1) NMI Interrupt
The nonmaskable external interrupt NMI is the highest-priority interrupt, and is always accepted regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or falling edge on the NMI pin. (2) IRQ15 to IRQ0 Interrupts
Interrupts IRQ15 to IRQ0 are requested by an input signal at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ0. Interrupts IRQ15 to IRQ0 have the following features: * The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an independent vector address. * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ0. * Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER. * The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. When the interrupts are requested while IRQ15 to IRQ0 interrupt requests are generated at low level of IRQn input, hold the corresponding IRQ input at low level until the interrupt handling starts. Then put the relevant IRQ input back to high level within the interrupt handling routine and clear the IRQnF bit (n = 15 to 0) in ISR to 0. If the relevant IRQ input is put back to high level before the interrupt handling starts, the relevant interrupt may not be executed. The detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. Therefore, when a pin is used as an external interrupt input pin, clear the DDR bit of the corresponding port to 0 so it is not used as an I/O pin for another function. A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.4.
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IRQnSCA, IRQnSCB
IRQnE
IRQn ISSm ExIRQn
Edge/level detection circuit
IRQnF S R Q
IRQn interrupt request
n = 15 to 0 m = 15 to 7 and 5 to 0
Clear signal
Note: Switching between the IRQ6 and ExIRQ6 pins is controlled by the EIVS bit in SYSCR3.
Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0 (3) KIN15 to KIN0 Interrupts and WUE15 to WUE0 Interrupts
Interrupts KIN15 to KIN0 and WUE15 to WUE0 are requested by an input signal at pins KIN15 to KIN0 and WUE15 to WUE0. Interrupts KIN15 to KIN0 and WUE15 to WUE0 have the following features according to the setting of the EIVS bit in system control register 3 (SYSCR3). * H8S/2140B Group compatible vector mode (EIVS = 0 in SYSCR3) Interrupts WUE7 to WUE0 and KIN15 to KIN8 correspond to interrupt IRQ7, and interrupts KIN7 to KIN0 correspond to interrupt IRQ6. The pin conditions for generating an interrupt request, whether the interrupt request is enabled, interrupt control level setting, and status of the interrupt request for the above interrupts are in accordance with the settings and status of the relevant interrupts IRQ7 and IRQ6. Interrupt settings for interrupts WUE15 to WUE8 can be made regardless of the settings for interrupts IRQ7 and IRQ6. Enabling or disabling of interrupt requests KIN15 to KIN0 and WUE15 to WUE0 can be selected using KMIMRA, KMIMR, WUEMRB, and WUEMR. If the KIN7 to KIN0 pins or WUE15 to WUE8 pins, and WUE7 to WUE0 pins are specified to be used as key-sensing interrupt input pins and wake-up event interrupt input pins, the interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7) must be set to low-level sensing or falling-edge sensing. When using the IRQ6 pin as the IRQ6 interrupt input pin, the KMIMR6 bit must be cleared to 0. When using the IRQ7 pin as the IRQ7 interrupt input pin, the KMIMR15 to KMIMR8 and WUEMR7 to WUEMR0 bits must all be set to 1. If even one of these bits is cleared to 0, the IRQ7 interrupt input from the IRQ7 pin is ignored.
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* Extended vector mode (EIVS = 1 in SYSCR3) Interrupts KIN15 to KIN8, KIN7 to KIN0, WUE15 to WUE8, and WUE7 to WUE0 each form a group. The interrupt exception handling for an interrupt request from the same group is started at the same vector address. An interrupt request is generated by a falling edge at pins KIN15 to KIN0 and WUE15 to WUE0. Enabling or disabling of interrupt requests KIN15 to KIN0 and WUE15 to WUE0 can be selected using KMIMRA, KMIMR, WUEMRB, and WUEMR. The status of interrupt requests KIN15 to KIN0 and WUE15 to WUE0 are not indicated. An IRQ6 interrupt is enabled only by input to the ExIRQ6 pin. The IRQ6 pin is only available for a KIN interrupt input, and functions as the KIN6 pin. The initial value of the KMIMR6 bit is 1. For the IRQ7 interrupt, either the IRQ7 pin or ExIRQ7 pin can be selected as the input pin using the ISS7 bit. The IRQ7 interrupt is not affected by the settings of the KMIMR15 to KMIMR8 and WUEMR7 to WUEMR0 bits. The detection of interrupts KIN15 to KIN0 and WUE15 to WUE0 does not depend on whether the relevant pin has been set for input or output. Therefore, when a pin is used as an external interrupt input pin, clear the DDR bit of the corresponding port to 0 so it is not used as an I/O pin for another function. A block diagram of interrupts KIN15 to KIN0 and WUE15 to WUE0 is shown in figure 5.5.
WUEMRn
Falling-edge detection circuit WUEn input n = 15 to 8 Clear signal
S R
Q
WUEn interrupt request
Figure 5.5 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE0 (Example of WUE15 to WUE8)
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5.4.2
Internal Interrupt Sources
Internal interrupts issued from the on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. * The control level for each interrupt can be set by ICR. * The DTC can be activated by an interrupt request from an on-chip peripheral module. * An interrupt request that activates the DTC is not affected by the interrupt control mode or the status of the CPU interrupt mask bits.
5.5
Interrupt Exception Handling Vector Tables
Tables 5.4 and 5.5 list interrupt exception handling sources, vector addresses, and interrupt priorities. H8S/2140B Group compatible vector mode or extended vector mode can be selected for the vector addresses by the EIVS bit in system control register 3 (SYSCR3). For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt requests from modules that are set to interrupt control level 1 (priority) by the interrupt control level and the I and UI bits in CCR are given priority and processed before interrupt requests from modules that are set to interrupt control level 0 (no priority).
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Table 5.4
Interrupt Sources, Vector Addresses, and Interrupt Priorities (H8S/2140B Group Compatible Vector Mode)
Vector Address Name NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 IRQ7, KIN15 to KIN8, WUE7 to WUE0 Vector Number 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Normal Mode H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A H'003C H'003E H'0040 H'0042 H'0044 H'0046 H'0048 H'004A H'004C H'004E H'0050 H'0052 H'0054 Advanced Mode H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 H'00006C H'000070 H'000074 H'000078 H'00007C H'000080 H'000084 H'000088 H'00008C H'000090 H'000094 H'000098 H'00009C H'0000A0 H'0000A4 H'0000A8 ICRD2 ICR -- ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 Priority High
Origin of Interrupt Source External pin
DTC WDT_0 WDT_1 --
SWDTEND (Software activation data transfer end) WOVI0 (Interval timer) WOVI1 (Interval timer) Address break
ICRA2 ICRA1 ICRA0 -- ICRB7 --
A/D converter ADI (A/D conversion end) Reserved for system use Reserved for system use Reserved for system use External pin TPU_0 Reserved for system use WUE15 to WUE8 TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TGI0V (Overflow 0) TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TGI1V (Overflow 1) TGI1U (Underflow 1)
ICRD4 ICRD3
TPU_1
Low
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Section 5 Interrupt Controller
Origin of Interrupt Source TPU_2
Vector Address Name TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TGI2V (Overflow 2) TGI2U (Underflow 2) Reserved for system use ICIA (Input capture A) ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) Reserved for system use Vector Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Normal Mode H'0056 H'0058 H'005A H'005C H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 H'0072 H'0074 H'0076 H'0078 H'007A H'007C H'007E H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AA H'00AC H'00AE Advanced Mode H'0000AC H'0000B0 H'0000B4 H'0000B8 H'0000BC H'0000C0 H'0000C4 H'0000C8 H'0000CC H'0000D0 H'0000D4 H'0000D8 H'0000DC H'0000E0 H'0000E4 H'0000E8 H'0000EC H'0000F0 H'0000F4 H'0000F8 H'0000FC H'000100 H'000104 H'000108 H'00010C H'000110 H'000114 H'000118 H'00011C H'000120 H'000124 H'000128 H'00012C H'000130 H'000134 H'000138 H'00013C H'000140 H'000144 H'000148 H'00014C H'000150 H'000154 H'000158 H'00015C ICRB6 ICR ICRD1 Priority High
FRT
External pin IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match B) OVI0 (Overflow) Reserved for system use CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture) CMIAX (Compare match A) CMIBX (Compare match B) OVIX (Overflow) Reserved for system use Reserved for system use Reserved for system use Reserved for system use Reserved for system use SCI_1 ERI1 (Reception error 1) RXI1 (Reception completion 1) TXI1 (Transmission data empty 1) TEI1 (Transmission end 1)
ICRD7
ICRD6
ICRB3
TMR_1
ICRB2
TMR_X TMR_Y
ICRB1
--
ICRC6
Low
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Section 5 Interrupt Controller
Origin of Interrupt Source SCI_2
Vector Address Name ERI2 (Reception error 2) RXI2 (Reception completion 2) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) IICI0 (1-byte transmission/reception completion) Reserved for system use IICI1 (1-byte transmission/reception completion) Reserved for system use KBIA (Reception completion A) KBIB (Reception completion B) KBIC (Reception completion C) KBTIA (Transmission completion A)/ KBCA (1st KCLKA) KBTIB (Transmission completion B)/ KBCB (1st KCLKB) KBTIC (Transmission completion C)/ KBCC (1st KCLKC) Reserved for system use Reserved for system use Reserved for system use LMCI (LPC/FW command reception completion) LMCUI (LPC/FW user command reception completion) IBFI4 (IDR4 reception completion) ERR1 (Transfer error, etc.) IBFI1 (IDR1 reception completion) IBFI2 (IDR2 reception completion) IBFI3 (IDR3 reception completion) Reserved for system use Vector Normal Number Mode 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 127 H'00B0 H'00B2 H'00B4 H'00B6 H'00B8 H'00BA H'00BC H'00BE H'00C0 H'00C2 H'00C4 H'00C6 H'00C8 H'00CA H'00CC H'00CE H'00D0 H'00D2 H'00D4 H'00D6 H'00D8 H'00DA H'00DC H'00DE H'00E0 H'00FE Advanced Mode H'000160 H'000164 H'000168 H'00016C H'000170 H'000174 H'000178 H'00017C H'000180 H'000184 H'000188 H'00018C H'000190 H'000194 H'000198 H'00019C H'0001A0 H'0001A4 H'0001A8 H'0001AC H'0001B0 H'0001B4 H'0001B8 H'0001BC H'0001C0 H'0001FC Low ICRC1 ICRB0 ICRC3 ICR ICRC5 Priority High
IIC_0
ICRC4
IIC_1
KBU
LPC
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Section 5 Interrupt Controller
Table 5.5
Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode)
Vector Address Name NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Vector Number 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Normal Mode H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A H'003C H'003E H'0040 H'0042 H'0044 H'0046 H'0048 H'004A H'004C H'004E H'0050 H'0052 H'0054 Advanced Mode H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 H'00006C H'000070 H'000074 H'000078 H'00007C H'000080 H'000084 H'000088 H'00008C H'000090 H'000094 H'000098 H'00009C H'0000A0 H'0000A4 H'0000A8 ICRD2 ICR -- ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0 -- ICRB7 -- ICRD5 ICRD4 ICRD3 Priority High
Origin of Interrupt Source External pin
DTC WDT_0 WDT_1 --
SWDTEND (Software activation data transfer end) WOVI0 (Interval timer) WOVI1 (Interval timer) Address break
A/D converter ADI (A/D conversion end) Reserved for system use External pin KIN7 to KIN0 KIN15 to KIN8 WUE7 to WUE0 WUE15 to WUE8 TPU_0 TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TGI0V (Overflow 0) TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TGI1V (Overflow 1) TGI1U (Underflow 1)
TPU_1
Low
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Section 5 Interrupt Controller
Origin of Interrupt Source TPU_2
Vector Address Name TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TGI2V (Overflow 1) TGI2U (Underflow 2) Reserved for system use ICIA (Input capture A) ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) Reserved for system use IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Vector Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Normal Mode H'0056 H'0058 H'005A H'005C H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 H'0072 H'0074 H'0076 H'0078 H'007A H'007C H'007E H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 Advanced Mode H'0000AC H'0000B0 H'0000B4 H'0000B8 H'0000BC H'0000C0 H'0000C4 H'0000C8 H'0000CC H'0000D0 H'0000D4 H'0000D8 H'0000DC H'0000E0 H'0000E4 H'0000E8 H'0000EC H'0000F0 H'0000F4 H'0000F8 H'0000FC H'000100 H'000104 H'000108 H'00010C H'000110 H'000114 H'000118 H'00011C H'000120 H'000124 H'000128 H'00012C H'000130 H'000134 H'000138 H'00013C H'000140 H'000144 H'000148 H'00014C ICRB6 ICR ICRD1 Priority High
FRT
External pin
ICRD7
ICRD6
TMR_0
CMIA0 (Compare match A) CMIB0 (Compare match B) OVI0 (Overflow) Reserved for system use CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture) CMIAX (Compare match A) CMIBX (Compare match B) OVIX (Overflow) Reserved for system use Reserved for system use Reserved for system use Reserved for system use Reserved for system use
ICRB3
TMR_1
ICRB2
TMR_X TMR_Y
ICRB1
--
Low
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Section 5 Interrupt Controller
Origin of Interrupt Source SCI_1
Vector Address Name ERI1 (Reception error 1) RXI1 (Reception completion 1) TXI1 (Transmission data empty 1) TEI1 (Transmission end 1) ERI2 (Reception error 2) RXI2 (Reception completion 2) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) IICI0 (1-byte transmission/reception completion) Reserved for system use IICI1 (1-byte transmission/reception completion) Reserved for system use KBIA (Reception completion A) KBIB (Reception completion B) KBIC (Reception completion C) KBTIA (Transmission completion A)/ KBCA (1st KCLKA) KBTIB (Transmission completion B)/ KBCB (1st KCLKB) KBTIC (Transmission completion C)/ KBCC (1st KCLKC) Reserved for system use Reserved for system use Reserved for system use LMCI (LPC/FW command reception completion) LMCUI (LPC/FW user command reception completion) IBFI4 (IDR4 reception completion) ERR1 (Transfer error, etc.) IBFI1 (IDR1 reception completion) IBFI2 (IDR2 reception completion) IBFI3 (IDR3 reception completion) Reserved for system use Vector Normal Number Mode 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 127 H'00A8 H'00AA H'00AC H'00AE H'00B0 H'00B2 H'00B4 H'00B6 H'00B8 H'00BA H'00BC H'00BE H'00C0 H'00C2 H'00C4 H'00C6 H'00C8 H'00CA H'00CC H'00CE H'00D0 H'00D2 H'00D4 H'00D6 H'00D8 H'00DA H'00DC H'00DE H'00E0 H'00FE Advanced Mode H'000150 H'000154 H'000158 H'00015C H'000160 H'000164 H'000168 H'00016C H'000170 H'000174 H'000178 H'00017C H'000180 H'000184 H'000188 H'00018C H'000190 H'000194 H'000198 H'00019C H'0001A0 H'0001A4 H'0001A8 H'0001AC H'0001B0 H'0001B4 H'0001B8 H'0001BC H'0001C0 H'0001FC Low ICRC1 ICRB0 ICRC3 ICR ICRC6 Priority High
SCI_2
ICRC5
IIC_0
ICRC4
IIC_1
KBU
LPC
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Section 5 Interrupt Controller
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI and address break interrupts are always accepted except for in the reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.6 shows the interrupt control modes. Table 5.6 Interrupt Control Modes
Priority Setting Registers ICR Interrupt Mask Bits I
Interrupt SYSCR Control Mode INTM1 INTM0 0 0 0
Description Interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 3-level interrupt mask control is performed by the I and UI bits. Priority levels can be set with ICR.
1
0
1
ICR
I, UI
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Section 5 Interrupt Controller
Figure 5.6 shows a block diagram of the priority determination circuit.
I ICR UI
Interrupt source
Interrupt acceptance control and 3-level mask control
Default priority determination
Vector number
Interrupt control modes 0 and 1
Figure 5.6 Block Diagram of Interrupt Control Operation
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Section 5 Interrupt Controller
(1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.7 shows the interrupts selected in each interrupt control mode. Table 5.7 Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bits Interrupt Control Mode I 0 0 1 1 0 1 UI * * * 0 1 [Legend] *: Don't care Selected Interrupts All interrupts (interrupt control level 1 has priority) NMI and address break interrupts All interrupts (interrupt control level 1 has priority) NMI, address break, and interrupt control level 1 interrupts NMI and address break interrupts
(2) Default Priority Determination The priority is determined for the selected interrupt, and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.8 shows operations and control signal functions in each interrupt control mode.
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Section 5 Interrupt Controller
Table 5.8
Operations and Control Signal Functions in Each Interrupt Control Mode
Setting INTM0 0 1 I IM IM Interrupt Acceptance Control 3-Level Control UI -- IM ICR PR PR
Interrupt Control Mode INTM1 0 1 0
Default Priority Determination
[Legend] : Interrupt operation control is performed IM: Used as an interrupt mask bit PR: Priority is set --: Not used
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests other than NMI and address break are masked by ICR and the I bit of CCR in the CPU. Figure 5.7 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. If the I bit in CCR is set to 1, the interrupt controller holds pending interrupt requests other than NMI and address break. If the I bit is cleared to 0, any interrupt request is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts.
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Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
Program execution state
Interrupt generated? Yes Yes
No
NMI No
An interrupt with interrupt control level 1?
No
Hold pending
Yes No IRQ0 Yes No IRQ1 Yes IRQ0 Yes IRQ1 IBFI3 Yes Yes IBFI3 Yes No No
I=0 Yes
No
Save PC and CCR
I
1
Read vector address
Branch to interrupt handling routine
Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
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Section 5 Interrupt Controller
5.6.2
Interrupt Control Mode 1
In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than NMI and address break by comparing the I and UI bits in CCR in the CPU, and the ICR setting. * An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending. * An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is cleared to 0. When both the I and UI bits are set to 1, the interrupt request is held pending. For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set to 1, and ICRA to ICRD are set to H'20, H'00, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are set to interrupt control level 1, and other interrupts are set to interrupt control level 0) is shown below. Figure 5.8 shows a state transition diagram. * All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 ...) * Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI = 0. * Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1.
I All interrupt requests are accepted I
0 0
1, UI
Only NMI, address break, and interrupt control level 1 interrupt requests are accepted
I Exception handling execution or I 1, UI 1
0
UI
0
Exception handling execution or UI 1
Only NMI and address break interrupt requests are accepted
Figure 5.8 State Transition in Interrupt Control Mode 1
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Section 5 Interrupt Controller
Figure 5.9 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or when the I bit is set to 1 while the UI bit is cleared to 0. An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0. When both the I and UI bits are set to 1, only NMI and address break interrupt requests are accepted, and other interrupts are held pending. When the I bit is cleared to 0, the UI bit does not affect acceptance of interrupt requests. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The I and UI bits in CCR are set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
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Section 5 Interrupt Controller
Program execution state No
Interrupt generated? Yes Yes
NMI No
An interrupt with interrupt control level 1?
No
Hold pending
Yes No No IRQ1 Yes IBFI3 Yes No IRQ0 Yes IRQ1 Yes IBFI3 Yes No
IRQ0 Yes
I=0 Yes
No
I=0 No Yes
No
UI = 0 Yes Save PC and CCR
I
1, UI
1
Read vector address Branch to interrupt handling routine
Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1
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Section 5 Interrupt Controller
5.6.3
Interrupt Exception Handling Sequence
Figure 5.10 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
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Interrupt is accepted Instruction prefetch Stack access Vector fetch Internal processing Prefetch of instruction in Internal processing interrupt handling routine
(1)
(3)
Section 5 Interrupt Controller
Interrupt level determination and wait for end of instruction
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(5) (7) (9) (11) (13) (2) (4)
Interrupt request signal
Internal address bus
Internal read signal
Internal write signal
Figure 5.10 Interrupt Exception Handling
(6)
(8)
Internal data bus
(10)
(12)
(14)
(1)
(2) (4) (3) (5) (7)
Instruction prefetch address (Not executed. Address is saved as PC contents, becoming return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP - 2 SP - 4
(6) (8) (9) (11) (10) (12) (13) (14)
Saved PC and CCR Vector address Start address of interrupt handling routine (contents of vector address) Start address of interrupt handling routine ((13) = (10) (12)) First instruction in interrupt handling routine
Section 5 Interrupt Controller
5.6.4
Interrupt Response Times
Table 5.9 shows interrupt response times - the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 5.9
No. 1 2 3 4 5 6
Interrupt Response Times
Normal Mode
1
Execution Status Interrupt priority determination*
Advanced Mode 3 1 to 21 2 2 2 2 12 to 32
3
Number of wait states until executing instruction 1 to 21 ends*2 Saving of PC and CCR in stack Vector fetch Instruction fetch*
3
2 1 2 2 11 to 31
Internal processing*4 Total (using on-chip memory)
Notes: 1. 2. 3. 4.
Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and prefetch of interrupt handling routine. Internal processing after interrupt acceptance and internal processing after vector fetch.
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Section 5 Interrupt Controller
5.6.5
DTC Activation by Interrupt
The DTC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to CPU * Activation request to DTC * Both of the above For details on interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC). Figure 5.11 shows a block diagram of the DTC and interrupt controller.
Interrupt request IRQ interrupt Interrupt source clear signal
Selection circuit
Select signal Clear signal DTCER
DTC activation request vector number
Control logic Clear signal
DTC
On-chip peripheral module
DTVECR
SWDTE clear signal
Interrupt controller
Determination of priority
CPU interrupt request vector number CPU
I, UI
Figure 5.11 Interrupt Control for DTC The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source
It is possible to select a DTC activation request or CPU interrupt request for an interrupt source with the DTCE bit in DTCERA to DTCERE of the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit in MRB of the DTC. When the DTC performs the specified number of data transfers and the transfer counter reaches 0, following the DTC data transfer the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU.
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Section 5 Interrupt Controller
(2)
Determination of Priority
The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.4, Location of Register Information and DTC Vector Table, for the respective priorities. (3) Operation Order
If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.10 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit in DTCERA to DTCERE of the DTC and the DISEL bit in MRB of the DTC. Table 5.10 Interrupt Source Selection and Clearing Control
Settings DTC DTCE 0 1 [Legend] : DISEL * 0 1 x Interrupt Source Selection/Clearing Control DTC CPU x
The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. x: The relevant interrupt cannot be used. *: Don't care
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Section 5 Interrupt Controller
5.7
5.7.1
Address Breaks
Features
With this LSI, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed. This function can be used to detect the beginning of execution of a bug location in the program, and branch to a correction routine. 5.7.2 Block Diagram
Figure 5.12 shows a block diagram of the address break function.
BAR
ABRKCR
Match signal Comparator Control logic
Address break interrupt request
Internal address
Prefetch signal (internal signal)
Figure 5.12 Block Diagram of Address Break Function
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Section 5 Interrupt Controller
5.7.3
Operation
ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority. When the interrupt is accepted, interrupt exception handling is started on completion of the currently executing instruction. With an address break interrupt, interrupt mask control by the I and UI bits in the CPU's CCR is ineffective. The register settings when the address break function is used are as follows. 1. Set the break address in bits A23 to A1 in BAR. 2. Set the BIE bit in ABRKCR to 1 to enable address breaks. An address break will not be requested if the BIE bit is cleared to 0. When the setting condition occurs, the CMF flag in ABRKCR is set to 1 and an interrupt is requested. If necessary, the source should be identified in the interrupt handling routine. 5.7.4 Usage Notes
* With the address break function, the address at which the first instruction byte is located should be specified as the break address. Occurrence of the address break condition may not be recognized for other addresses. * In normal mode, no comparison is made with address lines A23 to A16. * If a branch instruction (Bcc, BSR) jump instruction (JMP, JSR), RTS instruction, or RTE instruction is located immediately before the address set in BAR, execution of this instruction will output a prefetch signal for that address, and an address break may be requested. This can be prevented by not making a break address setting for an address immediately following one of these instructions, or by determining within the interrupt handling routine whether interrupt handling was initiated by a genuine condition occurrence. * As an address break interrupt is generated by a combination of the internal prefetch signal and address, the timing of the start of interrupt exception handling depends on the content and execution cycle of the instruction at the set address and the preceding instruction. Figure 5.13 shows some address timing examples.
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Section 5 Interrupt Controller
* Program area in on-chip memory, 1-state execution instruction at specified break address
Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Stack save Vector fetch Internal Instruction operation fetch
Address bus
H'0310 H'0312 H'0314 H'0316
H'0318
SP-2
SP-4
H'0036
NOP NOP NOP execution execution execution
Interrupt exeption handling
Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Breakpoint NOP instruction is executed at breakpoint address H'0312 and next address, H'0314; fetch from address H'0316 starts after end of exception handling.
* Program area in on-chip memory, 2-state execution instruction at specified break address
Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch operation fetch Stack save Vector fetch Internal Instruction operation fetch
Address bus
H'0310 H'0312 H'0314 H'0316
H'0318
SP-2
SP-4
H'0036
NOP execution
MOV.W execution
Interrupt exeption handling
Break request signal H'0310 H'0312 H'0314 H'0316 NOP MOV.W #xx : 16,Rd NOP NOP Breakpoint MOV instruction is executed at breakpoint address H'0312, NOP instruction at next address, H'0316, is not executed; fetch from address H'0316 starts after end of exception handling.
* Program area in external memory (2-state access, 16-bit-bus access), 1-state execution instruction at specified break address (Not available in this LSI)
Instruction fetch Instruction fetch Instruction fetch Internal operation Stack save Vector fetch Internal operation
Address bus
H'0310
H'0312
H'0314
SP-2
SP-4
H'0036
NOP execution
Interrupt exeption handling
Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Breakpoint NOP instruction at breakpoint address H'0312 is not executed; fetch from address H'0312 starts after end of exception handling.
Figure 5.13 Examples of Address Break Timing
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Section 5 Interrupt Controller
5.8
5.8.1
Usage Notes
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.12 shows an example where the CMIEA bit in TCR of the TMR is cleared to 0. The above conflict will not occur if an interrupt enable bit or interrupt source flag is cleared to 0 while the interrupt is disabled.
TCR write cycle by CPU CMIA exception handling
Internal address bus
TCR address
Internal write signal
CMIEA
CMFA
CMIA interrupt signal
Figure 5.14 Conflict between Interrupt Generation and Disabling
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Section 5 Interrupt Controller
5.8.2
Instructions for Disabling Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request including NMI issued during data transfer is not accepted until data transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during data transfer, interrupt exception handling starts at a break in the transfer cycles. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W MOV.W BNE R4,R4 L1
5.8.4
Vector Address Switching
Switching between H8S/2140B Group compatible vector mode and extended vector mode must be done in a state with no interrupts occurring. If the EIVS bit in SYSCR3 is changed from 0 to 1 when interrupt input is enabled because the KIN15 to KIN0 and WUE15 to WUE0 pins are set at low level, a falling edge is detected, thus causing an interrupt to be generated. The vector mode must be changed when interrupt input is disabled, that is the KIN15 to KIN0 and WUE15 to WUE0 pins are set at high level.
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Section 5 Interrupt Controller
5.8.5
External Interrupt Pin in Software Standby Mode and Watch Mode
* When the pins (IRQ15 to IRQ0, ExIRQ15 to ExIRQ0, KIN15 to KIN0, and WUE15 to WUE0) are used as external input pins in software standby mode or watch mode, the pins should not be left floating. * When the external interrupt pins (IRQ7, IRQ6, ExIRQ15 to ExIRQ8, KIN7 to KIN0, and WUE15 to WUE8) are used in software standby and watch modes, the noise canceller should be disabled. 5.8.6 Noise Canceller Switching
The noise canceller should be switched when the external input pins (IRQ7, IRQ6, ExIRQ15 to ExIRQ8, KIN7 to KIN0, and WUE15 to WUE8) are high. 5.8.7 IRQ Status Register (ISR)
Since IRQnF may be set to 1 according to the pin state after reset, the ISR should be read after reset, and then write 0 in IRQnF (n = 15 to 0).
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Section 5 Interrupt Controller
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Section 6 Bus Controller (BSC)
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC). The BSC has a bus arbitration function, and controls the operation of the internal bus masters - CPU, data transfer controller (DTC), and LPC interface (LPC). Though this LSI does not have external extended functions, take care not to set inappropriate values in the control registers related to the bus controller when utilizing software with other similar products.
6.1
Features
* Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU, DTC, and LPC.
Internal control signals Bus controller Bus mode signal
Internal data bus
BCR
WSCR
CPU bus request signal DTC bus request signal LPC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal LPC bus acknowledge signal
Figure 6.1 Block Diagram of BSC
BSCS20AA_000020020700
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Section 6 Bus Controller (BSC)
6.2
Register Descriptions
The bus controller has the following registers. * Bus control register (BCR) * Wait state control register (WSCR) 6.2.1
Bit 7 6 5 4 3 2 1 0
Bus Control Register (BCR)
Bit Name -- ICIS0 BRSTRM BRSTS1 BRSTS0 IOS1 IOS0 Initial Value 1 1 0 1 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. Idle Cycle Insertion The initial value should not be changed. Burst ROM Enable The initial value should not be changed. Burst Cycle Select 1 The initial value should not be changed. Burst Cycle Select 0 The initial value should not be changed. Reserved The initial value should not be changed. IOS Select 1, 0 The initial value should not be changed.
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Section 6 Bus Controller (BSC)
6.2.2
Bit 7 6 5 4 3 2 1 0
Wait State Control Register (WSCR)
Bit Name -- -- ABW AST WMS1 WMS0 WC1 WC0 Initial Value 1 1 1 1 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. Bus Width Control The initial value should not be changed. Access State Control The initial value should not be changed. Wait Mode Select 1, 0 The initial value should not be changed. Wait Count 1, 0 The initial value should not be changed.
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Section 6 Bus Controller (BSC)
6.3
Bus Arbitration
The BSC has a bus arbiter that arbitrates bus master operations. There are three bus masters - CPU, DTC, and LPC - which perform read/write operations when they have possession of the bus. 6.3.1 Priority of Bus Masters
Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus masters' bus request signals, and sends a bus request acknowledge signal to the bus master making the request at the designated timing. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The priority order of the bus masters is as follows:
(High) LPC > DTC > CPU (Low)
6.3.2
Bus Transfer Timing
When a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. Each bus master can relinquish the bus at the timings given below. (1) CPU
The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or LPC, the bus arbiter transfers the bus to the DTC or LPC. * DTC and LPC bus transfer timing The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. For details, see section 2.7, Bus States During Instruction Execution, in the H8S/2600 Series, H8S/2000 Series Programming Manual. If the CPU is in sleep mode, the bus is transferred immediately.
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Section 6 Bus Controller (BSC)
(2)
DTC
The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC is a bus master with lower priority than the LPC, and if a bus request is received from the LPC, the bus arbiter transfers the bus to the LPC. * LPC bus transfer timing The bus is transferred at a break between bus cycles. If a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. Similarly, in case of a 32-bit access by the DTC, the bus is not transferred between the component operations for each longword. (3) LPC
The LPC has the highest bus master priority. The LPC sends the bus arbiter a request for the bus when an activation request is generated. The LPC does not release the bus until it completes reading/writing the on-chip memory. For details, see section 18, LPC Interface (LPC).
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Section 6 Bus Controller (BSC)
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Section 7 Data Transfer Controller (DTC)
Section 7 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to addresses H'(FF)EC00 to H'(FF)EFFF in on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.
DTCH80CA_000020020300
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Section 7 Data Transfer Controller (DTC)
7.1
* * * * * * *
Features
Transfer is possible over any number of channels Three transfer modes Normal, repeat, and block transfer modes are available One activation source can trigger a number of data transfers (chain transfer) Direct specification of 16 Mbytes address space is possible Activation by software is possible Transfer can be set in byte or word units A CPU interrupt can be requested for the interrupt that activated the DTC
Internal address bus
Interrupt controller
DTC
On-chip RAM
CPU interrupt request
DTC activation request
[Legend] DTC mode register A, B MRA, MRB: DTC transfer count register A, B CRA, CRB: DTC source address register SAR: DTC destination address register DAR: DTCERA to DTCERE: DTC enable registers A to E DTC vector register DTVECR:
Figure 7.1 Block Diagram of DTC
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MRA MRB CRA CRB DAR SAR
Interrupt request
Internal data bus
Register information
Control logic
DTCERA to DTCERE
DTVECR
Section 7 Data Transfer Controller (DTC)
7.2
Register Descriptions
The DTC has the following registers. * * * * * * DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to on-chip RAM. * * DTC enable register (DTCER) DTC vector register (DTVECR)
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Section 7 Data Transfer Controller (DTC)
7.2.1
DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Bit 7 6 Bit Name SM1 SM0 Initial Value Undefined Undefined R/W -- -- Description Source Address Mode 1, 0 These bits specify an SAR operation after a data transfer. 0*: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0, by -2 when Sz = 1) 5 4 DM1 DM0 Undefined Undefined -- -- Destination Address Mode 1, 0 These bits specify a DAR operation after a data transfer. 0*: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0, by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0, by -2 when Sz = 1) 3 2 MD1 MD0 Undefined Undefined -- -- DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined -- DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area 0 Sz Undefined -- DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer [Legend] *: Don't care
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Section 7 Data Transfer Controller (DTC)
7.2.2
DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit 7 Bit Name Initial Value CHNE Undefined R/W -- Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, see section 7.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of data transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed. 6 DISEL Undefined -- DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time data transfer ends. (DTC does not clear the interrupt source flag which is as an activation source, to 0.) When this bit is cleared to 0, a CPU interrupt request is generated only when the specified number of data transfers ends. (DTC does not clear the interrupt source flag which is as an activation source, to 0.) 5 to 0 -- All undefined -- Reserved These bits have no effect on DTC operation. The write value should always be 0.
7.2.3
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address.
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Section 7 Data Transfer Controller (DTC)
7.2.4
DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 7.2.5 DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts; the upper eight bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 7.2.6 DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
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Section 7 Data Transfer Controller (DTC)
7.2.7
DTC Enable Registers (DTCER)
DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers: DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in tables 7.1 and 7.2. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register.
Bit 7 6 5 4 3 2 1 0 Bit Name DTCEn7 DTCEn6 DTCEn5 DTCEn4 DTCEn3 DTCEn2 DTCEn1 DTCEn0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source as a DTC activation source. [Clearing conditions] * * When data transfer has ended with the DISEL bit in MRB set to 1 When the specified number of transfers have ended
These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not been completed
Note: n: A to E
Table 7.1
Correspondence between Interrupt Sources and DTCER
Register
Bit Bit Name 7 6 5 4 3 2 1 0 DTCEn7 DTCEn6 DTCEn5 DTCEn4 DTCEn3 DTCEn2 DTCEn1 DTCEn0
DTCERA (16)IRQ0 (17)IRQ1 (18)IRQ2 (19)IRQ3 (28)ADI (48)ICIA (49)ICIB (52)OCIA
DTCERB (53)OCIB (39)TGI1A (40)TGI1B (43)TGI2A (44)TGI2B (64)CMIA0 (65)CMIB0 (68)CMIA1
DTCERC (69)CMIB1 (72)CMIAY (73)CMIBY (76)CMIAX (77)CMIBX (85)RXI1
DTCERD (86)TXI1 (89)RXI2 (90)TXI2 (92)IICI0 (94)IICI1
DTCERE (34)TGI0A (35)TGI0B (36)TGI0C (37)TGI0D (108)ERR1 (109)IBFI1 (110)IBFI2 (111)IBFI3
Note: n : A to E ( ) : Vector number
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Section 7 Data Transfer Controller (DTC)
7.2.8
DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt.
Bit 7 Bit Name Initial Value SWDTE 0 R/W R/W Description DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can always be written to this bit. Writing 0 is enabled only after 1 has been read. [Clearing conditions] * * When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written to the DISEL bit after a softwareactivated data transfer end interrupt (SWDTEND) request has been sent to the CPU. When the DISEL bit is set to 1 and data transfer has ended The specified number of transfers have ended On data transfer by software activation
[Holding conditions] * * * 6 5 4 3 2 1 0 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W
DTC Software Activation Vectors 6 to 0 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number x 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. When the SWDTE bit is 0, these bits can be written to.
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Section 7 Data Transfer Controller (DTC)
7.3
Activation Sources
The DTC is activated by an interrupt request or by a write to DTVECR by software. The interrupt request source to activate the DTC is selected by DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the interrupt flag that became the activation source or the corresponding DTCER bit is cleared. The activation source flag, in the case of RXI1, for example, is the RDRF flag in SCI_1. When an interrupt has been designated as a DTC activation source, the existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Figure 7.2 shows a block diagram of DTC activation source control. For details on the interrupt controller, see section 5, Interrupt Controller.
Source flag cleared Clear controller Clear DTCER Select Clear request
IRQ interrupt
Interrupt request
Selection circuit
On-chip peripheral module
DTC
DTVECR
Interrupt controller Interrupt mask
CPU
Figure 7.2 Block Diagram of DTC Activation Source Control
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Section 7 Data Transfer Controller (DTC)
7.4
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'(FF)EC00 to H'(FF)EFFF). Register information should be located at an address that is a multiple of four within the range. The method for locating the register information in address space is shown in figure 7.3. Locate MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 7.3, and the register information start address should be located at the vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the start address of the register information from the vector table set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] x 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is a 2-byte unit. Specify the lower two bytes of the register information start address.
Lower address B'00 Register information start address MRA MRB Chain transfer CRA MRA MRB CRA SAR DAR CRB Register information for 2nd transfer in chain transfer B'01 B'10 SAR DAR CRB Register information B'11
4 bytes
Figure 7.3 DTC Register Information Location in Address Space
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Section 7 Data Transfer Controller (DTC)
Table 7.2
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Activation Source Write to DTVECR IRQ0 IRQ1 IRQ2 IRQ3 ADI TGIA TGIB TGIC TGID TGIA TGIB TGIA TGIB ICIA ICIB OCIA OCIB CMIA0 CMIB0 CMIA1 CMIB1 CMIAY CMIBY CMIAX CMIBX RXI1 TXI1 RXI2 TXI2 IICI0 IICI1 Vector Number DTVECR 16 17 18 19 28 34 35 36 37 39 40 43 44 48 49 52 53 64 65 68 69 72 73 76 77 85 86 89 90 92 94 DTC Vector Address H'0400 + (vector number x 2) H'0420 H'0422 H'0424 H'0426 H'0438 H'0444 H'0446 H'0448 H'044A H'044E H'0450 H'0456 H'0458 H'0460 H'0462 H'0468 H'046A H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0498 H'049A H'04AA H'04AC H'04B2 H'04B4 H'04B8 H'04BC DTCE* -- DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC0 DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 Priority High
Activation Source Origin Software External pins
A/D converter TPU_0
TPU_1 TPU_2 FRT
TMR_0 TMR_1 TMR_Y TMR_X SCI_1 SCI_2 IIC_0 IIC_1
Low
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Section 7 Data Transfer Controller (DTC)
Activation Source Origin LPC
Activation Source ERRI IBFI1
Vector Number 108 109
DTC Vector Address H'04D8 H'04DA
DTCE* DTCEE3 DTCEE2
Priority High
Note:
*
IBFI2 110 H'04DC DTCEE1 IBFI3 111 H'04DE DTCEE0 Low DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0.
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Section 7 Data Transfer Controller (DTC)
7.5
Operation
The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, or block transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information.
Start
Read DTC vector Next transfer
Read register information
Data transfer
Write register information
CHNE = 1 No
Yes
Transfer counter = 0 or DISEL = 1
No
Yes
Clear an activation flag
Clear DTCER
End
Interrupt exception handling
Figure 7.4 DTC Operation Flowchart
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Section 7 Data Transfer Controller (DTC)
7.5.1
Normal Mode
In normal mode, one activation source transfers one byte or one word of data. Table 7.3 lists the register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has been completed, a CPU interrupt can be requested. Table 7.3
Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B
Register Functions in Normal Mode
Abbreviation SAR DAR CRA CRB Function Transfer source address Transfer destination address Transfer counter Not used
SAR Transfer
DAR
Figure 7.5 Memory Mapping in Normal Mode
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Section 7 Data Transfer Controller (DTC)
7.5.2
Repeat Mode
In repeat mode, one activation source transfers one byte or one word of data. Table 7.4 lists the register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has been completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated. In repeat mode, the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when the DISEL bit in MRB is cleared to 0. Table 7.4
Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B
Register Functions in Repeat Mode
Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds number of transfers Transfer Count Not used
SAR or DAR
Repeat area
Transfer
DAR or SAR
Figure 7.6 Memory Mapping in Repeat Mode
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Section 7 Data Transfer Controller (DTC)
7.5.3
Block Transfer Mode
In block transfer mode, one activation source transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 7.5 lists the register functions in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register that is specified as the block area is restored. The other address register is then incremented, decremented, or left fixed according to the register information. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has been completed, a CPU interrupt is requested. Table 7.5
Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B
Register Functions in Block Transfer Mode
Abbreviation SAR DAR CRAH CRAL CRB Function Transfer source address Transfer destination address Holds block size Block size counter Transfer counter
1st block
SAR or DAR
* * *
Block area Transfer
DAR or SAR
N th block
Figure 7.7 Memory Mapping in Block Transfer Mode
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Section 7 Data Transfer Controller (DTC)
7.5.4
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the register information start address stored at the DTC vector address, and then reads the first register information at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. In the case of transfer with the CHNE bit set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected.
Source
DTC vector address
Register information start address
Register information CHNE = 1 Register information CHNE = 0
Destination
Source
Destination
Figure 7.8 Chain Transfer Operation
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Section 7 Data Transfer Controller (DTC)
7.5.5
Interrupt Sources
An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control by the interrupt controller. In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 7.5.6
Operation Timing
DTC activation request DTC request
Data transfer
Vector read Address
Read Write
Transfer information read
Transfer information write
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
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Section 7 Data Transfer Controller (DTC)
DTC activation request DTC request
Data transfer
Read Write Read Write
Vector read Address
Transfer information read
Transfer information write
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)
DTC activation request DTC request Data transfer Vector read Address
Read Write Read Write
Data transfer
Transfer information read
Transfer information write
Transfer information read
Transfer information write
Figure 7.11 DTC Operation Timing (Example of Chain Transfer)
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Section 7 Data Transfer Controller (DTC)
7.5.7
Number of DTC Execution States
Table 7.6 lists the execution status for a single DTC data transfer, and table 7.7 shows the number of states required for each execution status. Table 7.6 DTC Execution Status
Register Information Vector Read Read/Write I J 1 1 1 6 6 6 Internal Operations M 3 3 3
Mode Normal Repeat Block transfer
Data Read K 1 1 N
Data Write L 1 1 N
[Legend] N: Block size (initial setting of CRAH and CRAL)
Table 7.7
Number of States Required for Each Execution Status
On-Chip RAM (H'(FF)EC00 to H'(FF)EFFF) 32 1 -- 1 On-Chip RAM (On-chip RAM area other than H'(FF)EC00 to H'(FF)EFFF) 16 1 -- -- OnChip ROM 16 1 1 --
Object to be Accessed Bus width Access states Execution Vector read SI status Register information read/write SJ Byte data read SK Word data read SK Byte data write SL Word data write SL Internal operation SM
On-Chip I/O Registers 8 2 -- -- 16 2 -- --
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
2 4 2 4 1
2 2 2 2 1
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Section 7 Data Transfer Controller (DTC)
The number of execution states is calculated from using the formula below. Note that is the sum of all transfers activated by one activation source (the number in which the CHNE bit is set to 1, plus 1).
Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for the DTC operation is 13 states. The time from activation to the end of data write is 10 states.
7.6
7.6.1
Procedures for Using DTC
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. [5] After one data transfer has been completed, or after the specified number of data transfers have been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. 7.6.2 Activation by Software
The procedure for using the DTC with software activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Check that the SWDTE bit is 0. [4] Write 1 to the SWDTE bit and the vector number to DTVECR. [5] Check the vector number written to DTVECR. [6] After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1 or after the specified number of data transfers have been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested.
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Section 7 Data Transfer Controller (DTC)
7.7
7.7.1
Examples of Use of the DTC
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI, RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. [2] Set the start address of the register information at the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. [5] Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. [6] When CRA becomes 0 after 128 data transfers have been completed, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine will perform wrap-up processing.
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Section 7 Data Transfer Controller (DTC)
7.7.2
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the transfer destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the transfer destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. [2] Set the start address of the register information at the DTC vector address (H'04C0). [3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. [4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. [5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. [6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. [7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform wrap-up processing.
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Section 7 Data Transfer Controller (DTC)
7.8
7.8.1
Usage Notes
Module Stop Mode Setting
DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the initial state, DTC operation is enabled. Access to DTC registers is disabled when module stop mode is set. Note that when the DTC is being activated, module stop mode can not be specified. For details, see section 24, Power-Down Modes. 7.8.2 On-Chip RAM
MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR should not be cleared to 0. 7.8.3 DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all interrupts and writing data after executing a dummy read on the relevant register. 7.8.4 Setting Required on Entering Subactive Mode or Watch Mode
Set the MSTP14 bit in MSTPCRH to 1 to make the DTC enter module stop mode, then confirm that is set to 1 before making a transition to subactive mode or watch mode. 7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter
Interrupt sources of the SCI, IIC, LPC, or A/D converter which activate the DTC are cleared when DTC reads from or writes to the respective registers, and they cannot be cleared by the DISEL bit in MRB.
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Section 8 I/O Ports
Section 8 I/O Ports
Table 8.1 is a summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output and data registers (DR and ODR) that store output data. DDR, DR, and ODR are not provided for an input-only port. Ports 1 to 3, 6, and B to F have built-in input pull-up MOSs. Port 1 to 3, C, and D can drive LEDs (with 5-mA current sink). P52, P97, P86, P42, and ports A and G are NMOS push-pull output. Table 8.1
Port Port 1
Port Functions
Mode 2, Mode 3 P17 P16 P15 P14 P13 P12 P11 P10 I/O Status Built-in input pull-up MOSs LED drive capability (sink current 5 mA)
Description General I/O port
Port 2
General I/O port also functioning as PWM output
P27/PW15 P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8
Built-in input pull-up MOSs LED drive capability (sink current 5 mA)
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Section 8 I/O Ports
Port Port 3
Description General I/O port also functioning as LPC input/output
Mode 2, Mode 3 P37/SERIRQ P36/LCLK P35/LRESET P34/LFRAME P33/LAD3 P32/LAD2 P31/LAD1 P30/LAD0
I/O Status Built-in input pull-up MOSs LED drive capability (sink current 5 mA)
Port 4
General I/O port also functioning as interrupt input, PWMX output, TMR_0, and TMR_1, SCI_2, IIC_1, and LPC inputs/outputs
P47/PWX1 P46/PWX0 P45/TMRI1 P44/TMO1 P43/TMCI1 P42/ExIRQ7/TMRI0/SCK2/ SDA1 P41/TMO0/RxD2/DCLKRUN P40/TMCI0/TxD2/DSERIRQ
Port 5
General I/O port also P52/ExIRQ6/SCL0 functioning as interrupt P51/TMOY input, IIC_0 input/output, P50/ExEXCL TMR_Y output, and external sub-clock input General I/O port also functioning as interrupt input, TMR_Y, keyboard input, FRT, and TMR_X inputs/outputs P67/IRQ7/KIN7/TMOX P66/IRQ6/KIN6/FTOB P65/KIN5/FTID P64/KIN4/FTIC P63/KIN3/FTIB P62/KIN2/FTIA/TMIY P61/KIN1/FTOA P60/KIN0/FTCI/TMIX Built-in input pull-up MOSs and noise canceller
Port 6
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Section 8 I/O Ports
Port Port 7
Description General input port also functioning as interrupt input and A/D converter analog input
Mode 2, Mode 3 P77/AN7 P76/AN6 P75/ExIRQ5/AN5 P74/ExIRQ4/AN4 P73/ExIRQ3/AN3 P72/ExIRQ2/AN2 P71/ExIRQ1/AN1 P70/ExIRQ0/AN0
I/O Status
Port 8
General I/O port also functioning as interrupt input, SCI_1, IrDA interface, IIC_1, and LPC inputs/outputs
P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1/IrRxD P84/IRQ3/TxD1/IrTxD P83/LPCPD P82/CLKRUN P81/GA20 P80/PME
Port 9
General I/O port also functioning as A/D converter external trigger, external sub-clock, interrupt input, system clock output, and IIC_0 input/output
P97/IRQ15/SDA0 P96//EXCL P95/IRQ14 P94/IRQ13 P93/IRQ12 P92/IRQ0 P91/IRQ1 P90/IRQ2/ADTRG
Built-in input pull-up MOSs (P95 to P90)
Port A
General I/O port also functioning as keyboard input and KBU input/output
PA7/KIN15/PS2CD PA6/KIN14/PS2CC PA5/KIN13/PS2BD PA4/KIN12/PS2BC PA3/KIN11/PS2AD PA2/KIN10/PS2AC PA1/KIN9 PA0/KIN8
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Section 8 I/O Ports
Port Port B
Description General I/O port also functioning as wake-up event input and LPC input/output
Mode 2, Mode 3 PB7/WUE7/DLAD0 PB6/WUE6/DLAD1 PB5/WUE5/DLAD2 PB4/WUE4/DLAD3 PB3/WUE3/DLFRAME PB2/WUE2 PB1/WUE1/LSCI PB0/WUE0/LSMI
I/O Status Built-in input pull-up MOSs
Port C
General I/O port also PC7/WUE15/DLDRQ functioning wake-up event PC6/WUE14/LDRQ input and LPC input/output PC5/WUE13 PC4/WUE12 PC3/WUE11 PC2/WUE10 PC1/WUE9 PC0/WUE8
Built-in input pull-up MOSs and noise canceller LED drive capability (sink current 5 mA)
Port D
General I/O port also functioning as TPU input/output
PD7/TIOCB2/TCLKD PD6/TIOCA2 PD5/TIOCB1/TCLKC PD4/TIOCA1 PD3/TIOCD0/TCLKB PD2/TIOCC0/TCLKA PD1/TIOCB0 PD0/TIOCA0
Built-in input pull-up MOSs LED drive capability (sink current 5 mA)
Port E
General input port also functioning as LPC input and emulator input
PE4*/ETMS PE3*/ETDO PE2*/ETDI PE1*/ETCK PE0/LID3
Built-in input pull-up MOSs
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Section 8 I/O Ports
Port Port F
Description General I/O port also functioning as interrupt input, and PWM and TMR_X outputs
Mode 2, Mode 3 PF7/ExPW15 PF6/ExPW14 PF5/ExPW13 PF4/ExPW12 PF3/IRQ11/ExTMOX PF2/IRQ10 PF1/IRQ9 PF0/IRQ8
I/O Status Built-in input pull-up MOSs
Port G General I/O port also PG7/ExIRQ15/ExSCLB interrupt input, TMR_0, PG6/ExIRQ14/ExSDAB TMR_1, TMR_X, and TMR_Y inputs, and IIC_0 and IIC_1 inputs/outputs PG5/ExIRQ13/ExSCLA PG4/ExIRQ12/ExSDAA PG3/ExIRQ11/ExTMIY PG2/ExIRQ10/ExTMIX PG1/ExIRQ9/ExTMCI1 PG0/ExIRQ8/ExTMCI0 Note: *
Built-in noise canceller
Not supported in the system development tool (emulator).
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Section 8 I/O Ports
8.1
Port 1
Port 1 is an 8-bit I/O port. Port 1 has a built-in input pull-up MOS that can be controlled by software. Port 1 has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 pull-up MOS control register (P1PCR) 8.1.1 Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 1 pins are output ports when P1DDR bits are set to 1, and input ports when cleared to 0.
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Section 8 I/O Ports
8.1.2
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P1DR stores output data for the port 1 pins that are used as the general output port. If a port 1 read is performed while the P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while the P1DDR bits are cleared to 0, the pin states are read.
8.1.3
Port 1 Pull-Up MOS Control Register (P1PCR)
P1PCR controls the on/off state of the input pull-up MOS for port 1 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in input state, the corresponding input pull-up MOS is turned on when a P1PCR bit is set to 1.
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Section 8 I/O Ports
8.1.4
Pin Functions
* P17, P16, P15, P14, P13, P12, P11, P10 The function of port 1 pins is switched as shown below according to the P1nDDR bit.
P1nDDR Pin function Note: n = 7 to 0 0 P1n input pin 1 P1n output pin
8.1.5
Port 1 Input Pull-Up MOS
Port 1 has a built-in input pull-up MOS that can be controlled by software. Table 8.2 summarizes the input pull-up MOS states. Table 8.2
Reset Off
Port 1 Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off On when P1DDR = 0 and P1PCR = 1; otherwise off.
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Section 8 I/O Ports
8.2
Port 2
Port 2 is an 8-bit I/O port. Port 2 pins also functions as PWM output pins. Port 2 has a built-in input pull-up MOS that can be controlled by software. Port 2 has the following registers. * Port 2 data direction register (P2DDR) * Port 2 data register (P2DR) * Port 2 pull-up MOS control register (P2PCR) 8.2.1 Port 2 Data Direction Register (P2DDR)
The individual bits of P2DDR specify input or output for the pins of port 2.
Bit 7 6 5 4 3 2 1 0 Bit Name P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 2 pins are output ports or PWM outputs when the P2DDR bits are set to 1, and input ports when cleared to 0.
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Section 8 I/O Ports
8.2.2
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P2DR stores output data for the port 2 pins that are used as the general output port. If a port 2 read is performed while the P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while the P2DDR bits are cleared to 0, the pin states are read.
8.2.3
Port 2 Pull-Up MOS Control Register (P2PCR)
P2PCR controls the on/off state of the input pull-up MOS for port 2 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in input state, the corresponding input pull-up MOS is turned on when a P2PCR bit is set to 1.
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Section 8 I/O Ports
8.2.4
Pin Functions
* P27/PW15, P26/PW14 The function of port 2 pins is switched as shown below according to the combination of the PWMAS bit in PTCNT0, the OEm bit in PWOERB of PWM, and the P2nDDR bit.
PWMAS P2nDDR OEm Pin function Note: n = 7 to 6 m = 15 to 14 0 0 0 1 1 P2n input pin 0 P2n output pin 1 1
P2n input pin P2n output pin PWm output pin
* P25/PW13, P24/PW12 The function of port 2 pins is switched as shown below according to the combination of the PWMBS bit in PTCNT0, the OEm bit in PWOERB of PWM, and the P2nDDR bit.
PWMBS P2nDDR OEm Pin function Note: n = 5 to 4 m = 13 to 12 0 0 0 1 1 P2n input pin 0 P2n output pin 1 1
P2n input pin P2n output pin PWm output pin
* P23/PW11, P22/PW10, P21/PW9, P20/PW8 The function of port 2 pins is switched as shown below according to the combination of the OEm bit in PWOERA of PWM and the P2nDDR bit.
P2nDDR OEm Pin function Note: n = 3 to 0 m = 11 to 8 0 P2n input pin 0 P2n output pin 1 1 PWm output pin
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Section 8 I/O Ports
8.2.5
Port 2 Input Pull-Up MOS
Port 2 has a built-in input pull-up MOS that can be controlled by software. Table 8.3 summarizes the input pull-up MOS states. Table 8.3
Reset Off
Port 2 Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off.
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Section 8 I/O Ports
8.3
Port 3
Port 3 is an 8-bit I/O port. Port 3 pins also function as LPC input/output pins. Port 3 has a built-in input pull-up MOS that can be controlled by software. Port 3 has the following registers. * Port 3 data direction register (P3DDR) * Port 3 data register (P3DR) * Port 3 pull-up MOS control register (P3PCR) 8.3.1 Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the pins of port 3.
Bit 7 6 5 4 3 2 1 0 Bit Name P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 3 pins are output ports when P3DDR bits are set to 1, and input ports when cleared to 0.
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Section 8 I/O Ports
8.3.2
Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P3DR stores output data for the port 3 pins that are used as the general output port. If a port 3 read is performed while the P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while the P3DDR bits are cleared to 0, the pin states are read.
8.3.3
Port 3 Pull-Up MOS Control Register (P3PCR)
P3PCR controls the on/off state of the input pull-up MOS for port 3 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in input state, the corresponding input pull-up MOS is turned on when a P3PCR bit is set to 1.
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8.3.4
Pin Functions
* P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 The function of port 3 pins is switched as shown below according to the combination of the LPC4E bit in HICR4 of LPC, LPC3E to LPC1E bits in HICR0, LMCE bit in LMCCR1, and the P3nDDR bit. LPCENABLE in the following table is expressed by the following logical expressions. LPCENABLE = 1 : LPC4E + LPC3E + LPC2E + LPC1E + LMCE
LPCENABLE P3nDDR Pin function Note: n = 7 to 0 0 P3n input pins 0 1 P3n output pins 1 LPC input/output pin
8.3.5
Port 3 Input Pull-Up MOS
Port 3 has a built-in input pull-up MOS that can be controlled by software. Table 8.4 summarizes the input pull-up MOS states. Table 8.4
Reset Off
Port 3 Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when P3DDR = 0 and P3PCR = 1; otherwise off.
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Section 8 I/O Ports
8.4
Port 4
Port 4 is an 8-bit I/O port. Port 4 pins also function as interrupt input, PWMX output, TMR_0, TMR_1, SCI_2, IIC_1, and LPC input/output pins. The output format for P42 and SCK2 is NMOS push-pull output. The output format for SDA1 is NMOS open-drain output. Port 4 has the following registers. * Port 4 data direction register (P4DDR) * Port 4 data register (P4DR) 8.4.1 Port 4 Data Direction Register (P4DDR)
The individual bits of P4DDR specify input or output for the pins of port 4.
Bit 7 6 5 4 3 2 1 0 Bit Name P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description If port 4 pins are specified for use as the general I/O port, the corresponding port 4 pins are output ports when the P4DDR bits are set to 1, and input ports when cleared to 0.
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Section 8 I/O Ports
8.4.2
Port 4 Data Register (P4DR)
P4DR stores output data for the port 4 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P4DR stores output data for the port 4 pins that are used as the general output port. If a port 4 read is performed while the P4DDR bits are set to 1, the P4DR values are read. If a port 4 read is performed while the P4DDR bits are cleared to 0, the pin states are read.
8.4.3
Pin Functions
* P47/PWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR of PWMX, and P47DDR bit.
OEB P47DDR Pin function 0 P47 input pin 0 1 P47 output pin 1 PWX1 output pin
* P46/PWMX0 The pin function is switched as shown below according to the combination of the OEA bit in DACR of PWMX, and the P46DDR bit.
OEA P46DDR Pin function 0 P46 input pin 0 1 P46 output pin 1 PWX0 output pin
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* P45/TMRI1 The pin function is switched as shown below according to the P45DDR bit. When the CCLR1 and CCLR0 bits in TCR of TMR_1 are set to 1, this pin is used as the TMRI1 input pin.
P45DDR Pin function 0 P45 input pin TMRI1 input pin 1 P45 output pin
* P44/TMO1 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCR of TMR_1 and the P44DDR bit.
OS3 to OS0 P44DDR Pin function 0 P44 input pin All 0 1 P44 output pin One bit is set as 1 TMO1 output pin
* P43/TMCI1 The pin function is switched as shown below according to the P43DDR bit. When the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_1, this pin can be used as the TMCII input pin.
P43DDR Pin function 0 P43 input pin TMCI1 input pin 1 P43 output pin
* P42/ExIRQ7/TMRI0/SCK2/SDA1 The pin function is switched as shown below according to the combination of the SDA1AS and SDA1BS bits in PTCNT1, ICE bit in ICCR of IIC_1, CKE1 and CKE0 bits in SCR of SCI_2, C/A bit in SMR, and the P42DDR bit. When the CCLR1 and CCLR0 bits in TCR of TMR_0 are set to 1, this pin is used as the TMRI0 input pin. When the ISS7 bit in ISSR and the IRQ7E bit in IER of the interrupt controller are set to 1, this pin can be used as the ExIRQ7 interrupt input pin. IICENABLE in the following table is expressed by the following logical expressions. IICENABLE = 1 : ICE * SDA1AS * SDA1BS
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IICENABLE CKE1 C/A CKE0 P42DDR Pin function 0 P42 input pin 0 1 P42 output pin 0 1 0
0 1 1 SCK2 output pin SCK2 input pin
1 0 0 0 SDA1 input/output pin
SCK2 output pin
ExIRQ7 input pin/TMRI0 input pin
Note: To use this pin as the SDA1 input/output pin, clear the SDA1AS and SDA1BS bits in PTCNT1, CKE1 and CKE0 bits in SCR of SCI_2, and C/A bit in SMR to 0. The output format for SDA1 is NMOS output only, and direct bus drive is possible. When this pin is used as the P42 output pin or SCK2 output pin, the output format is NMOS push-pull output.
* P41/TMO0/RxD2/DCLKRUN The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_0, RE bit in SCR of SCI_2, LPCS bit in PTCNT2 and the P41DDR bits.
LPCS OS3 to OS0 RE P41DDR Pin function 0 P41 input pin 0 1 P41 output pin All 0 1 RxD2 input pin 0 One bit is set as 1 0 TMO0 output pin 1 DCLKRUN input/output pin
Note: To use this pin as the TMO0 output pin, clear the RE bit in SCR of SCI_2 to 0.
* P40/TMCI0/TxD2/DSERIRQ The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_2, LPCS bit in PTCNT2, and the P40DDR bits. When the TMI0S bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_0, this bit is used as the TMCI0 input pin.
LPCS TE P40DDR Pin function 0 P40 input pin 0 1 P40 output pin 0 1 TxD2 output pin TMCI0 input pin 1 DSERIRQ input/output pin
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Section 8 I/O Ports
8.5
Port 5
Port 5 is a 3-bit I/O port. Port 5 pins also function as interrupt input pins, IIC_0 input/output pin, TMR_Y output pin, and the external sub-clock input pin. The output format for P52 is NMOS push-pull output. Port 5 has the following registers. * Port 5 data direction register (P5DDR) * Port 5 data register (P5DR) 8.5.1 Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the pins of port 5.
Bit Bit Name Initial Value Undefined 0 0 0 R/W W W W Description Reserved These bits cannot be modified. 2 1 0 P52DDR P51DDR P50DDR If port 5 pins are specified for use as the general I/O port, the corresponding port 5 pins are output ports when the P5DDR bits are set to 1, and input ports when cleared to 0.
7 to 3
8.5.2
Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 2 1 0 P52DR P51DR P50DR 0 0 0 R/W R/W R/W P5DR stores output data for the port 5 pins that are used as the general output port. If a port 5 read is performed while the P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while the P5DDR bits are cleared to 0, the pin states are read.
7 to 3
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8.5.3
Pin Functions
* P52/ExIRQ6/SCL0 The pin function is switched as shown below according to the combination of the SCL0AS and SCL0BS bits in PTCNT1, ICE bit in ICCR of IIC_1, and the P52DDR bit. When the IRQ6E bit in IER of the interrupt controller is set to 1, this pin can be used as the ExIRQ6 interrupt input pin. IICENABLE in the following table is expressed by the following logical expressions. IICENABLE = 1 : ICE * SCLOAS * SCLOBS
IICENABLE P52DDR Pin function 0 P52 input pin 0 1 P52 output pin ExIRQ6 input pin 1 SCL0 input/output pin
Note: To use this pin as the SCL0 input/output pin, clear the SCL0AS and SCL0BS bits in PTCNT1 to 0. The output format for SCL0 is NMOS output only, and direct bus drive is possible. When this pin is used as the P52 output pin, the output format is NMOS push-pull output.
* P51/TMOY The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_Y and the P51DDR bit.
OS3 to OS0 P51DDR Pin function 0 P51 input pin
All 0 One bit is set as 1
1 P51 output pin
TMOY output pin
* P50/ExEXCL The pin function is switched as shown below according to the combination of the EXCLS bit in PTCNT0, EXCLE bit in LPWRCR, and the P50DDR bit. To use this pin as the ExEXCL input pin, clear the P50DDR bit to 0.
EXCLS P50DDR EXCLE Pin function 0 0 1 0 0 1 ExEXCL input pin 1 1 0 P50 output pin
P50 input pin P50 output pin P50 input pin
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8.6
Port 6
Port 6 is an 8-bit I/O port. Port 6 pins also function as the interrupt input pin, TMR_Y, keyboard and noise cancel input pins, FRT, and TMR_X input/output pin. Port 6 can change the input level for four levels. Port 6 has the following registers. * * * * * * * Port 6 data direction register (P6DDR) Port 6 data register (P6DR) Pull-up MOS control register (KMPCR) System control register 2 (SYSCR2) Noise canceller enable register (P6NCE) Noise canceller decision control register (P6NCMC) Noise cancel cycle setting register (P6NCCS) Port 6 Data Direction Register (P6DDR)
8.6.1
The individual bits of P6DDR specify input or output for the pins of port 6.
Bit 7 6 5 4 3 2 1 0 Bit Name P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port 6 pins are output ports when P6DDR bits are set to 1, and input ports when cleared to 0.
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8.6.2
Port 6 Data Register (P6DR)
P6DR stores output data for the port 6 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P6DR stores output data for the port 6 pins that are used as the general output port. If a port 6 read is performed while the P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while the P6DDR bits are cleared to 0, the pin states are read.
8.6.3
Pull-Up MOS Control Register (KMPCR)
KMPCR controls the on/off state of the input pull-up MOS for port 6 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pins are in input state, the corresponding input pull-up MOS is turned on when a KMPCR bit is set to 1.
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8.6.4
Noise Canceller Enable Register (P6NCE)
P6NCE enables or disables the noise cancel circuit at port 6.
Bit 7 6 5 4 3 2 1 0 Bit Name P67NCE P66NCE P65NCE P64NCE P63NCE P62NCE P61NCE P60NCE Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Noise cancel circuit is enabled when P6NCE bit is set to 1, and the pin state is fetched in the P6DR in the sampling cycle set by the P6NCCS.
8.6.5
Noise Canceller Mode Control Register (P6NCMC)
P6NCMC controls whether 1 or 0 is expected for the input signal to port 6 in bit units.
Bit 7 6 5 4 3 2 1 0 Bit Name P67NCMC P66NCMC P65NCMC P64NCMC P63NCMC P62NCMC P61NCMC P60NCMC Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 1 expected: 1 is stored in the port data register when 1 is input stably 0 expected: 0 is stored in the port data register when 0 is input stably
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8.6.6
Noise Cancel Cycle Setting Register (P6NCCS)
P6NCCS controls the sampling cycles of the noise canceller.
Bit Bit Name Initial Value Undefined R/W R/W Description Reserved The read data is undefined. The write value should always be 0. 2 1 0 P6NCCK2 P6NCCK1 P6NCCK0 0 0 0 R/W R/W R/W These bits set the sampling cycles of the noise canceller. When is 10 MHz 000: 001: 010: 011: 100: 101: 110: 111: 0.80 s 12.8 s 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 104.9 ms /2 /32 /8192 /16384 /32768 /65536 /131072 /262144
7 to 3
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/2, /32, /8192, /16384, /32768, /65536, /131072, /262144 Sampling clock selection t
Pin input
Latch
Latch
Latch
Latch
Matching detection circuit
Port data register Interrupt input Key board input
t
Sampling clock
Figure 8.1 Noise Cancel Circuit
P6n Input
1 expected P6n Input
0 expected P6n Input
(n = 7 to 0)
Figure 8.2 Noise Cancel Operation
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Section 8 I/O Ports
8.6.7
System Control Register 2 (SYSCR2)
SYSCR2 controls the port 6 input level selection and the current specifications for the port 6 input pull-up MOSs.
Bit 7 6 Bit Name KWUL1 KWUL0 Initial Value 0 0 R/W R/W R/W Description Key Wakeup Level 1, 0 Select the port 6 input level. 00: Standard input level is selected 01: Input level 1 is selected 10: Input level 2 is selected 11: Input level 3 is selected 5 P6PUE 0 R/W Port 6 Input Pull-Up Extra Selects the current specification for the input pullup MOS. 0: Standard current specification is selected 1: Current-limit specification is selected 4 to 0 All 0 R/W Reserved The initial value should not be changed.
8.6.8
Pin Functions
* P67/IRQ7/KIN7/TMOX The function of port 6 pins is switched as shown below according to the combination of the TMOXS bit in PTCNT0, OS3 to OS0 bits in TCSR of TMR_X, and the P67DDR bit. When the KMIMR7 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN7 input pin. When the ISS7 bit in ISSR is cleared to 0 and the IRQ7E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ7 interrupt input pin.
TMOXS OS3 to OS0 P67DDR Pin function 0 P67 input pin All 0 1 P67 output pin 0 One bit is set as 1 TMOX output pin IRQ7 input pin/KIN7 input pin 0 P67 input pin 1 1 P67 output pin
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* P66/IRQ6/KIN6/FTOB The function of port 6 pins is switched as shown below according to the combination of the OEB bit in TOCR of FRT and the P66DDR bit. When the KMIMR6 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN6 input pin. When the EIVS bit in SYSCR is cleared to 0 and the IRQ6E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ6 interrupt input pin.
OEB P66DDR Pin function 0 P66 input pin 0 1 P66 output pin IRQ6 input pin/KIN6 input pin 1 FTOB output pin
* P65/KIN5/FTID The function of port 6 pins is switched as shown below according to the P65DDR bit. When the ICIDE bit in TIER of FRT is set to 1, this pin can be used as the FTID input pin. When the KMIMR5 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN5 input pin.
P65DDR Pin function 0 P65 input pin KIN5 input pin/FTID input pin 1 P65 output pin
* P64/KIN4/FTIC The function of port 6 pins is switched as shown below according to the P64DDR bit. When the ICICE bit in TIER of FRT is set to 1, this pin can be used as the FTIC input pin. When the KMIMR4 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN4 input pin.
P64DDR Pin function 0 P64 input pin KIN4 input pin/FTIC input pin 1 P64 output pin
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* P63/KIN3/FTIB The function of port 6 pins is switched as shown below according to the P63DDR bit. When the ICIBE bit in TIER of FRT is set to 1, this pin can be used as the FTIB input pin. When the KMIMR3 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN3 input pin.
P63DDR Pin function 0 P63 input pin KIN3 input pin/FTIB input pin 1 P63 output pin
* P62/KIN2/FTIA/TMIY The function of port 6 pins is switched as shown below according to the P62DDR bit. When the ICIAE bit in TIER of FRT is set to 1, this pin can be used as the FTIA input pin. When the TMIYS bit in PTCNT0 is cleared to 0 and the CCLR1 and CCLR0 bits in TCR of TMR_Y are both set to 1, this pin is used as the TMIY (TMRIY) input pin. When the KMIMR2 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN2 input pin.
P62DDR Pin function 0 P62 input pin 1 P62 output pin
KIN2 input pin/FTIA input pin/TMIY input pin
* P61/KIN1/FTOA The function of port 6 pins is switched as shown below according to the combination of the OEA bit in TOCR of FRT and the P61DDR bit. When the KMIMR1 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN1 input pin.
OEA P61DDR Pin function 0 P61 input pin 0 1 P61 output pin KIN1 input pin 1 FTOA output pin
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* P60/KIN0/FTCI/TMIX The function of port 6 pins is switched as shown below according to the P60DDR bit. When the CKS1 and CKS0 bits in TCR of FRT are both set to 1, this pin can be used as the FTCI input pin. When the TMIXS bit in PTCNT0 is cleared to 0 and the CCLR1 and CCLR0 bits in TCR of TMR_X are both set to 1, this pin is used as the TMIX(TMRIX) input pin. When the KMIMR0 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN0 input pin.
P60DDR Pin function 0 P60 input pin 1 P60 output pin
KIN0 input pin/FTCI input pin/TMIX input pin
8.6.9
Port 6 Input Pull-Up MOS
Port 6 has a built-in input pull-up MOS that can be controlled by software. Port 6 can selects the current specification for the input pull-up MOSs by the P6PUE bit. When the pin functions as an output pin of the built-in peripheral function, the input pull-up MOS is always off. Table 8.5 summarizes the input pull-up MOS states. Table 8.5
Reset Off
Port 6 Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when input state and KMPCR = 1; otherwise off.
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Section 8 I/O Ports
8.7
Port 7
Port 7 is an 8-bit input port. Port 7 pins also function as the interrupt input pins and A/D converter analog input pins. Port 7 has the following register. * Port 7 input data register (P7PIN) 8.7.1 Port 7 Input Data Register (P7PIN)
P7PIN indicates the pin states.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When a P7PIN read is performed, the pin states are always read.
The initial value is determined in accordance with the pin states of P77 to P70.
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Section 8 I/O Ports
8.7.2
Pin Functions
* P77/AN7, P76/AN6
Pin function Note: n = 7, 6 P7n input pin/ANn input pin
* P75/ExIRQ5/AN5, P74/ExIRQ4/AN4, P73/ExIRQ3/AN3, P72/ExIRQ2/AN2, P71/ExIRQ1/AN1, P70/ExIRQ0/AN0 When the ISS0n bit in ISSR and the IRQnE bit in IER of the interrupt controller are set to 1, this pin can be used as the ExIRQn interrupt input pin.
Pin function P7n input pin/ExIRQn input pin/ANn input pin
Note: n = 5 to 0 When the interrupt input pin is set, do not use as the AN input pin.
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Section 8 I/O Ports
8.8
Port 8
Port 8 is a 7-bit I/O port. Port 8 pins also function as the interrupt input pins, SCI_1 and IIC_1 input/output pins, and LPC input/output pin. The output format for P86 and SCK1 is NMOS pushpull output. The output format for SCL1 is NMOS open-drain output. * Port 8 data direction register (P8DDR) * Port 8 data register (P8DR) 8.8.1 Port 8 Data Direction Register (P8DDR)
The individual bits of P8DDR specify input or output for the pins of port 8.
Bit 7 6 5 4 3 2 1 0 Bit Name P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial Value Undefined 0 0 0 0 0 0 0 R/W W W W W W W W Description Reserved This bit cannot be modified. If port 8 pins are specified for use as the general I/O port, the corresponding port 8 pins are output ports when the P8DDR bits are set to 1, and input ports when cleared to 0.
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Section 8 I/O Ports
8.8.2
Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P86DR P85DR P84DR P83DR P82DR P81DR P80DR Initial Value 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. P8DR stores output data for the port 8 pins that are used as the general output port. If a port 8 read is performed while the P8DDR bits are set to 1, the P8DR values are read. If a port 8 read is performed while the P8DDR bits are cleared to 0, the pin states are read.
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Section 8 I/O Ports
8.8.3
Pin Functions
* P86/IRQ5/SCK1/SCL1 The pin function is switched as shown below according to the combination of the SCL1AS and SCL1BS bits in PTCNT1, ICE bit in ICCR of IIC_1, C/A bit in SMR of SCI_1, CKE0 and CKE1 bits in SCR, and the P86DDR bit. When the ISS5 bit in ISSR is cleared to 0 and the IRQ5E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ5 input pin. IICENABLE in the following table is expressed by the following logical expressions. IICENABLE = 1 : ICE * SCL1AS * SCL1BS
IICENABLE CKE1 C/A CKE0 P86DDR Pin function 0 0 1 0 1 0 1 IRQ5 input pin 0 1 1 0 0 0 SCL1 input/output pin
P86 input pin P86 output pin SCK1 output pin SCK1 input pin
Note: To use this pin as the SCL1 input/output pin, clear the SCL1AS and SCL1BS bits in PTCNT1, CKE1, CKE0 bits in SCR of SCI_1 and C/A bit in SMR to 0. The output format for SCL1 is NMOS output only, and direct bus drive is possible. When this pin is used as the P86 output pin or SCK1 output pin, the output format is NMOS push-pull output.
* P85/IRQ4/RxD1/IrRxD The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_1 and the P85DDR bit. When the ISS4 bit in ISSR is cleared to 0 and the IRQ4E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ4 input pin.
RE P85DDR Pin function 0 P85 input pin 0 1 P85 output pin IRQ4 input pin 1 RxD1 input pin/IrRxD input pin
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Section 8 I/O Ports
* P84/IRQ3/TxD1/IrTxD The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1 and the P84DDR bit. When the ISS3 bit in ISSR is cleared to 0 and the IRQ3E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ3 input pin.
TE P84DDR Pin function 0 P84 input pin 0 1 P84 output pin IRQ3 input pin 1 TxD1 output pin/IrTxD output pin
* P83/LPCPD The pin function is switched as shown below according to the combination of the LPC4E bit in HICR4 of LPC, LPC3E to LPC1E bits in HICR0, LMCE bit in LMCCR1, and the P83DDR bit. LPCENABLE in the following table is expressed by the following logical expressions. LPCENABLE : LPC4E + LPC3E + LPC2E + LPC1E + LMCE
LPCENABLE P83DDR Pin function 0 P83 input pin 0 1 P83 output pin 1 LPCPD input pin
* P82/CLKRUN The pin function is switched as shown below according to the combination of the LPC4E bit in HICR4 of LPC, LPC3E to LPC1E bits in HICR0, LMCE bit in LMCCR1, and the P82DDR bit. LPCENABLE in the following table is expressed by the following logical expressions. LPCENABLE : LPC4E + LPC3E + LPC2E + LPC1E + LMCE
LPCENABLE P82DDR Pin function 0 P82 input pin 0 1 P82 output pin 1 CLKRUN input/output pin
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Section 8 I/O Ports
* P81/GA20 The pin function is switched as shown below according to the combination of the FGA20E bit in HICR0 of LPC and the P81DDR bit.
FGA20E P81DDR Pin function 0 P81 input pin 0 1 P81 output pin 1 GA20 output pin
* P80/PME The pin function is switched as shown below according to the combination of the PMEE bit in HICR0 of LPC and the P80DDR bit.
PMEE P80DDR Pin function 0 P80 input pin 0 1 P80 output pin 1 PME output pin
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Section 8 I/O Ports
8.9
Port 9
Port 9 is an 8-bit I/O port. Port 9 pins also function as the interrupt input pins, A/D converter inputs, sub-clock input pin, IIC_0 I/O pin, and the system clock output pin (). The output format for P97 is NMOS push-pull output. The output format for SDA0 is NMOS open-drain output, and direct bus drive is possible. Port 9 has the following registers. * Port 9 data direction register (P9DDR) * Port 9 data register (P9DR) * Port 9 pull-up MOS control register (P9PCR) 8.9.1 Port 9 Data Direction Register (P9DDR)
The individual bits of P9DDR specify input or output for the pins of port 9.
Bit 7 Bit Name P97DDR Initial Value 0 R/W W Description The corresponding port 9 pins are output ports when the P9DDR bits are set to 1, and input ports when cleared to 0. When this bit is set to 1, the corresponding port 96 pin is the system clock output pin (). The corresponding port 9 pins are output ports when the P9DDR bits are set to 1, and input ports when cleared to 0.
6 5 4 3 2 1 0
P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
0 0 0 0 0 0 0
W W W W W W W
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Section 8 I/O Ports
8.9.2
Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR * Initial Value 0 Undefined* 0 0 0 0 0 0 R/W R/W R R/W R/W R/W R/W R/W R/W Description P9DR stores output data for the port 9 pins that are used as the general output port except for bit 6. If a port 9 read is performed while the P9DDR bits are set to 1, the P9DR values are read. If a port 9 read is performed while the P9DDR bits are cleared to 0, the pin states are read.
The initial value of bit 6 is determined in accordance with the P96 pin state.
8.9.3
Port 9 Pull-Up MOS Control Register (P9PCR)
P9PCR controls the on/off state of the input pull-up MOS for port 9 pins.
Bit 7, 6 5 4 3 2 1 0 Bit Name P95PCR P94PCR P93PCR P92PCR P91PCR P90PCR Initial Value All 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. When the pins are in input state, the corresponding input pull-up MOS is turned on when a P9PCR bit is set to 1.
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Section 8 I/O Ports
8.9.4
Pin Functions
* P97/IRQ15/SDA0 The pin function is switched as shown below according to the combination of the SDA0AS and SDA0BS bits in PTCNT1, ICE bit in ICCR of IIC_0, and the P97DDR bit. When the ISS15 bit in ISSR16 is cleared to 0 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ15 input pin. IICENABLE in the following table is expressed by the following logical expressions. IICENABLE = 1 : ICE * SDA0AS * SDA0BS
IICENABLE P97DDR Pin function 0 P97 input pin 0 1 P97 output pin IRQ15 input pin 1 SDA0 I/O pin
Note: The output format for SDA0 is NMOS output only, and direct bus drive is possible. When this pin is used as the P97 output pin, the output format is NMOS push-pull output.
* P96//EXCL The pin function is switched as shown below according to the combination of the EXCLS bit in PTCNT0, EXCLE bit in LPWRCR, and the P96DDR bit.
EXCLS P96DDR EXCLE Pin function Note: * 0 P96 input pin 0 1 EXCL input pin 0 1 output pin* P96 input pin 0 output pin* 1 1
The subclock is output in subactive, subsleep, and watch modes.
* P95/IRQ14 The pin function is switched as shown below according to the P95DDR bit. When the ISS14 bit in ISSR16 is cleared to 0 and the IRQ14E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ14 input pin.
P95DDR Pin function 0 P95 input pin IRQ14 input pin 1 P95 output pin
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* P94/IRQ13 The pin function is switched as shown below according to the P94DDR bit. When the ISS13 bit in ISSR16 is cleared to 0 and the IRQ13E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ13 input pin.
P94DDR Pin function 0 P94 input pin IRQ13 input pin 1 P94 output pin
* P93/IRQ12 The pin function is switched as shown below according to the P93DDR bit. When the ISS12 bit in ISSR16 is cleared to 0 and the IRQ12E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ12 input pin.
P93DDR Pin function 0 P93 input pin IRQ12 input pin 1 P93 output pin
* P92/IRQ0 The pin function is switched as shown below according to the P92DDR bit. When the ISS0 bit in ISSR is cleared to 0 and the IRQ0E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ0 input pin.
P92DDR Pin function 0 P92 input pin IRQ0 input pin 1 P92 output pin
* P91/IRQ1 The pin function is switched as shown below according to the P91DDR bit. When the ISS1 bit in ISSR is cleared to 0 and the IRQ1E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ1 input pin.
P91DDR Pin function 0 P91 input pin IRQ1 input pin 1 P91 output pin
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* P90/IRQ2/ADTRG The pin function is switched as shown below according to the P90DDR bit. When the TRGS1 and TRGS0 bits in ADCR are both set to 1, this pin can be used as the ADTRG input pin. When the ISS2 bit in ISSR is cleared to 0 and the IRQ2E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ2 input pin.
P90DDR Pin function 0 P90 input pin IRQ2 input pin/ADTRG input pin 1 P90 output pin
8.9.5
Port 9 Input Pull-Up MOS
P95 to P90 have built-in input pull-up MOSs that can be controlled by software. Table 8.6 summarizes the input pull-up MOS states. Table 8.6
Reset Off
Port 9 Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off On when P9DDR = 0 and P9PCR = 1; otherwise off.
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Section 8 I/O Ports
8.10
Port A
Port A is an 8-bit I/O port. Port A pins also function as the keyboard input pins and KBU input/output pins. The output format for port A is NMOS push-pull output. Port A has the following registers. PADDR and PAPIN have the same address. * Port A data direction register (PADDR) * Port A output data register (PAODR) * Port A input data register (PAPIN) 8.10.1 Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A.
Bit 7 6 5 4 3 2 1 0 Bit Name PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port A pins are output ports when the PADDR bits are set to 1, and input ports when cleared to 0.
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8.10.2
Port A Output Data Register (PAODR)
PAODR stores output data for the port A pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PAODR stores output data for the port A pins that are used as the general output port.
8.10.3
Port A Input Data Register (PAPIN)
PAPIN indicates the pin states.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When a PAPIN read is performed, the pin states are read. This register is assigned to the same address as that of PADDR. When this register is written to, data is written to PADDR and the port A setting is then changed.
The initial values are determined in accordance with the pin states of PA7 to PA0.
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8.10.4
Pin Functions
* PA7/KIN15/PS2CD, PA6/KIN14/PS2CC, PA5/KIN13/PS2BD, PA4/KIN12/PS2BC, PA3/KIN11/PS2AD, PA2/KIN10/PS2AC The function of port A pins is switched according to the combination of the KBIOE bit in KBCRH of KBU and the PAnDDR bit. When the KMIMRm bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KINm input pin.
KBIOE PAnDDR Pin function 0 PAn input pin 0 1 PAn output pin KINm input pin 1 KBU input/output pin
Notes: n = 7 to 2 m = 15 to 10 When the KBIOE bit or IICS bit in STCR is set to 1, the output format for PA7 to PA4 is NMOS open-drain output, and direct bus drive is possible. When the KBIOE bit is set to 1, the output format for PA3 and PA2 is NMOS open-drain output, and direct bus drive is possible.
* PA1/KIN9, PA0/KIN8 The function of port A pins is switched as shown below according to the PAnDDR bit. When the KMIMRm bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KINm input pin.
PAnDDR Pin function 0 PAn input pin KINm input pin 1 PAn output pin
Note: n = 1, 0 m = 9, 8
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Section 8 I/O Ports
8.11
Port B
Port B is an 8-bit I/O port. Port B pins also function as the wake-up event input pins and LPC input/output pins. Port B has the following registers. PBDDR and PBPIN have the same address. * Port B data direction register (PBDDR) * Port B output data register (PBODR) * Port B input data register (PBPIN) 8.11.1 Port B Data Direction Register (PBDDR)
PBDDR is used to specify the input/output attribute of each pin of port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port B pins are output ports when the PBDDR bits are set to 1, and input ports when cleared to 0.
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8.11.2
Port B Output Data Register (PBODR)
PBODR stores output data for the port B pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PBODR register stores the output data for the pins that are used as the general output port.
8.11.3
Port B Input Data Register (PBPIN)
PBPIN indicates the pin states.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When a PBPIN read is performed, the pin states are read. This register is assigned to the same address as that of PBDDR. When this register is written to, data is written to PBDDR and the port B setting is then changed.
The initial value of these pins is determined in accordance with the state of pins PB7 to PB0.
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8.11.4
Pin Functions
* PB7/WUE7/DLAD0 The pin function is switched as shown below according to the combination of the LPCS bit in PTCNT2 and the PB7DDR bit. When the WUEM7 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE7 input pin.
LPCS PB7DDR Pin function 0 PB7 input pin 0 1 PB7 output pin WUE7 input pin 1 DLAD0 input/output pin
* PB6/WUE6/DLAD1 The pin function is switched as shown below according to the combination of the LPCS bit in PTCNT2 and the PB6DDR bit. When the WUEM6 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE6 input pin.
LPCS PB6DDR Pin function 0 PB6 input pin 0 1 PB6 output pin WUE6 input pin 1 DLAD1 input/output pin
* PB5/WUE5/DLAD2 The pin function is switched as shown below according to the combination of the LPCS bit in PTCNT2 and the PB5DDR bit. When the WUEM5 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE5 input pin.
LPCS PB5DDR Pin function 0 PB5 input pin 0 1 PB5 output pin WUE5 input pin 1 DLAD2 input/output pin
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* PB4/WUE4/DLAD3 The pin function is switched as shown below according to the combination of the LPCS bit in PTCNT2 and the PB4DDR bit. When the WUEM4 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE4 input pin.
LPCS PB4DDR Pin function 0 PB4 input pin 0 1 PB4 output pin WUE4 input pin 1 DLAD3 input/output pin
* PB3/WUE3/DLFRAME The pin function is switched as shown below according to the combination of the LPCS bit in PTCNT2 and the PB3DDR bit. When the WUEM3 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE3 input pin.
LPCS PB3DDR Pin function 0 PB3 input pin 0 1 PB3 output pin WUE3 input pin 1 DLFRAME output pin
* PB2/WUE2 The pin function is switched as shown below according to the PB2DDR bit. When the WUEM2 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE2 input pin.
PB2DDR Pin function 0 PB2 input pin WUE2 input pin 1 PB2 output pin
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* PB1/ WUE1/LSCI The pin function is switched as shown below according to the combination of the LSCIE bit in HICR0 of LPC and the PB1DDR bit. When the WUEM1 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE1 input pin.
LSCIE PB1DDR Pin function 0 PB1 input pin 0 1 PB1 output pin WUE1 input pin 1 LSCI output pin
* PB0/WUE0/LSMI The pin function is switched as shown below according to the combination of the LSMIE bit in HICR0 of LPC and the PB0DDR bit. When the WUEM0 bit in WUEMRB of the interrupt controller is cleared to 0, this pin can be used as the WUE0 input pin.
LSMIE PB0DDR Pin function 0 PB0 input pin 0 1 PB0 output pin WUE0 input pin 1 LSMI output pin
8.11.5
Port B Input Pull-Up MOS
Port B has a built-in input pull-up MOS that can be controlled by software. Table 8.7 summarizes the input pull-up MOS states. Table 8.7
Reset Off
Port B Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off: On when PBDDR = 0 and PBODR = 1; otherwise off.
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Section 8 I/O Ports
8.12
Port C
Port C is an 8-bit I/O port. Port C pins also function as the wake-up event inputs, noise cancel input pins, and LPC input/output pins. Port C has the following registers. PCDDR and PCPIN have the same address. * * * * * * * Port C data direction register (PCDDR) Port C output data register (PCODR) Port C input data register (PCPIN) Port C Nch-OD control register (PCNOCR) Noise canceller enable register (PCNCE) Noise canceller decision control register (PCNCMC) Noise cancel cycle setting register (PCNCCS) Port C Data Direction Register (PCDDR)
8.12.1
The individual bits of PCDDR specify input or output for the pins of port C.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port C pins are output ports when the PCDDR bits are set to 1, and input ports when cleared to 0.
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Section 8 I/O Ports
8.12.2
Port C Output Data Register (PCODR)
PCODR stores output data for the port C pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PCODR register stores the output data for the pins that are used as the general output port.
8.12.3
Port C Input Data Register (PCPIN)
PCPIN indicates the pin states.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PC7PIN PC6PIN PC5PIN PC4PIN PC3PIN PC2PIN PC1PIN PC0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When a PCPIN read is performed, the pin states are read. This register is assigned to the same address as that of PCDDR. When this register is written to, data is written to PCDDR and the port C setting is then changed.
The initial value of these pins is determined in accordance with the state of pins PC7 to PC0.
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8.12.4
Noise Canceller Enable Register (PCNCE)
PCNCE enables or disables the noise cancel circuit at port C.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7NCE PC6NCE PC5NCE PC4NCE PC3NCE PC2NCE PC1NCE PC0NCE Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Noise cancel circuit is enabled when PCNCE bit is set to 1, and the pin state is fetched in the PCPIN in the sampling cycle set by the PCNCCS.
8.12.5
Noise Canceller Mode Control Register (PCNCMC)
PCNCMC controls whether 1 or 0 is expected for the input signal to port C in bit units.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7NCMC PC6NCMC PC5NCMC PC4NCMC PC3NCMC PC2NCMC PC1NCMC PC0NCMC Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 1 expected: 1 is stored in the port data register when 1 is input stably 0 expected: 0 is stored in the port data register when 0 is input stably
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8.12.6
Noise Cancel Cycle Setting Register (PCNCCS)
PCNCCS controls the sampling cycles of the noise canceller.
Bit Bit Name Initial Value Undefined R/W R/W Description Reserved The read data is undefined. The initial value should not be changed. 2 1 0 PCNCCK2 PCNCCK1 PCNCCK0 0 0 0 R/W R/W R/W These bits set the sampling cycles of the noise canceller. When is 10 MHz 000: 001: 010: 011: 100: 101: 110: 111: 0.88 s 12.8 s 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 104.9 ms /2 /32 /8192 /16384 /32768 /65536 /131072 /262144
7 to 3
8.12.7
Pin Functions
* PC7/WUE15/DLDRQ The pin function is switched as shown below according to the combination of the LDRQS bit in PTCNT2 and the PC7DDR. When the WUEMR15 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE15 input pin.
LDRQS PC7DDR Pin Function 0 PC7 input pin 0 1 PC7 output pin WUE15 input pin 1 DLDRQ input pin
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* PC6/WUE14/LDRQ The pin function is switched as shown below according to the combination of the LDRQS bit in PTCNT2 and the PC6DDR. When the WUEMR14 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE14 input pin.
LDRQS PC6DDR Pin Function 0 PC6 input pin 0 1 PC6 output pin WUE14 input pin 1 LDRQ output pin
* PC5/WUE13 The pin function is switched as shown below according to the PC5DDR. When the WUEMR13 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE13 input pin.
PC5DDR Pin Function 0 PC5 input pin WUE13 input pin 1 PC5 output pin
* PC4/WUE12 The pin function is switched as shown below according to the PC4DDR. When the WUEMR12 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE12 input pin.
PC4DDR Pin Function 0 PC4 input pin WUE12 input pin 1 PC4 output pin
* PC3/WUE11 The pin function is switched as shown below according to the PC3DDR. When the WUEMR11 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE11 input pin.
PC3DDR Pin Function 0 PC3 input pin WUE11 input pin 1 PC3 output pin
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* PC2/WUE10 The pin function is switched as shown below according to the PC2DDR. When the WUEMR10 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE10 input pin.
PC2DDR Pin Function 0 PC2 input pin WUE10 input pin 1 PC2 output pin
* PC1/WUE9 The pin function is switched as shown below according to the PC1DDR. When the WUEMR9 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE9 input pin.
PC1DDR Pin Function 0 PC1 input pin WUE9 input pin 1 PC1 output pin
* PC0/WUE8 The pin function is switched as shown below according to the PC0DDR. When the WUEMR8 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE8 input pin.
PC0DDR Pin Function 0 PC0 input pin WUE8 input pin 1 PC0 output pin
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Section 8 I/O Ports
8.12.8
Port C Nch-OD control register (PCNOCR)
The individual bits of PCNOCR specify output driver type for the pins of port C that is specified to output.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7NOCR PC6NOCR PC5NOCR PC4NOCR PC3NOCR PC2NOCR PC1NOCR PC0NOCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: CMOS (P channel driver is enable) 1: N channel open-drain (P channel driver is disable)
8.12.9
DDR NOCR ODR
Pin Functions
0 0 Off Off Off Input pin On 1 0 On Off 0 1 Off On Off Output pin 0 On Off 1 1 1 Off
N-ch driver P-ch driver Input pull-up MOS Pin function
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Section 8 I/O Ports
8.12.10 Port C Input Pull-Up MOS Port C has a built-in input pull-up MOS that can be controlled by software. Input pull-up MOS can be specified as on or off on an individual bit basis. Table 8.8 summarizes the input pull-up MOS states. Table 8.8
Reset Off
Port C Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off On when PCDDR = 0 and PCODR = 1; otherwise off.
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Section 8 I/O Ports
8.13
Port D
Port D is an 8-bit I/O port. Port D pins also function as the TPU I/O pins. Port D has the following registers. PDDDR and PDPIN have the same address. * * * * Port D data direction register (PDDDR) Port D output data register (PDODR) Port D input data register (PDPIN) Port D Nch-OD control register (PDNOCR) Port D Data Direction Register (PDDDR)
8.13.1
The individual bits of PDDDR specify input or output for the pins of port D.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port D pins are output ports when the PDDDR bits are set to 1, and input ports when cleared to 0.
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Section 8 I/O Ports
8.13.2
Port D Output Data Register (PDODR)
PDODR stores output data for the port D pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PDODR register stores the output data for the pins that are used as the general output port.
8.13.3
Port D Input Data Register (PDPIN)
PDPIN indicates the pin states of port D.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PD7PIN PD6PIN PD5PIN PD4PIN PD3PIN PD2PIN PD1PIN PD0PIN * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When a PDPIN read is performed, the pin states are read.
The initial value of these pins is determined in accordance with the state of pins PD7 to PD0.
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Section 8 I/O Ports
8.13.4
Pin Functions
* PD7/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the TPU channel 2 setting, TPSC2 to TPSC0 bits in TCR_0 of TPU, and the PD7DDR.
TPU Channel 2 Setting PD7DDR Pin Function 0 PD7 input pin Input or Initial Value 1 PD7 output pin
2
Output TIOCB2 output pin
TIOCB2 input pin*
TCLKD input pin*
1
Notes: 1. This pin functions as TCLKD input when TPSC2 to TPSC0 in TCR_0 are set to 111 or when channel 2 is set to phase counting mode. 2. This pin functions as TIOCB2 input when TPU channel 2 timer operating mode is set to normal operation or phase counting mode and IOB3 in TIOR_2 is set to 1.
* PD6/TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 setting and the PD6DDR.
TPU Channel 2 Setting PD6DDR Pin Function 0 PD6 input pin Input or Initial Value 1 PD6 output pin Output TIOCA2 output pin
TIOCA2 input pin*
Note:
*
This pin functions as TIOCA2 input when TPU channel 2 timer operating mode is set to normal operation or phase counting mode and IOA3 in TIOR_2 is set to 1.
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Section 8 I/O Ports
* PD5/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting, TPSC2 to TPSC0 bits in TCR_0 and TCR_2 of TPU, and the PD5DDR.
TPU Channel 1 Setting PD5DDR Pin Function 0 PD5 input pin Input or Initial Value 1 PD5 output pin
2
Output TIOCB1 output pin
TIOCB1 input pin*
TCLKC input pin*
1
Notes: 1. This pin functions as TCLKC input when TPSC2 to TPSC0 in TCR_0 or TCR_2 are set to 110 or when channel 2 is set to phase counting mode. 2. This pin functions as TIOCB1 input when TPU channel 1 timer operating mode is set to normal operation or phase counting mode and IOB3 to IOB0 in TIOR_1 are set to 10xx.
* PD4/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 setting and the PD4DDR.
TPU Channel 1 Setting PD4DDR Pin Function 0 PD4 input pin Input or Initial Value 1 PD4 output pin Output TIOCA1 output pin
TIOCA1 input pin*
Note:
*
This pin functions as TIOCA1 input when TPU channel 1 timer operating mode is set to normal operation or phase counting mode and IOA3 to IOA0 in TIOR_2 are set to 10xx.
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Section 8 I/O Ports
* PD3/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 setting, TPSC2 to TPSC0 bits in TCR_0 to TCR_2 of TPU, and the PD3DDR.
TPU Channel 0 Setting PD3DDR Pin Function 0 PD3 input pin Input or Initial Value 1 PD3 output pin
2
Output TIOCD0 output pin
TIOCD0 input pin*
TCLKB input pin*
1
Notes: 1. This pin functions as TCLKB input when TPSC2 to TPSC0 in any of TCR_0, TCR_1, and TCR_2 are set to 101 or when channel 1 is set to phase counting mode. 2. This pin functions as TIOCD0 input when TPU channel 0 timer operating mode is set to normal operation or phase counting mode and IOD3 to IOD0 in TIOR_0 are set to 10xx.
* PD2/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 setting, TPSC2 to TPSC0 bits in TCR_0 to TCR_2 of TPU, and the PD2DDR.
TPU Channel 0 Setting PD2DDR Pin Function 0 PD2 input pin Input or Initial Value 1 PD2 output pin
2
Output TIOCC0 output pin
TIOCC0 input pin*
TCLKA input pin*
1
Notes: 1. This pin functions as TCLKA input when TPSC2 to TPSC0 in any of TCR_0, TCR_1, and TCR_2 are set to 100 or when channel 1 is set to phase counting mode. 2. This pin functions as TIOCC0 input when TPU channel 0 timer operating mode is set to normal operation or phase counting mode and IOC3 to IOC0 in TIOR_0 are set to 10xx.
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Section 8 I/O Ports
* PD1/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 setting and the PD1DDR.
TPU Channel 0 Setting PD1DDR Pin Function 0 PD1 input pin Input or Initial Value 1 PD1 output pin Output TIOCB0 output pin
TIOCB0 input pin*
Note:
*
This pin functions as TIOCB0 input when TPU channel 0 timer operating mode is set to normal operation or phase counting mode and IOB3 to IOB0 in TIORH_0 are set to 10xx.
* PD0/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 setting and the PD0DDR.
TPU Channel 0 Setting PD0DDR Pin Function 0 PD0 input pin Input or Initial Value 1 PD0 output pin Output TIOCA0 output pin
TIOCA0 input pin*
Note:
*
This pin functions as TIOCA0 input when TPU channel 0 timer operating mode is set to normal operation or phase counting mode and IOA3 to IOA0 in TIORH_0 are set to 10xx. For the setting of the TPU channel, see section 12, 16-bit Timer Pulse Unit (TPU).
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Section 8 I/O Ports
8.13.5
Port D Nch-OD control register (PDNOCR)
The individual bits of PDNOCR specify output driver type for the pins of port D that is specified to output.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7NOCR PD6NOCR PD5NOCR PD4NOCR PD3NOCR PD2NOCR PD1NOCR PD0NOCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: CMOS (P channel driver is enable) 1: N channel open-drain (P channel driver is disable)
8.13.6
DDR NOCR ODR
Pin Functions
0 0 Off Off Off Input pin On 1 0 On Off 0 1 Off On Off Output pin 0 On Off 1 1 1 Off
N-ch driver P-ch driver Input pull-up MOS Pin function
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Section 8 I/O Ports
8.13.7
Port D Input Pull-Up MOS
Port D has a built-in input pull-up MOS that can be controlled by software. Input pull-up MOS can be specified as on or off on an individual bit basis. Table 8.9 summarizes the input pull-up MOS states. Table 8.9
Reset Off
Port D Input Pull-Up MOS States
Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off On when PCDDR = 0 and PDODR = 1; otherwise off.
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Section 8 I/O Ports
8.14
Port E
Port E is a 5-bit input port. Port E pins also function as the LPC input pins and emulator input/output pins. Port E has the following registers. * Port E input pull-up MOS control register (PEPCR) * Port E input data register (PEPIN) 8.14.1 Port E Input Pull-Up MOS Control Register (PEPCR)
PEPCR specifies each bit in input pull-up MOS on/off.
Bit Bit Name Initial Value All 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. 4 3 2 1 0 PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR 0: Input pull-up MOS is off 1: Input pull-up MOS is on
7 to 5
8.14.2
Port E Input Data Register (PEPIN)
PEPIN indicates the pin states of port E.
Bit Bit Name Initial Value All 0 Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R Description Reserved These bits are always read as 0. 4 3 2 1 0 Note: PE4PIN PE3PIN PE2PIN PE1PIN PE0PIN * When these bits are read, the pin states are returned. These bits cannot be modified.
7 to 5
The initial value of these pins is determined in accordance with the state of pins PE4 to PE0.
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Section 8 I/O Ports
8.14.3
Pin Functions
* PE4, PE3, PE2, PE1 The pin function is switched as shown below according to the PEnDDR.
Pin Function PEn input pin
Note: n = 4 to 1 The PE5 to PE1 pins are not supported in the system development tool (emulator).
* PE0/LID3 The function of port E pin is switched as shown below according to the combination of the LMCE bit in LMCCR of LPC.
LMCE Pin function 0 PE0 input pin 1 PE0, LID3 input pin
8.14.4
Port E Input Pull-Up MOS
Port E has a built-in input pull-up MOS that can be controlled by software. Input pull-up MOS can be specified as on or off on an individual bit basis. Table 8.10 summarizes the input pull-up MOS states. Table 8.10 Port E Input Pull-Up MOS States
Reset Off Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off On when PEPCR = 1; otherwise off.
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Section 8 I/O Ports
8.15
Port F
Port F is an 8-bit I/O port. Port F pins also function as the interrupt input pins and TMR_X and PWM output pins. Port F has the following registers. PFDDR and PFPIN have the same address. * * * * Port F data direction register (PFDDR) Port F output data register (PFODR) Port F input data register (PFPIN) Port F Nch-OD control register (PFNOCR) Port F Data Direction Register (PFDDR)
8.15.1
The individual bits of PFDDR specify input or output for the pins of port F.
Bit 7 6 5 4 3 2 1 0 Bit Name PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port F pins are output ports when the PFDDR bits are set to 1, and input ports when cleared to 0.
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Section 8 I/O Ports
8.15.2
Port F Output Data Register (PFODR)
PFODR stores output data for the port F pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PF7ODR PF6ODR PF5ODR PF4ODR PF3ODR PF2ODR PF1ODR PF0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PFODR register stores the output data for the pins that are used as the general output port.
8.15.3
Port F Input Data Register (PFPIN)
PFPIN indicates the pin states of port F.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value PF7PIN PF6PIN PF5PIN PF4PIN PF3PIN PF2PIN PF1PIN PF0PIN * Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When PFPIN is read, the pin states are returned.
The initial value of these pins is determined in accordance with the state of pins PF7 to PF0.
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8.15.4
Pin Functions
* PF7/ExPW15, PF6/ExPW14 The function of port F pins is switched as shown below according to the combination of the PWMAS bit in PTCNT0, the OEm bit in PWOERB of PWM, and the PFnDDR bit.
PWMAS PFnDDR OEm Pin function Note: n = 7, 6 m = 15, 14 PFn input pin 0 PFn output pin 0 1 0 PFn input pin 0 PFn output pin 1 1 1 ExPWm output pin
* PF5/ExPW13, PF4/ExPW12 The function of port F pins is switched as shown below according to the combination of the PWMBS bit in PTCNT0, the OEm bit in PWOERB of PWM, and the PFnDDR bit.
PWMBS PFnDDR OEm Pin function Note: n = 5, 4 m = 13, 12 PFn input pin 0 PFn output pin 0 1 0 PFn input pin 0 PFn output pin 1 1 1 ExPWm output pin
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Section 8 I/O Ports
* PF3/IRQ11/ExTMOX The pin function is switched as shown below according to the combination of the TMOXS bit in PTCNT0, OS3 to OS0 bits in TCSR of TMR_X, and PF3DDR bit. When the ISS11 bit in ISSR16 is cleared to 0 and the IRQ11E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ11 input pin.
TMOXS OS3 to OS0 PF3DDR Pin Function 0 PF3 input pin 0 1 PF3 output pin 0 PF3 input pin IRQ11 input pin All 0 1 PF3 output pin 1
One bit is set as 1
ExTMOX output pin
* PF2/IRQ10, PF1/IRQ9, PF0/IRQ8 The pin function is switched as shown below according to the PFnDDR bit. When the ISSm bit in ISSR16 is cleared to 0 and the IRQmE bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQm input pin.
PFnDDR Pin function Note: n = 2 to 0 m = 10 to 8 0 PFn input pin IRQm input pin 1 PFn output pin
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Section 8 I/O Ports
8.15.5
Port F Nch-OD control register (PFNOCR)
The individual bits of PFNOCR specify output driver type for the pins of port F that is specified to output.
Bit 7 6 5 4 3 2 1 0 Bit Name PF7NOCR PF6NOCR PF5NOCR PF4NOCR PF3NOCR PF2NOCR PF1NOCR PF0NOCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: CMOS (P channel driver is enable) 1: N channel open-drain (P channel driver is disable)
8.15.6
DDR NOCR ODR N-ch driver P-ch driver
Pin Functions
0 0 Off Off Off Input pin On 1 0 On Off 0 1 Off On Off Output pin 0 On Off 1 1 1 Off
Input pull-up MOS Pin function
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Section 8 I/O Ports
8.15.7
Port F Input Pull-Up MOS
Port F has a built-in input pull-up MOS that can be controlled by software. Input pull-up MOS can be specified as on or off on an individual bit basis. Table 8.11 summarizes the input pull-up MOS states. Table 8.11 Port F Input Pull-Up MOS States
Reset Off Hardware Standby Mode Off Software Standby Mode On/Off In Other Operations On/Off
[Legend] Off: Always off. On/Off On when PFDDR = 0 and PFODR = 1; otherwise off.
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Section 8 I/O Ports
8.16
Port G
Port G is an 8-bit I/O port. Port G pins also function as the interrupt input pins, and TMR_0, TMR_1, TMR_X, TMR_Y input pins and IIC_0, and IIC_1 input/output pins. The output format for port G is NMOS push-pull output. Port G has the following registers. PGDDR and PGPIN have the same address. * * * * * * * Port G data direction register (PGDDR) Port G output data register (PGODR) Port G input data register (PGPIN) Port G Nch-OD control register (PGNOCR) Noise canceller enable register (PGNCE) Noise canceller decision control register (PGNCMC) Noise cancel cycle setting register (PGNCCS) Port G Data Direction Register (PGDDR)
8.16.1
The individual bits of PGDDR specify input or output for the pins of port G.
Bit 7 6 5 4 3 2 1 0 Bit Name PG7DDR PG6DDR PG5DDR PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding port G pins are output ports when the PGDDR bits are set to 1, and input ports when cleared to 0.
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Section 8 I/O Ports
8.16.2
Port G Output Data Register (PGODR)
PGODR stores output data for the port G pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PG7ODR PG6ODR PG5ODR PG4ODR PG3ODR PG2ODR PG1ODR PG0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The PGODR register stores the output data for the pins that are used as the general output port.
8.16.3
Port G Input Data Register (PGPIN)
PGPIN indicates the pin states of port G.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value PG7PIN PG6PIN PG5PIN PG4PIN PG3PIN PG2PIN PG1PIN PG0PIN * Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When PGPIN is read, the pin states are returned. This register is assigned to the same address as that of PGDDR. When this register is written to, data is written to PGDDR and the port G setting is then changed.
The initial value of these pins is determined in accordance with the state of pins PG7 to PG0.
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Section 8 I/O Ports
8.16.4
Noise Canceller Enable Register (PGNCE)
PGNCE enables or disables the noise cancel circuit at port G. To use the port G pins as the IIC_0 and IIC_1input/output pins, these bits in PGNCE should be disabled.
Bit 7 6 5 4 3 2 1 0 Bit Name PG7NCE PG6NCE PG5NCE PG4NCE PG3NCE PG2NCE PG1NCE PG0NCE Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Noise cancel circuit is enabled when PGNCE bit is set to 1, and the pin state is fetched in the PGPIN in the sampling cycle set by the PGNCCS.
8.16.5
Noise Canceller Mode Control Register (PGNCMC)
PGNCMC controls whether 1 or 0 is expected for the input signal to port G in bit units.
Bit 7 6 5 4 3 2 1 0 Bit Name PG7NCMC PG6NCMC PG5NCMC PG4NCMC PG3NCMC PG2NCMC PG1NCMC PG0NCMC Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 1 expected: 1 is stored in the port data register when 1 is input 0 expected: 0 is stored in the port data register when 0 is input
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Section 8 I/O Ports
8.16.6
Noise Cancel Cycle Setting Register (PGNCCS)
PGNCCS controls the sampling cycles of the noise canceller.
Bit Bit Name Initial Value Undefined R/W R/W Description Reserved The read data is undefined. The initial value should not be changed. 2 1 0 PGNCCK2 PGNCCK1 PGNCCK0 0 0 0 R/W R/W R/W These bits set the sampling cycles of the noise canceller. When is 10 MHz 000: 001: 010: 011: 100: 101: 110: 111: 0.88 s 12.8 s 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 104.9 ms /2 /32 /8192 /16384 /32768 /65536 /131072 /262144
7 to 3
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Section 8 I/O Ports
8.16.7
Pin Functions
* PG7/ExIRQ15/ExSCLB The pin function is switched as shown below according to the combination of the SCL1BS and SCL0BS bits in PTCNT1, ICE bit in ICCR of IIC_1 and IIC_0, and the PG7DDR bit. When the ISS15 bit in ISSR16 is set to 1 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ15 input pin.
SCL1BS SCL0BS ICE_1 ICE_0 PG7DDR Pin function 0 1 0 1 ExSCLB (SCL1) input/output pin 0 0 0 0 1 0 1 1 0 1 1 ExSCLB (SCL0) input/output pin
PG7 PG7 PG7 PG7 input pin output pin input pin output pin
PG7 PG7 input pin output pin
ExIRQ15 input pin
Note: SCL1BS and SCL0BS, SCL1BS and SCL1AS, and SCL0BS and SCL0AS should not be set to 1 at the same time. The output format for ExSCLB is NMOS open-drain output, and direct bus drive is possible.
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Section 8 I/O Ports
* PG6/ExIRQ14/ExSDAB The pin function is switched as shown below according to the combination of the SDA1BS and SDA0BS bits in PTCNT1, ICE bit in ICCR of IIC_1 and IIC_0, and the PG6DDR bit. When the ISS14 bit in ISSR16 is set to 1 and the IRQ14E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ14 input pin.
SDA1BS SDA0BS ICE_1 ICE_0 PG6DDR Pin function 0 1 0 1 ExSDAB (SDA1) input/output pin 0 0 0 0 1 0 1 1 0 1 1 ExSDAB (SDA0) input/output pin
PG6 PG6 PG6 PG6 input pin output pin input pin output pin
PG6 PG6 input pin output pin
ExIRQ14 input pin
Note: SDA1BS and SDA0BS, SDA1BS and SDA1AS, and SDA0BS and SDA0AS should not be set to 1 at the same time. The output format for ExSDAB is NMOS open-drain output, and direct bus drive is possible.
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Section 8 I/O Ports
* PG5/ExIRQ13/ExSCLA The pin function is switched as shown below according to the combination of the SCL1AS and SCL0AS bits in PTCNT1, ICE bit in ICCR of IIC_1 and IIC_0, and the PG5DDR bit. When the ISS13 bit in ISSR16 is set to 1 and the IRQ13E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ13 input pin.
SCL1AS SCL0AS ICE_1 ICE_0 PG5DDR Pin function 0 1 0 1 ExSCLA (SCL1) input/output pin 0 0 0 0 1 0 1 1 0 1 1 ExSCLA (SCL0) input/output pin
PG5 PG5 PG5 PG5 input pin output pin input pin output pin
PG5 PG5 input pin output pin
ExIRQ13 input pin
Note: SCL1AS and SCL0AS, SCL1AS and SCL1BS, and SCL0AS and SCL0BS should not be set to 1 at the same time. The output format for ExSCLA is NMOS open-drain output, and direct bus drive is possible.
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Section 8 I/O Ports
* PG4/ExIRQ12/ExSDAA The pin function is switched as shown below according to the combination of the SDA1AS and SDA0AS bits in PTCNT1, ICE bit in ICCR of IIC_1 and IIC_0, and the PG4DDR bit. When the ISS12 bit in ISSR16 is set to 1 and the IRQ12E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ12 input pin.
SDA1AS SDA0AS ICE_1 ICE_0 PG4DDR Pin function 0 1 0 1 ExSDAA (SDA1) input/output pin 0 0 0 0 1 0 1 1 0 1 1 ExSDAA (SDA0) input/output pin
PG4 PG4 PG4 PG4 input pin output pin input pin output pin
PG4 PG4 input pin output pin
ExIRQ12 input pin
Note: SDA1AS and SDA0AS, SDA1AS and SDA1BS, and SDA0AS and SDA0BS should not be set to 1 at the same time. The output format for ExSDAA is NMOS open-drain output, and direct bus drive is possible.
* PG3/ExIRQ11/ExTMIY The pin function is switched as shown below according to the PG3DDR bit. When the TMIYS bit in PTCNT0 and the CCLR1 and CCLR0 bits in TCR of TMR_Y are cleared to 0, this pin is used as the ExTMIY (ExTMRIY) input pin. When the ISS11 bit in ISSR16 is set to 1 and the IRQ11E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ11 input pin.
PG3DDR Pin function 0 PG3 input pin 1 PG3 output pin ExIRQ11 input pin/ExTMIY input pin
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Section 8 I/O Ports
* PG2/ExIRQ10/ExTMIX The pin function is switched as shown below according to the PG2DDR bit. When the TMIXS bit in PTCNT0 and the CCLR1 and CCLR0 bits in TCR of TMR_X are cleared to 0, this pin is used as the ExTMIX (ExTMRIX) input pin. When the ISS10 bit in ISSR16 is set to 1 and the IRQ10E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ10 input pin.
PG2DDR Pin function 0 PG2 input pin 1 PG2 output pin ExIRQ10 input pin/ExTMIX input pin
* PG1/ExIRQ9/ExTMCI1 The pin function is switched as shown below according to the PG1DDR bit. When the TMCI1S bit in PTCNT0 is set to 1 and the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_1, this bit is used as the ExTMCI1 input pin. When the ISS9 bit in ISSR16 is set to 1 and the IRQ9E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ9 input pin.
PG1DDR Pin function 0 PG1 input pin 1 PG1 output pin
ExIRQ9 input pin/ExTMCI1 input pin
* PG0/ExIRQ8/ExTMCI0 The pin function is switched as shown below according to the PG0DDR bit. When the TMCI0S bit in PTCNT0 is set to 1 and the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_0, this bit is used as the ExTMCI0 input pin. When the ISS8 bit in ISSR16 is set to 1 and the IRQ8E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ8 input pin.
PG0DDR Pin function 0 PG0 input pin 1 PG0 output pin
ExIRQ8 input pin/ExTMCI0 input pin
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Section 8 I/O Ports
8.16.8
Port G Nch-OD control register (PGNOCR)
The individual bits of PGNOCR specify output driver type for the pins of port G that is specified to output.
Bit 7 6 5 4 3 2 1 0 Bit Name PG7NOCR PG6NOCR PG5NOCR PG4NOCR PG3NOCR PG2NOCR PG1NOCR PG0NOCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: NMOS push-pull (N channel driver in VCC side is enable) 1: N channel open-drain in VSS side (N channel driver in VCC side is disable)
8.16.9
DDR NOCR ODR
Pin Functions
0 0 Off Off Input pin 1 0 On Off 0 1 Off On Output pin 0 On Off 1 1 1 Off
N-ch driver in VSS side N-ch driver in VCC side Pin function
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Section 8 I/O Ports
8.17
Change of Peripheral Function Pins
For the 8-bit timer input/output, 8-bit PWM timer output, and IIC input/output, the multi-function I/O ports can be changed. I/O ports that also function as the external sub-clock input pin, 8-bit timer input/output pins, and the 8-bit PWM timer output pins are changed according to the setting of PTCNT0. I/O ports that also function as the IIC input/output pins are changed according to the setting of PTCNT1. I/O ports that also function as the docking LPC input/output pins are changed according to the setting of PTCNT2. The pin name of the peripheral function is indicated by adding `Ex' at the head of the original pin name. In each peripheral function description, the original pin name is used. 8.17.1 Port Control Register 0 (PTCNT0)
PTCNT0 selects ports that also function as the external sub-clock input pin, 8-bit timer input/output pins, and 14-bit PWM timer output pins.
Bit 7 6 5 4 3 2 1 0 Bit Name TMCI0S TMCI1S TMIXS TMIYS TMOXS PWMAS PWMBS EXCLS Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: P40/TMCI0 is selected 1: PG0/ExTMCI0 is selected 0: P43/TMCI1 is selected 1: PG1/ExTMCI1 is selected 0: P60/TMIX is selected 1: PG2/ExTMIX is selected 0: P62/TMIY is selected 1: PG3/ExTMIY is selected 0: P67/TMOX is selected 1: PF3/ExTMOX is selected 0: P27/PW15 and P26/PW14 are selected 1: PF7/ExPW15 and PF6/ExPW14 are selected 0: P25/PW13 and P24/PW12 are selected 1: PF5/ExPW13 and PF4/ExPW12 are selected 0: P96/EXCLK is selected 1: P50/ExEXCL is selected
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Section 8 I/O Ports
8.17.2
Port Control Register 1 (PTCNT1)
PTCNT1 selects ports that also function as IIC input/output pins.
Bit 7 6 5 4 Bit Name Initial Value R/W SCL0AS SCL1AS SCL0BS SCL1BS 0 0 0 0 R/W R/W R/W R/W 0000: 1000: 0100: 0010: 0001: 1001: 0110: 3 2 1 0 SDA0AS SDA1AS SDA0BS SDA1BS 0 0 0 0 R/W R/W R/W R/W 0000: 1000: 0100: 0010: 0001: 1001: 0110: Description IIC0 P52/SCL0 PG5/ExSCLA P52/SCL0 PG7/ExSCLB P52/SCL0 PG5/ExSCLA PG7/ExSCLB IIC0 P97/SDA0 PG4/ExSDAA P97/SDA0 PG6/ExSDAB P97/SDA0 PG4/ExSDAA PG6/ExSDAB IIC1 P86/SCL1 P86/SCL1 PG5/ExSCLA P86/SCL1 PG7/ExSCLB PG7/ExSCLB PG5/ExSCLA IIC1 P42/SDA1 P42/SDA1 PG4/ExSDAA P42/SDA1 PG6/ExSDAB PG6/ExSDAB PG4/ExSDAA
Settings other than those shown above are prohibited.
Settings other than those shown above are prohibited. Note: PTCNT1 must be written to while the ICE bit in ICCR is cleared to 0.
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Section 8 I/O Ports
8.17.3
Port Control Register 2 (PTCNT2)
PTCNT2 selects ports that also function as docking LPC input/output pins. Setting 1 to one of LPC3E to LPC1E in HICR0 and LPC4E in HICR4 enables this function.
Bit 7 Bit Name LPCS Initial Value 0 R/W R/W Description 0: PB7/WUE7, PB6/WUE6, PB5/WUE5, PB4/WUE4, PB3/WUE3, P41/TMO0/RxD2, P40/TMCI0/TxD2 are selected 1: PB7/WUE7/DLAD0, PB6/WUE6/DLAD1, PB5/WUE5/DLAD2, PB4/WUE4/DLAD3, PB3/WUE3/DLFRAME, P41/DCLKRUN, P40/TMCI0/DSERIRQ are selected 6 to 1 0 LDRQS All 0 0 R/W R/W Reserved The initial value should not be changed. 0: PC6/WUE14, PC7/WUE15 are selected 1: PC6/WUE14/LDRQ, PC7/WUE15/DLDRQ are selected
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Section 8 I/O Ports
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Section 9 8-Bit PWM Timer (PWM)
Section 9 8-Bit PWM Timer (PWM)
This LSI has an on-chip pulse width modulation (PWM) timer with eight outputs. Eight output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division. Connecting a low pass filter externally to the LSI enables the PWM to function as an 8-bit D/A converter.
9.1
Features
* Operable at a maximum carrier frequency of 1.25 MHz using pulse division (at 20 MHz operation) * Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output) * Direct or inverted PWM output, and PWM output enable/disable control * Selection of general ports for PWM output PW15/PW14 or ExPW15/ExPW14 PW13/PW12 or ExPW13/ExPW12
PWM0800A_000020020300
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Section 9 8-Bit PWM Timer (PWM)
Figure 9.1 shows a block diagram of the PWM timer.
P20/PW8 P21/PW9 P23/PW11 P24/PW12 PF4/ExPW12 P25/PW13 PF5/ExPW13 P26/PW14 PF6/ExPW14 P27/PW15 PF7/ExPW15 Clock counter
Port/PWM output control
P22/PW10
Comparator 8 Comparator 9 Comparator 10 Comparator 11 Comparator 12 Comparator 13 Comparator 14 Comparator 15
PWDR8 PWDR9 PWDR10
Module data bus Internal data bus
PWDR12 PWDR13 PWDR14 PWDR15
PWDPRB PWOERB P2DDR PFDDR PTCNTO [Legend] PWM register select PWSL: PWM data register PWDR: PWDPRB: PWM data polarity register B PWOERB: PWM output enable register B Peripheral clock select register PCSR: P2DDR: Port 2 data direction register PFDDR: Port F data direction register PTCNT0: Port control register 0
Select clock
PWSL PCSR
/2
/4
/8
/16
Internal clock
Figure 9.1 Block Diagram of PWM Timer
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Bus interface
PWDR11
Section 9 8-Bit PWM Timer (PWM)
9.2
Input/Output Pins
Table 9.1 shows the PWM output pins. Table 9.1
Name PWM output 15 to 8 ExPWM output 15 to 12
Pin Configuration
Abbreviation PW15 to PW8 ExPW15 to ExPW12 I/O Output Function PWM timer pulse output 15 to 8 A pin for outputting is selected among PWn and ExPWn. (n = 15 to 12) For details, section 8.17.1, Port Control Register 0 (PTCNT0).
9.3
Register Descriptions
The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see section 3.2.3, Serial Timer Control Register (STCR). * * * * * PWM register select (PWSL) PWM data registers 15 to 8 (PWDR15 to PWDR8) PWM data polarity register B (PWDPRB) PWM output enable register B (PWOERB) Peripheral clock select register (PCSR)
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Section 9 8-Bit PWM Timer (PWM)
9.3.1
PWM Register Select (PWSL)
PWSL is used to select the input clock and the PWM data register.
Bit 7 6 Bit Name PWCKE PWCKS Initial Value 0 0 R/W R/W R/W Description PWM Clock Enable PWM Clock Select These bits, together with bits PWCKB and PWCKA in PCSR, select the internal clock input to TCNT in the PWM. For details, see table 9.2. The resolution, PWM conversion period, and carrier frequency depend on the selected internal clock, and can be obtained from the following equations. Resolution (minimum pulse width) = 1/internal clock frequency PWM conversion period = resolution x 256 Carrier frequency = 16/PWM conversion period With a 20 MHz system clock (), the resolution, PWM conversion period, and carrier frequency are as shown in table 9.3. 5 4 3 2 1 0 -- -- RS3 RS2 RS1 RS0 1 0 0 0 0 0 R R R/W R/W R/W R/W Reserved Always read as 1 and cannot be modified. Reserved Always read as 0 and cannot be modified. Register Select These bits select the PWM data register. 0xxx: No effect on operation 1000: PWDR8 selected 1001: PWDR9 selected 1010: PWDR10 selected 1011: PWDR11 selected 1100: PWDR12 selected 1101: PWDR13 selected 1110: PWDR14 selected 1111: PWDR15 selected [Legend] x: Don't care.
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Section 9 8-Bit PWM Timer (PWM)
Table 9.2
Internal Clock Selection
PCSR PWCKB -- -- 0 PWCKA -- -- 0 1 1 0 1 Description Clock input is disabled (system clock) is selected /2 is selected /4 is selected /8 is selected /16 is selected (Initial value)
PWSL PWCKE 0 1 PWCKS -- 0 1
Table 9.3
Resolution, PWM Conversion Period, and Carrier Frequency when = 20 MHz
Resolution 50 ns 100 ns 200 ns 400 ns 800 ns PWM Conversion Period 1.28 s 25.6 s 51.2 s 102.4 s 204.8 s Carrier Frequency 1250 kHz 625 kHz 312.5 kHz 156.3 kHz 78.1 kHz
Internal Clock Frequency /2 /4 /8 /16
9.3.2
PWM Data Registers 15 to 8 (PWDR15 to PWDR8)
PWDR are 8-bit readable/writable registers. The PWM has eight PWM data registers. Each PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The lower four bits specify how many extra pulses are to be added within the conversion period comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios within the conversion period. For 256/256 (100%) output, port output should be used.
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Section 9 8-Bit PWM Timer (PWM)
9.3.3
PWM Data Polarity Register B (PWDPRB)
PWDPR selects the PWM output phase. * PWDPRB
Bit 7 6 5 4 3 2 1 0 Bit Name OS15 OS14 OS13 OS12 OS11 OS10 OS9 OS8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Select 15 to 8 These bits select the PWM output phase. Bits OS15 to OS8 correspond to outputs PW15 to PW8. 0: PWM direct output (PWDR value corresponds to high width of output) 1: PWM inverted output (PWDR value corresponds to low width of output)
9.3.4
PWM Output Enable Register B (PWOERB)
PWOER switches between PWM output and port output. * PWOERB
Bit 7 6 5 4 3 2 1 0 Bit Name OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Enable 15 to 8 These bits, together with P2DDR, specify the P2n/PWm pin state. Bits OE15 to OE8 correspond to outputs PW15 to PW8. P2nDDR OEn: Pin state 0x: Port input 10: Port output or PWM 256/256 output 11: PWM output (0 to 255/256 output) [Legend] x: Don't care Note: n = 7 to 0 m = 15 to 8
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Section 9 8-Bit PWM Timer (PWM)
To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set to port output. DR data is output when the corresponding pin is used as port output. A value corresponding to PWM 256/256 output is determined by the OS bit, so the value should have been set to DR beforehand. 9.3.5 Peripheral Clock Select Register (PCSR)
PCSR selects the PWM input clock.
Bit 7 6 5 4 3 2 1 Bit Name PWCKXB PWCKXA PWCKB PWCKA Initial Value 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PWM Clock Select B, A Together with bits PWCKE and PWCKS in PWSL, these bits select the internal clock input to the clock counter in the PWM. For details, see table 9.2. See section 10.3.4, Peripheral Clock Select Register (PCSR). Description See section 10.3.4, Peripheral Clock Select Register (PCSR).
0
PWCKXC
0
R/W
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Section 9 8-Bit PWM Timer (PWM)
9.4
Operation
The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 9.4 shows the duty cycles of the basic pulse. Table 9.4 Duty Cycle of Basic Pulse
Basic Pulse Waveform (Internal) H: 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 L:
Upper 4 Bits B'0000 B'0001 B'0010 B'0011 B'0100 B'0101 B'0110 B'0111 B'1000 B'1001 B'1010 B'1011 B'1100 B'1101 B'1110 B'1111
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Section 9 8-Bit PWM Timer (PWM)
The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the rising edge of a basic pulse. When the upper four bits of PWDR are B'0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. Table 9.5 shows the positions of the additional pulses added to the basic pulses, and figure 9.2 shows an example of additional pulse timing. Table 9.5 Position of Pulses Added to Basic Pulses
Basic Pulse No. Lower 4 Bits 0 B'0000 B'0001 B'0010 B'0011 B'0100 B'0101 B'0110 B'0111 B'1000 B'1001 B'1010 B'1011 B'1100 B'1101 B'1110 B'1111 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
No additional pulse Resolution width With additional pulse Additioal pulse
Figure 9.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000)
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Section 9 8-Bit PWM Timer (PWM)
9.4.1
PWM Setting Example
1-conversion cycle
PWDR setting example H'7F
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Duty cycle 127/256
Basic waveform 112 pulses
Additiona pulse 15 pulses
H'80
128/256
128 pulses
0 pulses
H'81
129/256
128 pulses
1 pulse
H'82
130/256
128 pulses
2 pulses
: Pulse added Combination of the basic pulse and added pulse outputs 0/256 to 255/256 of dudty cycle as low ripple wave form.
Figure 9.3 Example of PWM Setting 9.4.2 Diagram of PWM Used as D/A Converter
Figure 9.4 shows the diagram example when using the PWM pulse as the D/A converter. Analog signal with low ripple can be generated by connecting the low pass filter.
Resistor : 120 k Capacitor : 0.1 F This LSI
Low pass filter
Reference value
Figure 9.4 Example when PWM is Used as D/A Converter
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Section 9 8-Bit PWM Timer (PWM)
9.5
9.5.1
Usage Notes
Module Stop Mode Setting
PWM operation can be enabled or disabled by the module stop control register. In the initial state, PWM operation is disabled. Access to PWM registers is enabled when module stop mode is cancelled. For details, see section 24, Power-Down Modes.
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Section 9 8-Bit PWM Timer (PWM)
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Section 10 14-Bit PWM Timer (PWMX)
Section 10 14-Bit PWM Timer (PWMX)
This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
10.1
Features
* Division of pulse into multiple base cycles to reduce ripple * Eight resolution settings The resolution can be set to 1, 2, 64, 128, 256, 1024, 4096, or 16384 system clock cycles. * Two base cycle settings The base cycle can be set equal to T x 64 or T x 256, where T is the resolution. * Sixteen operation clocks (by combination of eight resolution settings and two base cycle settings) Figure 10.1 shows a block diagram of the PWM (D/A) module.
Internal clock /2, /64, /128, /256, /1024, /4096, /16384 Clock Base cycle compare match A PWX0 PWX1
Fine-adjustment pulse addition A
Internal data bus
PCSR
Select clock
Bus interface
Comparator A Comparator B
DADRA DADRB
Base cycle compare match B
Fine-adjustment pulse addition B
Control logic Base cycle overflow DACNT
DACR [Legend] DACR: PWMX D/A control register (6 bits) DADRA: PWMX D/A data register A (15 bits) DADRB: PWMX D/A data register B (15 bits) DACNT: PWMX D/A counter (14 bits) PCSR: Peripheral clock select register Module data bus
Figure 10.1 PWMX (D/A) Block Diagram
PWM1420A_000020020300
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Section 10 14-Bit PWM Timer (PWMX)
10.2
Input/Output Pins
Table 10.1 lists the PWMX (D/A) module input and output pins. Table 10.1 Pin Configuration
Name PWMX output pin 0 PWMX output pin 1 Abbreviation I/O PWX0 PWX1 Output Output Function PWMX output of channel A PWMX output of channel B
10.3
Register Descriptions
The PWMX (D/A) module has the following registers. The PWMX (D/A) registers are assigned to the same addresses with other registers. The registers are selected by the IICE bit in the serial timer control register (STCR). For details on the module stop control register, see section 24.1.3, Module Stop Control Register H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA). * * * * * PWMX (D/A) counter (DACNT) PWMX (D/A) data register A (DADRA) PWMX (D/A) data register B (DADRB) PWMX (D/A) control register (DACR) Peripheral clock select register (PCSR)
Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or DADRB.
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Section 10 14-Bit PWM Timer (PWMX)
10.3.1
PWMX (D/A) Counter (DACNT)
DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper 2-bit counter. As DACNT is 16 bits, data transfer between the CPU is performed through the temporary register (TEMP). For details, see section 10.4, Bus Master Interface.
DACNTH Bit (CPU): Bit (counter): 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 7 8 6 9 5 10 DACNTL 4 11 3 12 2 13 1 0 REGS
* DACNTH
Bit 7 to 0 Bit Name Initial Value R/W R/W Description Upper Up-Counter
DACNT7 to All 0 DACNT0
* DACNTL
Bit 7 to 2 1 0 Bit Name Initial Value R/W R/W R R/W Description Lower Up-Counter Reserved Always read as 1 and cannot be modified. REGS 1 Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed
DACNT 8 to All 0 DACNT 13 1
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Section 10 14-Bit PWM Timer (PWMX)
10.3.2
PWMX (D/A) Data Registers A and B (DADRA and DADRB)
DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. As DACNT is 16 bits, data transfer between the CPU is performed through the temporary register (TEMP). For details, see section 10.4, Bus Master Interface. * DADRA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Carrier Frequency Select 0: Base cycle = resolution (T) x 64 The range of DA13 to DA0: H'0100 to H'3FFF 1: Base cycle = resolution (T) x 256 The range of DA13 to DA0: H'0040 to H'3FFF 0 1 R Reserved Always read as 1 and cannot be modified. Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by fixing DA0 and DA1 to 0. The two data bits are not compared with DACNT12 and DACNT13 of DACNT.
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Section 10 14-Bit PWM Timer (PWMX)
* DADRB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Carrier Frequency Select 0: Base cycle = resolution (T) x 64 DA13 to DA0 range = H'0100 to H'3FFF 1: Base cycle = resolution (T) x 256 DA13 to DA0 range = H'0040 to H'3FFF 0 REGS 1 R/W Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by fixing DA0 and DA1 to 0. The two data bits are not compared with DACNT12 and DACNT13 of DACNT.
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Section 10 14-Bit PWM Timer (PWMX)
10.3.3
PWMX (D/A) Control Register (DACR)
DACR enables the PWM outputs, and selects the output phase and operating speed.
Bit 7 6 Bit Name PWME Initial Value 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. PWMX Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H0003 5 4 3 OEB 1 1 0 R R R/W Reserved Always read as 1 and cannot be modified. Output Enable B Enables or disables output on PWMX (D/A) channel B. 0: PWMX (D/A) channel B output (at the PWX1 output pin) is disabled 1: PWMX (D/A) channel B output (at the PWX1 output pin) is enabled 2 OEA 0 R/W Output Enable A Enables or disables output on PWMX (D/A) channel A. 0: PWMX (D/A) channel A output (at the PWX0 output pin) is disabled 1: PWMX (D/A) channel A output (at the PWX0 output pin) is enabled 1 OS 0 R/W Output Select Selects the phase of the PWMX (D/A) output. 0: Direct PWMX (D/A) output 1: Inverted PWMX (D/A) output 0 CKS 0 R/W Clock Select Selects the PWMX (D/A) resolution. Eight kinds of resolution can be selected. 0: Operates at resolution (T) = system clock cycle time (tcyc) 1: Operates at resolution (T) = system clock cycle time (tcyc) x 2, x 64, x 128, x 256, x 1024, x 4096, and x 16384.
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Section 10 14-Bit PWM Timer (PWMX)
10.3.4
Peripheral Clock Select Register (PCSR)
PCSR and the CKS bit of DACR select the operating speed.
Bit 7 6 5 4 Bit Name PWCKXB PWCKXA Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. PWMX clock select These bits select a clock cycle with the CKS bit of DACR of PWMX being 1. See table 10.2. 3 2 1 0 PWCKB PWCKA PWCKXC 0 0 0 0 R/W R/W R/W R/W Reserved The initial value should not be changed. PWM clock select B, A See section 9.3.5, Peripheral Clock Select Register (PCSR). PWMX clock select This bit selects a clock cycle with the CKS bit of DACR of PWMX being 1. See table 10.2.
Table 10.2 Clock Select of PWMX
PWCKXC 0 0 0 0 1 1 1 1 PWCKXB 0 0 1 1 0 0 1 1 PWCKXA 0 1 0 1 0 1 0 1 Resolution (T) Operates on the system clock cycle (tcyc) x 2 Operates on the system clock cycle (tcyc) x 64 Operates on the system clock cycle (tcyc) x 128 Operates on the system clock cycle (tcyc) x 256 Operates on the system clock cycle (tcyc) x 1024 Operates on the system clock cycle (tcyc) x 4096 Operates on the system clock cycle (tcyc) x 16384 Setting prohibited
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Section 10 14-Bit PWM Timer (PWMX)
10.4
Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. * Write When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the lower byte is written to, the lower-byte write data and TEMP value are combined, and the combined 16-bit value is written in the register. * Read When the upper byte is read from, the upper-byte value is transferred to the CPU and the lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lowerbyte value in TEMP is transferred to the CPU. These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper byte should always be accessed before the lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction cannot be used to access these registers. Example 1: Write to DACNT
MOV.W R0, @DACNT ; Write R0 contents to DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0 ; Copy contents of DADRA to R0
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Section 10 14-Bit PWM Timer (PWMX)
Table 10.3 Reading/Writing to 16-bit Registers
Read Register DADRA, DADRB DACNT Word O O Byte O x Word O O Write Byte x x
[Legend] O: Enabled access. Word-unit access includes accessing byte sequentially, first upper byte, and then lower byte. x: The result of the access in the unit cannot be guaranteed.
(a) Write to upper byte Module data bus Bus interface
CPU [H'AA] Upper byte
TEMP [H'AA]
DACNTH [ ] (b) Write to lower byte
DACNTL [ ]
CPU [H'57] Lower byte
Module data bus Bus interface
TEMP [H'AA]
DACNTH [H'AA]
DACNTL [H'57]
Figure 10.2 (1) DACNT Access Operation (1) [CPU DACNT(H'AA57) Writing]
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Section 10 14-Bit PWM Timer (PWMX)
(a) Read upper byte Module data bus Bus interface
CPU [H'AA] Upper byte
TEMP [H'AA]
DACNTH [ ] (b) Read lower byte
DACNTL [ ]
CPU [H'57] Lower byte
Module data bus Bus interface
TEMP [H'AA]
DACNTH [H'AA]
DACNTL [H'57]
Figure 10.2 (2) DACNT Access Operation (2) [DACNT CPU(H'AA57) Reading]
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Section 10 14-Bit PWM Timer (PWMX)
10.5
Operation
A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. DA13 to DA0 in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 10.4 and 10.5 show the types of waveform output available.
1 conversion cycle (T x 214 (= 16384)) tf Base cycle (T x 64 or T x 256)
tL
T: Resolution TL = tLn (OS = 0)
n=1 m
(When CFS = 0, m = 256 When CFS = 1, m = 64)
Figure 10.3 PWMX (D/A) Operation Table 10.4 summarizes the relationships between the CKS and CFS bit settings and the resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DA13 to DA0 in DADR contain at least a certain minimum value. The relationship between the OS bit and the output waveform is shown in figures 10.4 and 10.5.
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Section 10 14-Bit PWM Timer (PWMX)
Table 10.4 Settings and Operation (Examples when = 20 MHz)
PCSR PWCKX0 PWCKX1 C B A Resolution T CK (s) 0 0.05 Base CFS Cycle 0 3.2 (s) /312.5kHz 1 12.8 (s) () 0 0 0 1 0.1 0 /78.1kHz 6.4 (s) /156.2kHz 1 25.6 (s) (/2) 0 0 1 1 3.2 0 /39.1kHz 204.8 (s) /4.9kHz 1 819.2 (s) (/64) 0 1 0 1 6.4 0 /1.2kHz 409.6 (s) /2.4kHz 1 1638.4 (s) (/128) /610.4kHz 104.9 (ms) 52.4 (ms) 1.64 (ms) Conversion Cycle 819.2 (s) TL/TH (OS = 0/OS = 1) Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Accuracy DA3 DA2 DA1 (Bits) 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA0 Bit Data Conversion Cycle* 819.2 s 204.8 s 51.2 s 819.2 s 204.8 s 51.2 s 1638.4 s 409.6 s 102.4 s 1638.4 s 409.6 s 102.4 s 52.4 ms 13.1 ms 3.3 ms 52.4 ms 13.1 ms 3.3 ms 104.9 ms 26.2 ms 6.6 ms 104.9 ms 26.2 ms 6.6 ms Fixed DADR Bits
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Section 10 14-Bit PWM Timer (PWMX)
PCSR PWCKX0 PWCKX1 C 0 B 1 A 1 Resolution T CKS (s) 1 12.8 Base CFS Cycle 0 819.2 (s) /1.2kHz 1 3276.8 (s) (/256) /305.2kH z 1 0 0 1 51.2 0 3.3 (ms) /305.2Hz 1 13.1 (ms) (/1024) 1 0 1 1 204.8 0 /76.3Hz 13.1 (ms) /76.3Hz 1 52.4 (ms) (/4096) 1 1 0 1 496.48 0 /19.1Hz 52.4 (ms) /19.1Hz 1 209.7 (ms) (/16384) 1 1 1 1 Setting prohibited /4.8Hz 8.13 (s) 2.03 (s) 838.9 (ms) Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Conversion Cycle 209.7 (ms) TL/TH (OS = 0/OS = 1) Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF
Fixed DADR Bits Bit Data Accuracy DA3 DA2 DA1 DA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Bits) 14 12 10 14 12 10 0 0 0 0 0 0 0 0 Conversion Cycle* 209.7 ms 52.4 ms 13.1 ms 209.7 ms 52.4 ms 13.1 ms
14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
838.9 ms 209.7 ms 52.4 ms 838.9 ms 209.7 ms 52.4 ms 3.4 s 838.9 ms 209.7 ms 3.4 s 838.9 ms 209.7 ms 13.4 s 3.4 s 838.9 ms 13.4 s 3.4 s 838.9 ms
Note:
*
Indicates the conversion cycle when specific DA3 to DA0 bits are fixed.
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Section 10 14-Bit PWM Timer (PWMX)
1 conversion cycle tf1 tf2 tf255 tf256
tL1
tL2
tL3
tL255
tL256
tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tL1 + tL2 + tL3+ *** + tL255 + tL256 = TL a. CFS = 0 [base cycle = resolution (T) x 64]
1 conversion cycle tf1 tf2 tf63 tf64
tL1
tL2
tL3
tL63
tL64
tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tL1 + tL2 + tL3 + *** + tL63 + tL64 = TL b. CFS = 1 [base cycle = resolution (T) x 256]
Figure 10.4 Output Waveform (OS = 0, DADR corresponds to TL)
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Section 10 14-Bit PWM Timer (PWMX)
1 conversion cycle tf1 tf2 tf255 tf256
tH1
tH2
tH3
tH255
tH256
tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tH1 + tH2 + tH3 + *** + tH255 + tH256 = TH a. CFS = 0 [base cycle = resolution (T) x 64]
1 conversion cycle tf1 tf2 tf63 tf64
tH1
tH2
tH3
tH63
tH64
tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tH1 + tH2 + tH3 + *** + tH63 + tH64 = TH b. CFS = 1 [base cycle = resolution (T) x 256]
Figure 10.5 Output Waveform (OS = 1, DADR corresponds to TH) An example of the additional pulses when CFS = 1 (base cycle = resolution (T) x 256) and OS = 1 (inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0) determine the locations of the additional pulses as shown in figure 10.6. Table 10.5 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
CFS 1 1
Duty cycle of base pulse
Location of additional pulses
Figure 10.6 D/A Data Register Configuration when CFS = 1 In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in figure 10.7. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of the base pulse duty cycle is 2/256 x (T).
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Section 10 14-Bit PWM Timer (PWMX)
Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the location of base pulse No. 63 according to table 10.5. Thus, an additional pulse of 1/256 x (T) is to be added to the base pulse.
1 conversion cycle Base cycle No. 0 Base cycle No. 1 Base cycle No. 63
Base pulse High width: 2/256 x (T) Base pulse 2/256 x (T)
Additional pulse output location Additional pulse 1/256 x (T)
Figure 10.7 Output Waveform when DADR = H'0207 (OS = 1) However, when CFS = 0 (base cycle = resolution (T) x 64), the duty cycle of the base pulse is determined by the upper six bits and the locations of the additional pulses by the subsequent eight bits with a method similar to as above.
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Base pulse No.
Table 10.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)
Lower 6 bits
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Section 10 14-Bit PWM Timer (PWMX)
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REJ09B0098-0300
Section 10 14-Bit PWM Timer (PWMX)
10.6
10.6.1
Usage Notes
Module Stop Mode Setting
PWMX operation can be enabled or disabled by using the module stop control register. In the initial state, PWMX operation is disabled. Register access is enabled by clearing module stop mode. For details, see section 24, Power-Down Modes.
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Section 11 16-Bit Free-Running Timer (FRT)
Section 11 16-Bit Free-Running Timer (FRT)
This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods.
11.1
Features
* Selection of four clock sources One of the three internal clocks (/2, /8, or /32), or an external clock input can be selected (enabling use as an external event counter). * Two independent comparators Two independent waveforms can be output. * Four independent input capture channels The rising or falling edge can be selected. Buffer modes can be specified. * Counter clearing The free-running counters can be cleared on compare-match A. * Seven independent interrupts Two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. * Special functions provided by automatic addition function The contents of OCRAR and OCRAF can be added to the contents of OCRA automatically, enabling a periodic waveform to be generated without software intervention. The contents of ICRD can be added automatically to the contents of OCRDM x 2, enabling input capture operations in this interval to be restricted. Figure 11.1 shows a block diagram of the FRT.
TIM8FR1A_000020020300
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Section 11 16-Bit Free-Running Timer (FRT)
External clock
Internal clock
FTCI Clock selector
/2 /8 /32
Clock
OCRAR/F
OCRA
Compare-match A
Bus interface
FTOA FTOB FTIA FTIB FTIC FTID
Input capture Overflow
Module data bus
Comparator A
Internal data bus
FRC
Clear Compare-match B
Control logic
Comparator B
OCRB
ICRA ICRB ICRC ICRD
Comparator M
Compare-match M
x1 x2
OCRDM TCSR TIER TCR TOCR
ICIA ICIB ICIC ICID OCIA OCIB FOVI
Interrupt signal
[Legend] OCRA, OCRB: Output compare register A, B (16-bit) OCRAR,OCRAF: Output compare register AR, AF (16-bit) OCRDM: Output compare register DM (16-bit) FRC: Free-running counter (16-bit) ICRA to ICRD: Input capture registers A to D (16-bit) TCSR: Timer control/status register (8-bit) TIER: Timer interrupt enable register (8-bit) TCR: Timer control register (8-bit) TOCR: Timer output compare control register (8-bit)
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer
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Section 11 16-Bit Free-Running Timer (FRT)
11.2
Input/Output Pins
Table 11.1 lists the FRT input and output pins. Table 11.1 Pin Configuration
Name Counter clock input pin Output compare A output pin Output compare B output pin Input capture A input pin Input capture B input pin Input capture C input pin Input capture D input pin Abbreviation FTCI FTOA FTOB FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function FRC counter clock input Output compare A output Output compare B output Input capture A input Input capture B input Input capture C input Input capture D input
11.3
Register Descriptions
The FRT has the following registers. * * * * * * * * * * * * * * Free-running counter (FRC) Output compare register A (OCRA) Output compare register B (OCRB) Input capture register A (ICRA) Input capture register B (ICRB) Input capture register C (ICRC) Input capture register D (ICRD) Output compare register AR (OCRAR) Output compare register AF (OCRAF) Output compare register DM (OCRDM) Timer interrupt enable register (TIER) Timer control/status register (TCSR) Timer control register (TCR) Timer output compare control register (TOCR)
Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS bit in TOCR. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and OCRDM. Register selection is controlled by the ICRS bit in TOCR.
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Section 11 16-Bit Free-Running Timer (FRT)
11.3.1
Free-Running Counter (FRC)
FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot be accessed in 8-bit units. FRC is initialized to H'0000. 11.3.2 Output Compare Registers A and B (OCRA and OCRB)
The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit readable/writable register whose contents are continually compared with the value in FRC. When a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is set to 1 in TCSR. If the OEA or OEB bit in TOCR is set to 1, when the OCR and FRC values match, the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output compare output pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCR should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCR is initialized to H'FFFF. 11.3.3 Input Capture Registers A to D (ICRA to ICRD)
The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is detected, the current FRC value is transferred to the corresponding input capture register (ICRA to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to 1. The FRC contents are transferred to ICR regardless of the value of ICF. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR. ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of buffer enable bits A and B (BUFEA and BUFEB) in TCR. For example, if an input capture occurs when ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then transferred to the buffer register ICRC. When IEDGA and IEDGC bits in TCR are set to different values, both rising and falling edges can be specified as the change of the external input signal. When IEDGA and IEDGC are set to the same value, either rising edge or falling edge can be specified as the change of the external input signal. To ensure input capture, the input capture pulse width should be at least 1.5 system clocks () for a single edge. When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clocks ().
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Section 11 16-Bit Free-Running Timer (FRT)
ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is initialized to H'0000. 11.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF)
OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the 1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added. The operation due to compare-match A varies according to whether the compare-match follows addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A following addition of OCRAR. When using the OCRA automatic addition function, do not select internal clock /2 as the FRC input clock together with a set value of H'0001 or less for OCRAR (or OCRAF). OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRAR and OCRAF are initialized to H'FFFF. 11.3.5 Output Compare Register DM (OCRDM)
OCRDM is a 16-bit readable/writable register in which the upper eight bits are fixed at H'00. When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, the operation of ICRD is changed to include the use of OCRDM. The point at which input capture D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to the contents of ICRD, and the result is compared with the FRC value. The point at which the values match is taken as the end of the mask interval. New input capture D events are disabled during the mask interval. A mask interval is not generated when the contents of OCRDM are H'0000 while the ICRDMS bit is set to 1. OCRDM should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRDM is initialized to H'0000.
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Section 11 16-Bit Free-Running Timer (FRT)
11.3.6
Timer Interrupt Enable Register (TIER)
TIER enables and disables interrupt requests.
Bit 7 Bit Name ICIAE Initial Value 0 R/W R/W Description Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1. 0: ICIA requested by ICFA is disabled 1: ICIA requested by ICFA is enabled 6 ICIBE 0 R/W Input Capture Interrupt B Enable Selects whether to enable input capture interrupt B request (ICIB) when input capture flag B (ICFB) in TCSR is set to 1. 0: ICIB requested by ICFB is disabled 1: ICIB requested by ICFB is enabled 5 ICICE 0 R/W Input Capture Interrupt C Enable Selects whether to enable input capture interrupt C request (ICIC) when input capture flag C (ICFC) in TCSR is set to 1. 0: ICIC requested by ICFC is disabled 1: ICIC requested by ICFC is enabled 4 ICIDE 0 R/W Input Capture Interrupt D Enable Selects whether to enable input capture interrupt D request (ICID) when input capture flag D (ICFD) in TCSR is set to 1. 0: ICID requested by ICFD is disabled 1: ICID requested by ICFD is enabled 3 OCIAE 0 R/W Output Compare Interrupt A Enable Selects whether to enable output compare interrupt A request (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. 0: OCIA requested by OCFA is disabled 1: OCIA requested by OCFA is enabled
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Section 11 16-Bit Free-Running Timer (FRT)
Bit 2
Bit Name OCIBE
Initial Value 0
R/W R/W
Description Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled
1
OVIE
0
R/W
Timer Overflow Interrupt Enable Selects whether to enable a free-running timer overflow request interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. 0: FOVI requested by OVF is disabled 1: FOVI requested by OVF is enabled
0
1
R
Reserved This bit is always read as 1 and cannot be modified.
11.3.7
Timer Control/Status Register (TCSR)
TCSR is used for counter clear selection and control of interrupt request signals.
Bit 7 Bit Name ICFA Initial Value 0 R/W Description
R/(W)* Input Capture Flag A This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been transferred to ICRA. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRA [Clearing condition] Read ICFA when ICFA = 1, then write 0 to ICFA
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Section 11 16-Bit Free-Running Timer (FRT)
Bit 6
Bit Name ICFB
Initial Value 0
R/W
Description
R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB. [Setting condition] When an input capture signal causes the FRC value to be transferred to ICRB [Clearing condition] Read ICFB when ICFB = 1, then write 0 to ICFB
5
ICFC
0
R/(W)* Input Capture Flag C This status flag indicates that the FRC value has been transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of an input capture signal specified by the IEDGC bit at the FTIC input pin, ICFC is set but data is not transferred to ICRC. In buffer operation, ICFC can be used as an external interrupt signal by setting the ICICE bit to 1. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFC when ICFC = 1, then write 0 to ICFC
4
ICFD
0
R/(W)* Input Capture Flag D This status flag indicates that the FRC value has been transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of an input capture signal specified by the IEDGD bit at the FTID input pin, ICFD is set but data is not transferred to ICRD. In buffer operation, ICFD can be used as an external interrupt signal by setting the ICIDE bit to 1. [Setting condition] When an input capture signal is received [Clearing condition] Read ICFD when ICFD = 1, then write 0 to ICFD
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Section 11 16-Bit Free-Running Timer (FRT)
Bit 3
Bit Name OCFA
Initial Value 0
R/W
Description
R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA
2
OCFB
0
R/(W)* Output Compare Flag B This status flag indicates that the FRC value matches the OCRB value. [Setting condition] When FRC = OCRB [Clearing condition] Read OCFB when OCFB = 1, then write 0 to OCFB
1
OVF
0
R/(W)* Overflow Flag This status flag indicates that the FRC has overflowed. [Setting condition] When FRC overflows (changes from H'FFFF to H'0000) [Clearing condition] Read OVF when OVF = 1, then write 0 to OVF
0
CCLRA
0
R/W
Counter Clear A This bit selects whether the FRC is to be cleared at compare-match A (when the FRC and OCRA values match). 0: FRC clearing is disabled 1: FRC is cleared at compare-match A
Note:
*
Only 0 can be written to clear the flag.
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Section 11 16-Bit Free-Running Timer (FRT)
11.3.8
Timer Control Register (TCR)
TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source.
Bit 7 Bit Name IEDGA Initial Value 0 R/W R/W Description Input Edge Select A Selects the rising or falling edge of the input capture A signal (FTIA). 0: Capture on the falling edge of FTIA 1: Capture on the rising edge of FTIA 6 IEDGB 0 R/W Input Edge Select B Selects the rising or falling edge of the input capture B signal (FTIB). 0: Capture on the falling edge of FTIB 1: Capture on the rising edge of FTIB 5 IEDGC 0 R/W Input Edge Select C Selects the rising or falling edge of the input capture C signal (FTIC). 0: Capture on the falling edge of FTIC 1: Capture on the rising edge of FTIC 4 IEDGD 0 R/W Input Edge Select D Selects the rising or falling edge of the input capture D signal (FTID). 0: Capture on the falling edge of FTID 1: Capture on the rising edge of FTID 3 BUFEA 0 R/W Buffer Enable A Selects whether ICRC is to be used as a buffer register for ICRA. 0: ICRC is not used as a buffer register for ICRA 1: ICRC is used as a buffer register for ICRA 2 BUFEB 0 R/W Buffer Enable B Selects whether ICRD is to be used as a buffer register for ICRB. 0: ICRD is not used as a buffer register for ICRB 1: ICRD is used as a buffer register for ICRB
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Section 11 16-Bit Free-Running Timer (FRT)
Bit 1 0
Bit Name CKS1 CKS0
Initial Value 0 0
R/W R/W
Description Clock Select 1, 0 Select clock source for FRC. 00: /2 internal clock source 01: /8 internal clock source 10: /32 internal clock source 11: External clock source (counting at FTCI rising edge)
11.3.9
Timer Output Compare Control Register (TOCR)
TOCR enables output from the output compare pins, selects the output levels, switches access between output compare registers A and B, controls the ICRD and OCRA operating modes, and switches access to input capture registers A, B, and C.
Bit 7 Bit Name ICRDMS Initial Value 0 R/W R/W Description Input Capture D Mode Select Specifies whether ICRD is used in the normal operating mode or in the operating mode using OCRDM. 0: The normal operating mode is specified for ICRD 1: The operating mode using OCRDM is specified for ICRD 6 OCRAMS 0 R/W Output Compare A Mode Select Specifies whether OCRA is used in the normal operating mode or in the operating mode using OCRAR and OCRAF. 0: The normal operating mode is specified for OCRA 1: The operating mode using OCRAR and OCRAF is specified for OCRA 5 ICRS 0 R/W Input Capture Register Select The same addresses are shared by ICRA and OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which registers are selected when the shared addresses are read from or written to. The operation of ICRA, ICRB, and ICRC is not affected. 0: ICRA, ICRB, and ICRC are selected 1: OCRAR, OCRAF, and OCRDM are selected
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Section 11 16-Bit Free-Running Timer (FRT)
Bit 4
Bit Name OCRS
Initial Value 0
R/W R/W
Description Output Compare Register Select OCRA and OCRB share the same address. The OCRS determines which register is selected when the shared address is read from or written to. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected
3
OEA
0
R/W
Output Enable A Enables or disables output of the output compare A output pin (FTOA). 0: Output compare A output is disabled 1: Output compare A output is enabled
2
OEB
0
R/W
Output Enable B Enables or disables output of the output compare B output pin (FTOB). 0: Output compare B output is disabled 1: Output compare B output is enabled
1
OLVLA
0
R/W
Output Level A Selects the level to be output at the output compare A output pin (FTOA) in response to compare-match A (signal indicating a match between the FRC and OCRA values). When the OCRAMS bit is 1, this bit is ignored. 0: 0 is output at compare-match A 1: 1 is output at compare-match A
0
OLVLB
0
R/W
Output Level B Selects the level to be output at the output compare B output pin (FTOB) in response to compare-match B (signal indicating a match between the FRC and OCRB values). 0: 0 is output at compare-match B 1: 1 is output at compare-match B
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Section 11 16-Bit Free-Running Timer (FRT)
11.4
11.4.1
Operation
Pulse Output
Figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software.
FRC H'FFFF Counter clear OCRA
OCRB
H'0000
FTOA
FTOB
Figure 11.2 Example of Pulse Output
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Section 11 16-Bit Free-Running Timer (FRT)
11.5
11.5.1
Operation Timing
FRC Increment Timing
Figure 11.3 shows the FRC increment timing with an internal clock source. Figure 11.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks ().
Internal clock
FRC input clock
FRC
N-1
N
N+1
Figure 11.3 Increment Timing with Internal Clock Source
External clock input pin
FRC input clock
FRC
N
N+1
Figure 11.4 Increment Timing with External Clock Source
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Section 11 16-Bit Free-Running Timer (FRT)
11.5.2
Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare output pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A.
FRC
N
N+1
N
N+1
OCRA
N
N
Compare-match A signal Clear* OLVLA
Output compare A output pin FTOA Note : * Indicates instruction execution by software.
Figure 11.5 Timing of Output Compare A Output 11.5.3 FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this operation.
Compare-match A signal
FRC
N
H'0000
Figure 11.6 Clearing of FRC by Compare-Match A Signal
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Section 11 16-Bit Free-Running Timer (FRT)
11.5.4
Input Capture Input Timing
The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is selected.
Input capture input pin Input capture signal
Figure 11.7 Input Capture Input Signal Timing (Usual Case) If ICRA to ICRD are read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (). Figure 11.8 shows the timing for this case.
Read cycle of ICRA to ICRD T1 T2
Input capture input pin
Input capture signal
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read)
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Section 11 16-Bit Free-Running Timer (FRT)
11.5.5
Buffered Input Capture Input Timing
ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 11.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
FTIA
Input capture signal
FRC
n
n+1
N
N+1
ICRA
M
n
n
N
ICRC
m
M
M
n
Figure 11.9 Buffered Input Capture Timing Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if either set of two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture input signal arrives, input capture is delayed by one system clock (). Figure 11.10 shows the timing when BUFEA = 1.
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Section 11 16-Bit Free-Running Timer (FRT)
CPU read cycle of ICRA or ICRC T1 T2
FTIA
Input capture signal
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) 11.5.6 Timing of Input Capture Flag (ICF) Setting
The input capture flag, ICFA to ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA to ICRD). Figure 11.11 shows the timing of setting the ICFA to ICFD flag.
Input capture signal
ICFA to ICFD
FRC
N
ICRA to ICRD
N
Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting
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Section 11 16-Bit Free-Running Timer (FRT)
11.5.7
Timing of Output Compare Flag (OCF) setting
The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. When the FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next cycle of the clock source. Figure 11.12 shows the timing of setting the OCFA or OCFB flag.
FRC
N
N+1
OCRA, OCRB
N
Compare-match signal
OCFA, OCFB
Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting 11.5.8 Timing of FRC Overflow Flag Setting
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 11.13 shows the timing of setting the OVF flag.
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Section 11 16-Bit Free-Running Timer (FRT)
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 11.13 Timing of Overflow Flag (OVF) Setting 11.5.9 Automatic Addition Timing
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. Figure 11.14 shows the OCRA write timing.
FRC
N
N +1
OCRA
N
N+A
OCRAR, OCRAF
A
Compare-match signal
Figure 11.14 OCRA Automatic Addition Timing
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Section 11 16-Bit Free-Running Timer (FRT)
11.5.10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture signal is generated. The mask signal is set by the input capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match. Figure 11.15 shows the timing of setting the mask signal. Figure 11.16 shows the timing of clearing the mask signal.
Input capture signal
Input capture mask signal
Figure 11.15 Timing of Input Capture Mask Signal Setting
FRC
N
N+1
ICRD + OCRDM x 2
N
Compare-match signal
Input capture mask signal
Figure 11.16 Timing of Input Capture Mask Signal Clearing
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Section 11 16-Bit Free-Running Timer (FRT)
11.6
Interrupt Sources
The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 11.2 lists the sources and priorities of these interrupts. The ICIA, ICIB, OCIA, and OCIB interrupts can be used as the on-chip DTC activation sources. Table 11.2 FRT Interrupt Sources
Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI Interrupt Source Input capture of ICRA Input capture of ICRB Input capture of ICRC Input capture of ICRD Compare match of OCRA Compare match of OCRB Overflow of FRC Interrupt Flag ICFA ICFB ICFC ICFD OCFA OCFB OVF DTC Activation Enable Enable Disable Disable Enable Enable Disable Low Priority High
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Section 11 16-Bit Free-Running Timer (FRT)
11.7
11.7.1
Usage Notes
Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.17 shows the timing for this type of conflict.
Write cycle of FRC T1 T2
Address
FRC address
Internal write signal
Counter clear signal
FRC
N
H'0000
Figure 11.17 Conflict between FRC Write and Clear
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Section 11 16-Bit Free-Running Timer (FRT)
11.7.2
Conflict between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict.
Write cycle of FRC T1 T2
Address
FRC address
Internal write signal
FRC input clock
FRC
N
M
Write data
Figure 11.18 Conflict between FRC Write and Increment
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Section 11 16-Bit Free-Running Timer (FRT)
11.7.3
Conflict between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of conflict. If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of the automatic addition is not written to OCRA. Figure 11.20 shows the timing for this type of conflict.
Write cycle of OCR T1 T2
Address
OCR address
Internal write signal
FRC
N
N+1
OCR
N
M Write data
Compare-match signal Disabled
Figure 11.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Not Used)
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Section 11 16-Bit Free-Running Timer (FRT)
Address
OCRAR (OCRAF) address
Internal write signal
OCRAR (OCRAF)
Old data
New data
Compare-match signal
Disabled
FRC
N
N+1
OCR
N Automatic addition is not performed because compare-match signals are disabled.
Figure 11.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Used) 11.7.4 Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may source FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 11.3. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 11.3, the changeover is regarded as a falling edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock and external clock can also source FRC to increment.
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Section 11 16-Bit Free-Running Timer (FRT)
Table 11.3 Switching of Internal Clock and FRC Operation
Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low to low
No. 1
FRC Operation
Clock before switchover
Clock after switchover
FRC clock
FRC
N
N+1
CKS bit rewrite
2
Switching from low to high
Clock before switchover
Clock after switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
3
Switching from high to low
Clock before switchover
Clock after switchover * FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
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Section 11 16-Bit Free-Running Timer (FRT)
No. 4
Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to high
FRC Operation
Clock before switchover
Clock after switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
Note:
*
Generated on the assumption that the switchover is a falling edge; FRC is incremented.
11.7.5
Module Stop Mode Setting
FRT operation can be enabled or disabled by the module stop control register. In the initial state, FRT operation is disabled. Access to FRT registers is enabled when module stop mode is cancelled. For details, see section 24, Power-Down Modes.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Section 12 16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 12.1 and figure 12.1, respectively.
12.1
Features
* Maximum 8-pulse input/output * Selection of eight counter input clocks for channels 0 and 2, seven counter input clocks for channel 1 * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation Maximum of 7-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channel 0 * Phase counting mode settable independently for each of channels 1 and 2 * Fast access via internal 16-bit bus * 13 interrupt sources * Automatic transfer of register data * A/D converter conversion start trigger can be generated
TIMTPU2A_010020020100
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Section 12 16-Bit Timer Pulse Unit (TPU)
Clock input Internal clock:
/1 /4 /16 /64 /256 /1024 TCLKA TCLKB TCLKC TCLKD
TSYR
Control logic
Internal data bus
Common
Bus interface
TMDR
Channel 2
TSR
TSTR
External clock:
A/D converter convertion start signal
TGRA
Input/output pins Channel 0:
TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2
Module data bus
TIOR
TIER
TCR
TGRB
TCNT
Channel 2:
TIORH TIORL
TMDR
Channel 0
TSR
TIER
TCR
Channel 1:
Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U
TMDR
Control logic for channel 0 to 2
Channel 1
TSR
TGRA
TIOR
TGRB TGRC TGRD TGRB
TCNT TCNT
[Legend] TSTR: Timer start register TSYR: Timer synchro register TCR: Timer control register TMDR: Timer mode register
TIOR(H, L) Timer I/O control registers (H, L) TIER: Timer interrupt enable register TSR: Timer status register TGR(A, B, C, D): TImer general registers (A, B, C, D)
Figure 12.1 Block Diagram of TPU
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TIER
TCR
TGRA
Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.1 TPU Functions
Item Count clock Channel 0 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD General registers (TGR) TGRA_0 TGRB_0 TGRA_1 TGRB_1 TIOCA1 TIOCB1 Channel 1 /1 /4 /16 /64 /256 TCLKA TCLKB Channel 2 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOCA2 TIOCB2
General registers/buffer TGRC_0 registers TGRC_0 I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 Counter clear function Compare match output 0 output 1 output Toggle output Input capture function
TGR compare match TGR compare match TGR compare match or or input capture or input capture input capture O O O O O O O O O O O O O O O O O O
Synchronous operation O PWM mode Phase counting mode Buffer operation O O
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Section 12 16-Bit Timer Pulse Unit (TPU)
Item DTC activation A/D converter trigger Interrupt sources
Channel 0
Channel 1
Channel 2
TGR compare match or TGR compare match or TGR compare match or input capture input capture input capture TGRA_0 compare match or input capture 5 sources * * * * * Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow TGRA_1 compare match or input capture 4 sources * * * * Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow TGRA_2 compare match or input capture 4 sources * * * * Compare match or input capture 2A Compare match or input capture 2B Overflow Underflow
[Legend] O: Enable : Disable
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.2
Input/Output Pins
Table 12.2 Pin Configuration
Channel All Symbol TCLKA TCLKB TCLKC TCLKD 0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 phase counting mode A phase input) External clock B input pin (Channel 1 phase counting mode B phase input) External clock C input pin (Channel 2 phase counting mode A phase input) External clock D input pin (Channel 2 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.3
Register Descriptions
The TPU has the following registers. * * * * * * * * * * * * * * * * * * * * * * * * * * * Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0) Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1) Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2)
Common Registers * Timer start register (TSTR) * Timer synchro register (TSYR)
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.3.1
Timer Control Register (TCR)
The TCR registers control the TCNT operation for each channel. The TPU has a total of three TCR registers, one for each channel (channel 0 to 2). TCR register settings should be made only when TCNT operation is stopped.
Bit 7 6 5 4 3 Bit Name Initial value CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 12.3 and 12.4 for details. Clock Edge 1 and 0 These bits select the input clock edge. When the input clock is counted using both edges, the input clock 1 and 2, /4 both edges = /2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges [Legend] x: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 12.5 to 12.7 for details.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.3 CCLR2 to CCLR0 (channel 0)
Channel 0 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous/clearing synchronous 1 operation* TCNT clearing disabled TCNT cleared by TGRC compare 2 match/input capture* TCNT cleared by TGRD compare 2 match/input capture* TCNT cleared by counter clearing for another channel performing synchronous 1 clearing/synchronous operation*
1
0
0 1
1
0 1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register. TCNT is not cleared because the buffer register setting has priority, and compare match/input capture dose not occur.
Table 12.4 CCLR2 to CCLR0 (channels 1 and 2)
Channel 1, 2 Bit 7 Bit 6 Reserved*2 CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous 1 clearing/synchronous operation*
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.5 TPSC2 to TPSC0 (channel 0)
Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input
Table 12.6 TPSC2 to TPSC0 (channel 1)
Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Setting prohibited
Note: This setting is ignored when channel 1 is in phase counting mode.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.7 TPSC2 to TPSC0 (channel 2)
Channel 2 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024
Note: This setting is ignored when channel 2 is in phase counting mode.
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.3.2
Timer Mode Register (TMDR)
The TMDR registers are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped.
Bit 7 6 5 Bit Name Initial value BFB 1 1 0 R/W R R R/W Description Reserved These bits are always read as 1 and cannot be modified. Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register. TGRD input capture/output compare is not generation. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 3 to 0 These bits are used to set the timer operating mode. MD3 is a reserved bit. In a write, the write value should always be 0. See table 12.8, MD3 to MD0 for details.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.8 MD3 to MD0
Bit 3 1 MD3* 0 Bit2 MD2*2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 x x 0 1 1 x Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Setting prohibited
[Legend] x: Don't care Notes: 1. MD3 is reserved bit. In a write, it should be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.3.3
Timer I/O Control Register (TIOR)
The TIOR registers control the TGR registers. The TPU has four TIOR registers, two each for channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. * TIORH_0, TIOR_1, TIOR_2
Bit 7 6 5 4 3 2 1 0 Bit Name Initial value IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control A3 to A0 Specify the function of TGRA. Description I/O Control B3 to B0 Specify the function of TGRB.
* TIORL_0
Bit 7 6 5 4 3 2 1 0 Bit Name Initial value IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. Description I/O Control D3 to D0 Specify the function of TGRD.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.9 TIORH_0 (channel 0)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture register Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge Capture input source is TIOCB0 pin Input capture at both edges Setting prohibited
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.10 TIORH_0 (channel 0)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture register TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Setting prohibited
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.11 TIORL_0 (channel 0)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register* TGRA_0 Function Output Compare register* TIOCD0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge Capture input source is TIOCD0 pin Input capture at both edges Setting prohibited
[Legend] x: Don't care Note: When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.12 TIORL_0 (channel 0)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 1 IOC0 0 1 1 0 1 TGRC_0 Function Output compare register* TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match 1 0 0 1 1 0 Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match 1 1 0 0 0 1 1 1 x x x Input capture register* Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Setting prohibited
[Legend] x: Don't care Note: * When the BFA bit in TMDR_0 is set to 1and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.13 TIOR_1 (channel 1)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match 1 0 0 1 1 0 Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match 1 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture register Initial output is 1 output Toggle output at compare match Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge Capture input source is TIOCB1 pin Input capture at both edges Setting prohibited
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.14 TIOR_1 (channel 1)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture register TGRA_1 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Setting prohibited
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.15 TIOR_2 (channel 2)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x Input capture register TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge Capture input source is TIOCB2 pin Input capture at both edges
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.16 TIOR_2 (channel 2)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x Input capture register TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.3.4
Timer Interrupt Enable Register (TIER)
The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel.
Bit 7 Bit Name Initial value TTGE 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 5 TCIEU 1 0 R R/W Reserved This bit is always read as 1 and cannot be modified. Underflow Interrupt Enable Enables or disables interrupt requests (TCU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channel 0, bit 5 is reserved. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD disabled 1: Interrupt requests (TGID) by TGFD enabled.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Bit 2
Bit Name Initial value TGIEC 0
R/W R/W
Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC disabled 1: Interrupt requests (TGIC) by TGFC enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB disabled 1: Interrupt requests (TGIB) by TGFB enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA disabled 1: Interrupt requests (TGIA) by TGFA enabled
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.3.5
Timer Status Register (TSR)
The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for each channel.
Bit 7 Bit Name Initial value TCFD 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channel 1 and 2. In channel 0, bit 7 is reserved. It is always read as 0 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 5 TCFU 1 0 R Reserved This bit is always read as 1 and cannot be modified. R/(W)* Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (change from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 4 TCFV 0 R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (change from H'FFFF to H'0000) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1
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Section 12 16-Bit Timer Pulse Unit (TPU)
Bit 3
Bit Name Initial value TGFD 0
R/W
Description
R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register When DTC is activated by TGID interrupt while DISEL bit or MRB in DTC is 0 When 0 is written to TGFD after reading TGFD = 1
[Clearing conditions] * * 2 TGFC 0
R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When the TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register When DTC is activated by TGIC interrupt while DISEL bit or MRB in DTC is 0 When 0 is written to TGFC after reading TGFC = 1
[Clearing conditions] * *
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Section 12 16-Bit Timer Pulse Unit (TPU)
Bit 1
Bit Name Initial value TGFB 0
R/W R/(W)*
Description Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * * When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register When DTC is activated by TGFB interrupt while DISEL bit of MRB in DTC is 0. When 0 is written to TGFB after reading TGFB = 1
[Clearing conditions] * * 0 TGFA 0 R/(W)*
Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. The write value should always be 0 to clear this flag. [Setting conditions] * * When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFA after reading TGFA = 1
[Clearing conditions] * * Note: *
The write value should always be 0 to clear the flag.
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.3.6
Timer Counter (TCNT)
The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 12.3.7 Timer General Register (TGR)
The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four for channel 0 and two each for channels 1 and 2. TGRC and TGRD for channel 0 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA--TGRC and TGRB--TGRD. 12.3.8 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2. TCNT of a channel performs counting when the corresponding bit in TSTR is set to 1. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bit Bit Name Initial Value R/W 0 0 0 0 R R/W R/W R/W Description Reserved The initial value should not be changed. 2 1 0 CST2 CST1 CST0 Counter Start 2 to 0 (CST2 to CST0) These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation
7 to 3 -
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.3.9
Timer Synchro Register (TSYR)
TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit Bit Name Initial Value R/W 0 0 0 0 R/W R/W R/W R/W Description Reserved: The initial value should not be changed. 2 1 0 SYNC2 SYNC1 SYNC0 Timer Synchro 2 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible
7 to 3 -
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.4
12.4.1
Interface to Bus Master
16-Bit Registers
TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read from or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 12.2.
Internal data bus
H
Bus master Module data bus
L
Bus interface
TCNTH
TCNTL
Figure 12.2 16-Bit Register Access Operation [Bus Master TCNT (16 Bits)] 12.4.2 8-Bit Registers
Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figures 12.3, 12.4, and 12.5.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Internal data bus
H
Bus master Module data bus
L
Bus interface
TCR
Figure 12.3 8-Bit Register Access Operation [Bus Master TCR (Upper 8 Bits)]
Internal data bus
H
Bus master Module data bus
L
Bus interface
TMDR
Figure 12.4 8-Bit Register Access Operation [Bus Master TMDR (Lower 8 Bits)]
Internal data bus
H
Bus master Module data bus
L
Bus interface
TCR
TMDR
Figure 12.5 8-Bit Register Access Operation [Bus Master TCR and TMDR (16 Bits)]
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.5
12.5.1
Operation
Basic Functions
Each channel has a TCNT and TGR. TCNT performs up-counting, and is also capable of freerunning operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation
When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. 1. Example of count operation setting procedure Figure 12.6 shows an example of the count operation setting procedure.
Operation selection [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation.
Select counter clock
[1]
Periodic counter
Free-running counter
Select counter clearing source
[2]
[3] Select output compare register
Set period
[4]
Start count operation
[5]
Start count operation
Figure 12.6 Example of Counter Operation Setting Procedure
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Section 12 16-Bit Timer Pulse Unit (TPU)
2. Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 12.7 illustrates free-running counter operation.
TCNT value H'FFFF
H'0000
Time
CST bit
TCFV
Figure 12.7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 12.8 illustrates periodic counter operation.
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Section 12 16-Bit Timer Pulse Unit (TPU)
TCNT value TGR
Counter cleared by TGR compare match
H'0000
Time
CST bit Flag cleared by software or DTC activation TGF
Figure 12.8 Periodic Counter Operation (2) Waveform Output by Compare Match
The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. Example of setting procedure for waveform output by compare match Figure 12.9 shows an example of the setting procedure for waveform output by compare match.
Output selection [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin unit the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation.
Select waveform output mode
[1]
Set output timing
[2]
Start count operation
[3]

Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match
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Section 12 16-Bit Timer Pulse Unit (TPU)
2. Examples of waveform output operation Figure 12.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time
Figure 12.10 Example of 0 Output/1 Output Operation Figure 12.11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output
TIOCB TIOCA
Figure 12.11 Example of Toggle Output Operation
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Section 12 16-Bit Timer Pulse Unit (TPU)
(3)
Input Capture Function
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. 1. Example of input capture operation setting procedure Figure 12.12 shows an example of the input capture operation setting procedure.
Input selection [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. [1]
Select input capture input
Start count
[2]

Figure 12.12 Example of Input Capture Operation Setting Procedure
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Section 12 16-Bit Timer Pulse Unit (TPU)
2. Example of input capture operation Figure 12.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB input (falling edge)
TCNT value H'0180 H'0160
H'0010 H'0005 H'0000 Time
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB TGRB H'0180
Figure 12.13 Example of Input Capture Operation
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.5.2
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 can all be designated for synchronous operation. (1) Example of Synchronous Operation Setting Procedure
Figure 12.14 shows an example of the synchronous operation setting procedure.
Synchronous operation selection Set synchronous operation [1]
Synchronous presetting
Synchronous clearing
Set TCNT
[2]
Clearing source generation channel? Yes Select counter clearing source Start count
No
[3]
Set synchronous counter clearing Start count
[4]
[5]
[5]

[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 12.14 Example of Synchronous Operation Setting Procedure
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Section 12 16-Bit Timer Pulse Unit (TPU)
(2)
Example of Synchronous Operation
Figure 12.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 12.5.4, PWM Modes.
Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time
TIOCA_0 TIOCA_1 TIOCA_2
Figure 12.15 Example of Synchronous Operation
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.5.3
Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 12.17 shows the register combinations used in buffer operation. Table 12.17 Register Combinations in Buffer Operation
Channel 0 Timer General Register TGRA_0 TGRB_0 Buffer Register TGRC_0 TGRD_0
* When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 12.16.
Compare match signal
Buffer register
Timer general register
Comparator
TCNT
Figure 12.16 Compare Match Buffer Operation * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 12.17.
Input capture signal
Buffer register
Timer general register
TCNT
Figure 12.17 Input Capture Buffer Operation
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Section 12 16-Bit Timer Pulse Unit (TPU)
(1)
Example of Buffer Operation Setting Procedure
Figure 12.18 shows an example of the buffer operation setting procedure.
Buffer operation
Select TGR function
[1]
[1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation.
Set buffer operation
[2]
Start count
[3]

Figure 12.18 Example of Buffer Operation Setting Procedure
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Section 12 16-Bit Timer Pulse Unit (TPU)
(2)
Examples of Buffer Operation
1. When TGR is an output compare register Figure 12.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 12.5.4, PWM Modes.
TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520
H'0450
TIOCA
Figure 12.19 Example of Buffer Operation (1)
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Section 12 16-Bit Timer Pulse Unit (TPU)
2. When TGR is an input capture register Figure 12.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value H'0F07 H'09FB H'0532 H'0000 Time
TIOCA
TGRA
H'0532
H'0F07
H'09FB
TGRC
H'0532
H'0F07
Figure 12.20 Example of Buffer Operation (2)
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.5.4
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0 % to 100 % duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 4-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 7-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 12.18.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.18 PWM Output Registers and Output Pins
Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
(1)
Example of PWM Mode Setting Procedure
Figure 12.21 shows an example of the PWM mode setting procedure.
PWM mode
Select counter clock
[1]
Select counter clearing source
[2]
Select waveform output level
[3]
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 start the count operation.
Set TGR
[4]
Set PWM mode
[5]
Start count
[6]

Figure 12.21 Example of PWM Mode Setting Procedure
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Section 12 16-Bit Timer Pulse Unit (TPU)
(2)
Examples of PWM Mode Operation
Figure 12.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty.
TCNT value TGRA
Counter cleared by TGRA compare match
TGRB H'0000 Time
TIOCA
Figure 12.22 Example of PWM Mode Operation (1)
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Section 12 16-Bit Timer Pulse Unit (TPU)
Figure 12.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty.
Counter cleared by TGRB_1 compare match
TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000
Time TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 12.23 Example of PWM Mode Operation (2)
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Section 12 16-Bit Timer Pulse Unit (TPU)
Figure 12.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
TCNT value TGRB rewritten TGRA
TGRB H'0000
TGRB rewritten
TGRB rewritten Time
TIOCA
0% duty
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time
TIOCA
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten
TGRB H'0000 100% duty 0% duty
TGRB rewritten Time
TIOCA
Figure 12.24 Example of PWM Mode Operation (3)
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.5.5
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 12.19 shows the correspondence between external clock pins and channels. Table 12.19 Phase Counting Mode Clock Input Pins
External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD
(1)
Example of Phase Counting Mode Setting Procedure
Figure 12.25 shows an example of the phase counting mode setting procedure.
Phase counting mode
[1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. [1]
Select phase counting mode
Start count
[2]

Figure 12.25 Example of Phase Counting Mode Setting Procedure
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Section 12 16-Bit Timer Pulse Unit (TPU)
(2)
Examples of Phase Counting Mode Operation
In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 12.26 shows an example of phase counting mode 1 operation, and table 12.20 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value
Up-count
Down-count
Time
Figure 12.26 Example of Phase Counting Mode 1 Operation Table 12.20 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count
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Section 12 16-Bit Timer Pulse Unit (TPU)
2. Phase counting mode 2 Figure 12.27 shows an example of phase counting mode 2 operation, and table 12.21 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count
Time
Figure 12.27 Example of Phase Counting Mode 2 Operation Table 12.21 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count
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Section 12 16-Bit Timer Pulse Unit (TPU)
3. Phase counting mode 3 Figure 12.28 shows an example of phase counting mode 3 operation, and table 12.22 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value
Up-count
Down-count
Time
Figure 12.28 Example of Phase Counting Mode 3 Operation Table 12.22 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care
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Section 12 16-Bit Timer Pulse Unit (TPU)
4. Phase counting mode 4 Figure 12.29 shows an example of phase counting mode 4 operation, and table 12.23 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value
Up-count
Down-count
Time
Figure 12.29 Example of Phase Counting Mode 4 Operation Table 12.23 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.6
12.6.1
Interrupts
Interrupt Source and Priority
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 12.24 lists the TPU interrupt sources.
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Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.24 TPU Interrupts
Channel Name 0 TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U Interrupt Source Interrupt Flag DTC Activation Enable Enable Enable Enable Disable Enable Enable Disable Disable Enable Enable Disable Disable Low Priority High
TGRA_0 input TGFA capture/compare match TGRB_0 input TGFB capture/compare match TGRC_0 input TGFC capture/compare match TGRD_0 input TGFD capture/compare match TCNT_0 overflow TCFV
TGRA_1 input TGFA capture/compare match TGRB_1 input TGFB capture/compare match TCNT_1 overflow TCNT_1 underflow TCFV TCFU
TGRA_2 input TGFA capture/compare match TGRB_2 input TGFB capture/compare match TCNT_2 overflow TCNT_2 underflow TCFV TCFU
Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.
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Section 12 16-Bit Timer Pulse Unit (TPU)
(1)
Input Capture/Compare Match Interrupt
An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channel 0, and two each for channels 1 and 2. (2) Overflow Interrupt
An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has three overflow interrupts, one for each channel. (3) Underflow Interrupt
An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has two underflow interrupts, one each for channels 1 and 2. 12.6.2 DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 7, Data Transfer Controller (DTC). A total of eight TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channel 0, and two each for channels 1 and 2. 12.6.3 A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of three TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel.
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.7
12.7.1 (1)
Operation Timing
Input/Output Timing
TCNT Count Timing
Figure 12.30 shows TCNT count timing in internal clock operation, and figure 12.31 shows TCNT count timing in external clock operation.
Internal clock
Falling edge
Rising edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 12.30 Count Timing in Internal Clock Operation
External clock
Falling edge
Rising edge
Falling edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 12.31 Count Timing in External Clock Operation
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Section 12 16-Bit Timer Pulse Unit (TPU)
(2)
Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 12.32 shows output compare output timing.
TCNT input clock TCNT N N+1
TGR
N
Compare match signal TIOC pin
Figure 12.32 Output Compare Output Timing (3) Input Capture Signal Timing
Figure 12.33 shows input capture signal timing.
Input capture input Input capture signal
TCNT
N
N+1
N+2
TGR
N
N+2
Figure 12.33 Input Capture Input Signal Timing
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Section 12 16-Bit Timer Pulse Unit (TPU)
(4)
Timing for Counter Clearing by Compare Match/Input Capture
Figure 12.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 12.35 shows the timing when counter clearing by input capture occurrence is specified.
Compare match signal Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 12.34 Counter Clear Timing (Compare Match)
Input capture signal
Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 12.35 Counter Clear Timing (Input Capture)
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Section 12 16-Bit Timer Pulse Unit (TPU)
(5)
Buffer Operation Timing
Figures 12.36 and 12.37 show the timing in buffer operation.
TCNT
n
n+1
Compare match signal TGRA, TGRB TGRC, TGRD
n
N
N
Figure 12.36 Buffer Operation Timing (Compare Match)
Input capture signal
TCNT
N
N+1
TGRA, TGRB TGRC, TGRD
n
N
N+1
n
N
Figure 12.37 Buffer Operation Timing (Input Capture)
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.7.2 (1)
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match
Figure 12.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing.
TCNT input clock
TCNT
N
N+1
TGR
N
Compare match signal
TGF flag
TGI interrupt
Figure 12.38 TGI Interrupt Timing (Compare Match)
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Section 12 16-Bit Timer Pulse Unit (TPU)
(2)
TGF Flag Setting Timing in Case of Input Capture
Figure 12.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing.
Input capture signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 12.39 TGI Interrupt Timing (Input Capture)
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Section 12 16-Bit Timer Pulse Unit (TPU)
(3)
TCFV Flag/TCFU Flag Setting Timing
Figure 12.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 12.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
TCNT input clock TCNT (overflow) Overflow signal
H'FFFF
H'0000
TCFV flag
TCIV interrupt
Figure 12.40 TCIV Interrupt Setting Timing
TCNT input clock TCNT (underflow) Underflow signal
H'0000
H'FFFF
TCFU flag
TCIU interrupt
Figure 12.41 TCIU Interrupt Setting Timing
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Section 12 16-Bit Timer Pulse Unit (TPU)
(4)
Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 12.42 shows the timing for status flag clearing by the CPU, and figure 12.43 shows the timing for status flag clearing by the DTC.
TSR write cycle T1 T2
Address
TSR address
Write signal
Status flag
Interrupt request signal
Figure 12.42 Timing for Status Flag Clearing by CPU
DTC read cycle T1 T2 DTC write cycle T1 T2
Address
Source address
Destination address
Status flag
Interrupt request signal
Figure 12.43 Timing for Status Flag Clearing by DTC Activation
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.8
12.8.1
Usage Notes
Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 12.44 shows the input clock conditions in phase counting mode.
Phase Phase differdifferOverlap ence ence
Overlap TCLKA (TCLKC) TCLKB (TCLKD)
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more
Figure 12.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 12.8.2 Caution on Period Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula:
f = -------- (N + 1)
Where f: Counter frequency : Operating frequency N: TGR set value
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.8.3
Conflict between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 12.45 shows the timing in this case.
TCNT write cycle T2 T1
Address
TCNT address
Write signal Counter clear signal
TCNT
N
H'0000
Figure 12.45 Conflict between TCNT Write and Clear Operations 12.8.4 Conflict between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 12.46 shows the timing in this case.
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Section 12 16-Bit Timer Pulse Unit (TPU)
TCNT write cycle T1 T2
Address
TCNT address
Write signal TCNT input clock N TCNT write data M
TCNT
Figure 12.46 Conflict between TCNT Write and Increment Operations 12.8.5 Conflict between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 12.47 shows the timing in this case.
TGR write cycle T1 T2 Address TGR address
Write signal Compare match signal TCNT N N+1
Prohibited
TGR
N TGR write data
M
Figure 12.47 Conflict between TGR Write and Compare Match
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.8.6
Conflict between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 12.48 shows the timing in this case.
TGR write cycle T2 T1 Address Buffer register address
Write signal Compare match signal Buffer register write data Buffer register TGR N M
N
Figure 12.48 Conflict between Buffer Register Write and Compare Match
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.8.7
Conflict between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 12.49 shows the timing in this case.
TGR read cycle T2 T1 Address TGR address
Read signal Input capture signal TGR X M
Internal data bus
M
Figure 12.49 Conflict between TGR Read and Input Capture
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.8.8
Conflict between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 12.50 shows the timing in this case.
TGR write cycle T2 T1 Address TGR address
Write signal Input capture signal TCNT M
TGR
M
Figure 12.50 Conflict between TGR Write and Input Capture
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.8.9
Conflict between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 12.51 shows the timing in this case.
Buffer register write cycle T2 T1 Address Buffer register address
Write signal Input capture signal TCNT N
TGR Buffer register
M
N
M
Figure 12.51 Conflict between Buffer Register Write and Input Capture
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.8.10 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 12.52 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
TCNT input clock TCNT Counter clear signal TGF Disabled TCFV H'FFFF H'0000
Figure 12.52 Conflict between Overflow and Counter Clearing
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Section 12 16-Bit Timer Pulse Unit (TPU)
12.8.11 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 12.53 shows the operation timing when there is conflict between TCNT write and overflow.
TCNT write cycle T2 T1
Address
TCNT address
Write signal
TCNT write data H'FFFF M
TCNT
TCFV flag
Figure 12.53 Conflict between TCNT Write and Overflow 12.8.12 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 12.8.13 Module Stop Mode Setting TPU operation can be enabled or disabled by the module stop control register. In the initial state, TPU operation is disabled. Access to TPU registers is enabled when module stop mode is cancelled. For details, see section 24, Power-Down Modes.
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Section 13 8-Bit Timer (TMR)
Section 13 8-Bit Timer (TMR)
This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, and TMR_X) with four channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
13.1
Features
* Selection of clock sources The counter input clock can be selected from six internal clocks and an external clock * Selection of three ways to clear the counters The counters can be cleared on compare-match A, compare-match B, or by an external reset signal. * Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. * Cascading of two channels Cascading of TMR_0 and TMR_1 Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1 as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count mode). Cascading of TMR_Y and TMR_X Operation as a 16-bit timer can be performed using TMR_Y as the upper half and TMR_X as the lower half (16-bit count mode). TMR_X can be used to count TMR_Y compare-match occurrences (compare-match count mode). * Multiple interrupt sources for each channel TMR_0, TMR_1, and TMR_Y: Three types of interrupts: Compare-match A, comparematch B, and overflow TMR_X: Four types of interrupts: Compare-match A, compare match B, overflow, and input capture
TIMH265A_000020020800
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Section 13 8-Bit Timer (TMR)
* Selection of general ports for timer input/output TMCI0/ExTMCI0, TMCI1/ExTMCI1, or TMIX/ExTMIX TMIY/ExTMIY or TMOX/ExTMOX Figures 13.1 and 13.2 show block diagrams of 8-bit timers. An input capture function is added to TMR_X.
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Section 13 8-Bit Timer (TMR)
External clock sources
TMCI0/ExTMCI1 TMCI1/ExTMCI0
Internal clock sources TMR_0 /2, /8, /32, /64, /256, /1024
TMR_1 /2, /8, /64, /128, /1024, /2048
Clock 1 Clock 0
Clock select
TCORA_0
TCORA_1
Compare-match A1 Compare-match A0 Comparator A_0
Overflow 1 Overflow 0
Clear 0
Comparator A_1
TMO0 TMRI0
TCNT_0
TCNT_1
Clear 1
Compare-match B1 Compare-match B0 Comparator B_0 TMO1 TMRI1 Control logic
Comparator B_1
TCORB_0
TCORB_1
TCSR_0
TCSR_1
TCR_0
TCR_1
Interrupt signals CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1
[Legend] TCORA_0: TCORB_0: TCNT_0: TCSR_0: TCR_0:
Time constant register A_0 Time constant register B_0 Timer counter_0 Timer control/status register_0 Timer control register_0
TCORA_1: TCORB_1: TCNT_1: TCSR_1: TCR_1:
Time constant register A_1 Time constant register B_1 Timer counter_1 Timer control/status register_1 Timer control register_1
Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)
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Internal bus
Section 13 8-Bit Timer (TMR)
External clock sources
TMCIY/ExTMCIX TMCIX/ExTMCIY
Internal clock sources TMR_X
, /2, /4, /2048, /4096, /8192
TMR_Y
/4, /256, /2048, /4096, /8192, /16384
Clock X Clock Y
Clock select
TCORA_Y
TCORA_X
Compare-match AX Compare-match AY
Overflow X Overflow Y Clear Y
Comparator A_Y
Comparator A_X
TCNT_Y
TCNT_X
Clear X
TMOY TMRIY
Comparator B_Y
Comparator B_X
Compare-match BY
TCORB_Y
Control logic
TMOX/ExTMOX TMRIX
TCORB_X
Input capture
TICRR TICRF TICR
Compare-match C
Comparator C
+
TCORC
TCSR_Y TCR_Y
TISR
Interrupt signals
TCSR_X TCR_X
CMIAY CMIBY OVIY ICIX
[Legend] TCORA_Y: Time constant register A_Y TCORB_Y: Time constant register B_Y TCNT_Y: Timer counter_Y TCSR_Y: Timer control/status register_Y TCR_Y: Timer control register_Y TISR: Timer input select register TCORA_X: Time constant register A_X TCORB_X: Time constant register B_X TCNT_X: Timer counter_X TCSR_X: Timer control/status register_X TCR_X: Timer control register_X TICR: Input capture register TCORC: Time constant register C TICRR: Input capture register R TICRF: Input capture register F
Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X)
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Internal bus
Compare- match BX
Section 13 8-Bit Timer (TMR)
13.2
Input/Output Pins
Table 13.1 summarizes the input and output pins of the TMR. Table 13.1 Pin Configuration
Channel TMR_0 Name Timer output Timer clock input Symbol TMO0 TMCI0, ExTMCI0 TMRI0 TMO1 TMCI1, ExTMCI1 TMRI1 I/O Output Input Function Output controlled by compare-match External clock input for the counter TMCI0 or ExTMCI0 is selected for timer input. Input Output Input External reset input for the counter Output controlled by compare-match External clock input for the counter TMCI1 or ExTMCI1 is selected for timer input. Input External reset input for the counter External clock input/external reset input for the counter TMIY or ExTMIY is selected for timer input. Timer output TMR_X Timer output TMOY TMOX, ExTMOX Output Output Output controlled by compare-match Output controlled by compare-match TMOX or ExTMOX is selected for timer output. External clock input/external reset input for the counter TMIX or ExTMIX is selected for timer input. Note: * For details, see section 8.17.1, Port Control Register 0 (PTCNT0).
Timer reset input TMR_1 Timer output Timer clock input
Timer reset input TMR_Y Timer clock/reset input
TMIY, ExTMIY Input (TMCIY/TMRIY)
Timer clock/reset input
TMIX, ExTMIX Input (TMCIX/TMRIX)
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Section 13 8-Bit Timer (TMR)
13.3
Register Descriptions
The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). TMR_0 * Timer counter_0 (TCNT_0) * Time constant register A_0 (TCORA_0) * Time constant register B_0 (TCORB_0) * Timer control register_0 (TCR_0) * Timer control/status register_0 (TCSR_0) TMR_1 * Timer counter_1 (TCNT_1) * Time constant register A_1 (TCORA_1) * Time constant register B_1 (TCORB_1) * Timer control register_1 (TCR_1) * Timer control/status register_1 (TCSR_1) TMR_Y * Timer counter_Y (TCNT_Y) * Time constant register A_Y (TCORA_Y) * Time constant register B_Y (TCORB_Y) * Timer control register_Y (TCR_Y) * Timer control/status register_Y (TCSR_Y) * Timer input select register (TISR) * Timer connection register S (TCONRS) TMR_X * Timer counter_X (TCNT_X) * Time constant register A_X (TCORA_X) * Time constant register B_X (TCORB_X) * Timer control register_X (TCR_X) * Timer control/status register_X (TCSR_X) * Input capture register (TICR) * Time constant register (TCORC) * Input capture register R (TICRR)
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Section 13 8-Bit Timer (TMR)
* Input capture register F (TICRF) * Timer connection register I (TCONRI) For both TMR_Y and TMR_X * Timer XY control register (TCRXY) Note: Some of the registers of TMR_X and TMR_Y use the same address. The registers can be switched by the TMRX/Y bit in TCONRS. TCNT_Y, TCORA_Y, TCORB_Y, and TCR_Y can be accessed when the RELOCATE bit in SYSCR3 and the KINWUE bit in SYSCR are cleared to 0 and the TMRX/Y bit in TCONRS is set to 1, or when the RELOCATE bit in SYSCR3 is set to 1. TCNT_X, TCORA_X, TCORB_X, and TCR_X can be accessed when the RELOCATE bit in SYSCR3, the KINWUE bit in SYSCR, and the TMRX/Y bit in TCONRS are cleared to 0, or when the RELOCATE bit in SYSCR3 is set to 1. 13.3.1 Timer Counter (TCNT)
Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 (or TCNT_X and TCNT_Y) comprise a single 16-bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, compare-match A signal or compare-match B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00. 13.3.2 Time Constant Register A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 (or TCORA_X and TCORA_Y) comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by these compare-match A signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF.
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Section 13 8-Bit Timer (TMR)
13.3.3
Time Constant Register B (TCORB)
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 (or TCORB_X and TCORB_Y) comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by these compare-match B signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. 13.3.4 Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests.
Bit 7 Bit Name Initial Value R/W Description CMIEB 0 R/W Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled 6 CMIEA 0 R/W Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt request (CMIA) is disabled 1: CMFA interrupt request (CMIA) is enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled
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Section 13 8-Bit Timer (TMR)
Bit 4 3
Bit Name Initial Value R/W Description CCLR1 CCLR0 0 0 R/W Counter Clear 1, 0 R/W These bits select the method by which the timer counter is cleared. 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input
2 1 0
CKS2 CKS1 CKS0
0 0 0
R/W Clock Select 2 to 0 R/W These bits select the clock input to TCNT and count R/W condition, together with the ICKS1 and ICKS0 bits in STCR. For details, see table 13.2.
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Section 13 8-Bit Timer (TMR)
Table 13.2 Clock Input to TCNT and Count Condition (1)
TCR Channel CKS2 TMR_0 0 0 0 0 0 0 0 1 TMR_1 0 0 0 0 0 0 0 1 CKS1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 CKS0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 STCR ICKS1 -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- ICKS0 -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- Description Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /32 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /256 Increments at overflow signal from TCNT_1* Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /128 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /2048 Increments at compare-match A from TCNT_0*
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Section 13 8-Bit Timer (TMR)
TCR Channel CKS2 Common 1 1 1 Note: * CKS1 0 1 1 CKS0 1 0 1
STCR ICKS1 -- -- -- ICKS0 -- -- -- Description Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock
If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated. These settings should not be made.
Table 13.2 Clock Input to TCNT and Count Condition (2)
TCR Channel CKS2 TMR_Y 0 0 0 0 1 0 0 0 0 1 1 1 1 CKS1 0 0 1 1 0 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 0 1 0 1 0 1 0 1 TCRXY CKSX -- -- -- -- -- -- -- -- -- -- -- -- -- CKSY 0 0 0 0 0 1 1 1 1 1 x x x Description Disables clock input Increments at /4 Increments at /256 Increments at /2048 Disables clock input Disables clock input Increments at /4096 Increments at /8192 Increments at /16384 Increments at overflow signal from TCNT_X* Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock
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Section 13 8-Bit Timer (TMR)
TCR Channel CKS2 TMR_X 0 0 0 0 1 0 0 0 0 1 1 1 1 Note: * CKS1 0 0 1 1 0 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 0 1 0 1 0 1 0 1
TCRXY CKSX 0 0 0 0 0 1 1 1 1 1 x x x CKSY -- -- -- -- -- -- -- -- -- -- -- -- -- Description Disables clock input Increments at Increments at /2 Increments at /4 Disables clock input Disables clock input Increments at /2048 Increments at /4096 Increments at /8192 Increments at compare-match A from TCNT_Y* Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock
If the TMR_Y clock input is set as the TCNT_X overflow signal and the TMR_X clock input is set as the TCNT_Y compare-match signal simultaneously, a count-up clock cannot be generated. These settings should not be made.
[Legend] x: Don't care : Invalid
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Section 13 8-Bit Timer (TMR)
13.3.5
Timer Control/Status Register (TCSR)
TCSR indicates the status flags and controls compare-match output. * TCSR_0
Bit 7 Bit Name Initial Value R/W CMFB 0 Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_0 and TCORB_0 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_0 and TCORA_0 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_0 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
4
ADTE
0
R/W
A/D Trigger Enable Enables or disables A/D converter start requests by compare-match A. 0: A/D converter start requests by compare-match A are disabled 1: A/D converter start requests by compare-match A are enabled
3 2
OS3 OS2
0 0
R/W R/W
Output Select 3, 2 These bits specify how the TMO0 pin output level is to be changed by compare-match B of TCORB_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
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Section 13 8-Bit Timer (TMR)
Bit 1 0
Bit Name Initial Value R/W OS1 OS0 0 0 R/W R/W
Description Output Select 1, 0 These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
Note:
*
Only 0 can be written, for flag clearing.
* TCSR_1
Bit 7 Bit Name Initial Value R/W CMFB 0 Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_1 and TCORA_1 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_1 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
4
--
1
R
Reserved This bit is always read as 1 and cannot be modified.
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Section 13 8-Bit Timer (TMR)
Bit 3 2
Bit Name Initial Value R/W OS3 OS2 0 0 R/W R/W
Description Output Select 3, 2 These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
1 0
OS1 OS0
0 0
R/W R/W
Output Select 1, 0 These bits specify how the TMO1 pin output level is to be changed by compare-match A of TCORA_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
Note:
*
Only 0 can be written, for flag clearing.
* TCSR_X
Bit 7 Bit Name Initial Value R/W CMFB 0 Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_X and TCORB_X match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_X and TCORA_X match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA
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Section 13 8-Bit Timer (TMR)
Bit 5
Bit Name Initial Value R/W OVF 0
Description
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_X overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
4
ICF
0
R/(W)* Input Capture Flag [Setting condition] When a rising edge and falling edge is detected in the external reset signal in that order. [Clearing condition] Read ICF when ICF = 1, then write 0 in ICF
3 2
OS3 OS2
0 0
R/W R/W
Output Select 3, 2 These bits specify how the TMOX pin output level is to be changed by compare-match B of TCORB_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
1 0
OS1 OS0
0 0
R/W R/W
Output Select 1, 0 These bits specify how the TMOX pin output level is to be changed by compare-match A of TCORA_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
Note:
*
Only 0 can be written, for flag clearing.
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Section 13 8-Bit Timer (TMR)
* TCSR_Y
Bit 7 Bit Name Initial Value R/W CMFB 0 Description
R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB
6
CMFA
0
R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_Y and TCORA_Y match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] When TCNT_Y overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF
4
ICIE
0
R/W
Input Capture Interrupt Enable Enables or disables the ICF interrupt request (ICIX) when the ICF bit in TCSR_X is set to 1. 0: ICF interrupt request (ICIX) is disabled 1: ICF interrupt request (ICIX) is enabled
3 2
OS3 OS2
0 0
R/W R/W
Output Select 3, 2 These bits specify how the TMOY pin output level is to be changed by compare-match B of TCORB_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
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Section 13 8-Bit Timer (TMR)
Bit 1 0
Bit Name Initial Value R/W OS1 OS0 0 0 R/W R/W
Description Output Select 1, 0 These bits specify how the TMOY pin output level is to be changed by compare-match A of TCORA_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output)
Note:
*
Only 0 can be written, for flag clearing.
13.3.6
Time Constant Register C (TCORC)
TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always compared with TCNT. When a match is detected, a compare-match C signal is generated. However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of TICR is disabled. TCORC is initialized to H'FF. 13.3.7 Input Capture Registers R and F (TICRR and TICRF)
TICRR and TICRF are 8-bit read-only registers. While the ICST bit in TCONRI is set to 1, the contents of TCNT are transferred at the rising edge and falling edge of the external reset input (TMRIX) in that order. The ICST bit is cleared to 0 when one capture operation ends. TICRR and TICRF are initialized to H'00.
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Section 13 8-Bit Timer (TMR)
13.3.8
Timer Input Select Register (TISR)
TISR permits or prohibits a signal source of external clock/reset input for the counter.
Bit Bit Name Initial Value R/W All 1 0 R/(W) R/W Description Reserved The initial value should not be changed. 0 IS Input Select Selects a timer clock/reset input pin (TMIY) as the signal source of external clock/reset input for the TMR_Y counter. 0: Input is prohibited 1: TMIY (TMCIY/TMRIY) is permitted for input
7 to 1 --
13.3.9
Timer Connection Register I (TCONRI)
TCONRI controls the input capture function.
Bit Bit Name Initial Value All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. 4 ICST Input Capture Start Bit TMR_X has input capture registers (TICRR and TICRF). TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF, respectively, and the ICST bit is cleared to 0. [Clearing condition] When a rising edge followed by a falling edge is detected on TMRIX [Setting condition] When 1 is written in ICST after reading ICST = 0
7 to 5 --
3 to 0 --
All 0
R/W
Reserved The initial values should not be modified.
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Section 13 8-Bit Timer (TMR)
13.3.10 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers.
Bit 7 Bit Name TMRX/Y Initial Value 0 R/W R/W Description TMR_X/TMR_Y Access Select For details, see table 13.3. 0: The TMR_X registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 1: The TMR_Y registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 6 to 0 All 0 R/W Reserved The initial values should not be modified.
Table 13.3 Registers Accessible by TMR_X/TMR_Y
TMRX/Y H'FFF0 0 1 TMR_X TCR_X TMR_Y TCR_Y H'FFF1 TMR_X TMR_Y H'FFF2 TMR_X TMR_Y H'FFF3 TMR_X TICRF TMR_Y H'FFF4 TMR_X TCNT TMR_Y H'FFF5 TMR_X TCORC TMR_Y H'FFF6 TMR_X H'FFF7 TMR_X
TCSR_X TICRR
TCORA_X TCORB_X
TCSR_Y TCORA_Y TCORB_Y TCNT_Y TISR
13.3.11 Timer XY Control Register (TCRXY) TCRXY selects the TMR_X and TMR_Y output pins and internal clock.
Bit 7, 6 5 4 3 to 0 Bit Name CKSX CKSY -- Initial Value All 0 0 0 All 0 R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. TMR_X Clock Select For details about selection, see table 13.2. TMR_Y Clock Select For details about selection, see table 13.2. Reserved The initial value should not be changed.
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Section 13 8-Bit Timer (TMR)
13.4
13.4.1
Operation
Pulse Output
Figure 13.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0, and set the CCLR0 bit in TCR to 1 so that TCNT is cleared according to the compare match of TCORA. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB. According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width can be output without the intervention of software.
TCNT H'FF TCORA TCORB H'00 Counter clear
TMO
Figure 13.3 Pulse Output Example
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Section 13 8-Bit Timer (TMR)
13.5
13.5.1
Operation Timing
TCNT Count Timing
Figure 13.4 shows the TCNT count timing with an internal clock source. Figure 13.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks () for a single edge and at least 2.5 system clocks () for both edges. The counter will not increment correctly if the pulse width is less than these values.
Internal clock
TCNT input clock
TCNT
N-1
N
N+1
Figure 13.4 Count Timing for Internal Clock Input
External clock input pin
TCNT input clock
TCNT
N-1
N
N+1
Figure 13.5 Count Timing for External Clock Input (Both Edges)
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Section 13 8-Bit Timer (TMR)
13.5.2
Timing of CMFA and CMFB Setting at Compare-Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 13.6 shows the timing of CMF flag setting.
TCNT
N
N+1
TCOR Compare-match signal
N
CMF
Figure 13.6 Timing of CMF Setting at Compare-Match 13.5.3 Timing of Timer Output at Compare-Match
When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 13.7 shows the timing of timer output when the output is set to toggle by a compare-match A signal.
Compare-match A signal
Timer output pin
Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal
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Section 13 8-Bit Timer (TMR)
13.5.4
Timing of Counter Clear at Compare-Match
TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.8 shows the timing of clearing the counter by a compare-match.
Compare-match signal
TCNT
N
H'00
Figure 13.8 Timing of Counter Clear by Compare-Match 13.5.5 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 13.9 shows the timing of clearing the counter by an external reset input.
External reset input pin
Clear signal
TCNT
N-1
N
H'00
Figure 13.9 Timing of Counter Clear by External Reset Input
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Section 13 8-Bit Timer (TMR)
13.5.6
Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of OVF flag setting.
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 13.10 Timing of OVF Flag Setting
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Section 13 8-Bit Timer (TMR)
13.6
TMR_0 and TMR_1 Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, the 16-bit count mode or compare-match count mode is available. 13.6.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with TMR_0 occupying the upper 8 bits and TMR_1 occupying the lower 8 bits. * Setting of compare-match flags The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs. The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit comparematch occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear by the TMI0 pin has been set. The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. * Pin output Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare-match conditions. Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare-match conditions. 13.6.2 Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts the occurrence of compare-match A for TMR_0. TMR_0 and TMR_1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each or TMR_0 and TMR_1.
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Section 13 8-Bit Timer (TMR)
13.7
TMR_Y and TMR_X Cascaded Connection
If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected by the settings of the CKSX and CKSY bits in TCRXY. 13.7.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_Y are set to B'100 and the CKSY bit in TCRXY is set to 1, the timer functions as a single 16-bit timer with TMR_Y occupying the upper eight bits and TMR_X occupying the lower 8 bits. * Setting of compare-match flags The CMF flag in TCSR_Y is set to 1 when an upper 8-bit compare-match occurs. The CMF flag in TCSR_X is set to 1 when a lower 8-bit compare-match occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR_Y have been set for counter clear at comparematch, only the upper eight bits of TCNT_Y are cleared. The upper eight bits of TCNT_Y are also cleared when counter clear by the TMRIY pin has been set. The settings of the CCLR1 and CCLR0 bits in TCR_X are enabled, and the lower 8 bits of TCNT_X can be cleared by the counter. * Pin output Control of output from the TMOY pin by bits OS3 to OS0 in TCSR_Y is in accordance with the upper 8-bit compare-match conditions. Control of output from the TMOX pin by bits OS3 to OS0 in TCSR_X is in accordance with the lower 8-bit compare-match conditions. 13.7.2 Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_X are set to B'100 and the CKSX bit in TCRXY is set to 1, TCNT_X counts the occurrence of compare-match A for TMR_Y. TMR_X and TMR_Y are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel.
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Section 13 8-Bit Timer (TMR)
13.7.3
Input Capture Operation
TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF. (1) Input Capture Signal Input Timing
Figure 13.11 shows the timing of the input capture operation.
TMRIX
Input capture signal TCNT_X TICRR TICRF M m n n n+1 n m N N N+1
Figure 13.11 Timing of Input Capture Operation If the input capture signal is input while TICRR and TICRF are being read, the input capture signal is delayed by one system clock () cycle. Figure 13.12 shows the timing of this operation.
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Section 13 8-Bit Timer (TMR)
TICRR, TICRF read cycle T1 T2
TMRIX
Input capture signal
Figure 13.12 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) (2) Selection of Input Capture Signal Input
TMRIX (input capture input signal of TMR_X) is selected according to the setting of the ICST bit in TCONRI. The input capture signal selection is shown in table 13.4. Table 13.4 Input Capture Signal Selection
TCONRI Bit 4 ICST 0 1 Description Input capture function not used TMIX pin input selection
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Section 13 8-Bit Timer (TMR)
13.8
Interrupt Sources
TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX. Table 13.5 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. Table 13.5 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X
Channel TMR_0 Name CMIA0 CMIB0 OVI0 TMR_1 CMIA1 CMIB1 OVI1 TMR_Y CMIAY CMIBY OVIY TMR_X ICIX CMIAX CMIBX OVIX Interrupt Source TCORA_0 compare-match TCORB_0 compare-match TCNT_0 overflow TCORA_1 compare-match TCORB_1 compare-match TCNT_1 overflow TCORA_Y compare-match TCORB_Y compare-match TCNT_Y overflow Input capture TCORA_X compare-match TCORB_X compare-match TCNT_X overflow Interrupt Flag CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF ICF CMFA CMFB OVF Low Interrupt Priority High
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Section 13 8-Bit Timer (TMR)
13.9
13.9.1
Usage Notes
Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 13.13, clearing takes priority and the counter write is not performed.
TCNT write cycle by CPU T1 T2
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 13.13 Conflict between TCNT Write and Clear
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Section 13 8-Bit Timer (TMR)
13.9.2
Conflict between TCNT Write and Count-Up
If a count-up occurs during the T2 state of a TCNT write cycle as shown in figure 13.14, the counter write takes priority and the counter is not incremented.
TCNT write cycle by CPU
T1
T2
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 13.14 Conflict between TCNT Write and Count-Up
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Section 13 8-Bit Timer (TMR)
13.9.3
Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 13.15, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled.
TCOR write cycle by CPU
T1
T2
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data Compare-match signal
Disabled
Figure 13.15 Conflict between TCOR Write and Compare-Match
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Section 13 8-Bit Timer (TMR)
13.9.4
Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the operation follows the output status that is defined for compare-match A or B, according to the priority of the timer output shown in table 13.6. Table 13.6 Timer Output Priorities
Output Setting Toggle output 1 output 0 output No change Low Priority High
13.9.5
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 13.7 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 13.7, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge, and TCNT is incremented. Erroneous incrementation can also happen when switching between internal and external clocks.
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Section 13 8-Bit Timer (TMR)
Table 13.7 Switching of Internal Clocks and TCNT Operation
Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from low 1 to low level*
No. 1
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT clock
TCNT
N CKS bit rewrite
N+1
2
Clock switching from low to high level*2
Clock before switchover Clock after switchover TCNT clock
TCNT
N
N+1
N+2
CKS bit rewrite
3
Clock switching from high to low level*3
Clock before switchover Clock after switchover TCNT clock *4
TCNT
N
N+1 CKS bit rewrite
N+2
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Section 13 8-Bit Timer (TMR)
No. 4
Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from high to high level
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT clock
TCNT
N
N+1
N+2 CKS bit rewrite
Notes: 1. 2. 3. 4.
Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
13.9.6
Mode Setting with Cascaded Connection
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. 13.9.7 Module Stop Mode Setting
TMR operation can be enabled or disabled using the module stop control register. The initial setting is for TMR operation to be halted. Register access is enabled by canceling the module stop mode. For details, see section 24, Power-Down Modes.
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Section 14 Watchdog Timer (WDT)
Section 14 Watchdog Timer (WDT)
This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can output an overflow signal (RESO) externally if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can generate an internal reset signal or an internal NMI interrupt signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. A block diagram of the WDT_0 and WDT_1 are shown in figure 14.1.
14.1
Features
* Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks. * Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode: * If the counter overflows, an internal reset or an internal NMI interrupt is generated. * When the LSI is selected to be internally reset at counter overflow, a low level signal is output from the RESO pin if the counter overflows. Internal Timer Mode: * If the counter overflows, an internal timer interrupt (WOVI) is generated.
WDT0102A_000020020300
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Section 14 Watchdog Timer (WDT)
WOVI0 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signal*1 Internal reset signal*1
Interrupt control Reset control
Overflow
Clock
Clock selection
/2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock
TCNT_0
TCSR_0
Module bus WDT_0
Bus interface
WOVI1 (Interrupt request signal) Internal NMI (Interrupt request signal*2) RESO signal*1 Internal reset signal*1
Interrupt control Reset control
Overflow
Clock
Clock selection
/2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock
SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256
TCNT_1
TCSR_1
Module bus WDT_1 [Legend] TCSR_0: Timer control/status register_0 TCNT_0: Timer counter_0 TCSR_1: Timer control/status register_1 TCNT_1: Timer counter_1
Bus interface
Notes: 1. The RESO signal outputs the low level signal when the internal reset signal is generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal first resets the WDT in which the overflow has occurred first. 2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1. The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from that from WDT_1.
Figure 14.1 Block Diagram of WDT
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Internal bus
Internal bus
Section 14 Watchdog Timer (WDT)
14.2
Input/Output Pins
The WDT has the pins listed in table 14.1. Table 14.1 Pin Configuration
Name Reset output pin Symbol RESO I/O Output Input Function Outputs the counter overflow signal in watchdog timer mode Inputs the clock pulses to the WDT_1 prescaler counter
External sub-clock input EXCL pin
14.3
Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers. For details, see section 14.6.1, Notes on Register Access. For details on the system control register, see section 3.2.2, System Control Register (SYSCR). * Timer counter (TCNT) * Timer control/status register (TCSR) 14.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared to 0.
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Section 14 Watchdog Timer (WDT)
14.3.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode. * TCSR_0
Bit 7 Bit Name Initial Value R/W OVF 0 Description
R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] * * When TCSR is read when OVF = 1, then 0 is written to OVF When 0 is written to TME
6
WT/IT
0
R/W
Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode
5
TME
0
R/W
Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H00.
4 3
0
R/(W) R/W
Reserved The initial value should not be changed. Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested
RST/NMI 0
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Section 14 Watchdog Timer (WDT)
Bit 2 1 0
Bit Name Initial Value R/W CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W
Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow frequency for = 20 MHz is enclosed in parentheses. 000: /2 (frequency: 25.6 s) 001: /64 (frequency: 819.2 s) 010: /128 (frequency: 1.6 ms) 011: /512 (frequency: 6.6 ms) 100: /2048 (frequency: 26.2 ms) 101: /8192 (frequency: 104.9 ms) 110: /32768 (frequency: 419.4 ms) 111: /131072 (frequency: 1.68 s)
Note:
*
Only 0 can be written, to clear the flag.
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Section 14 Watchdog Timer (WDT)
* TCSR_1
Bit 7 Bit Name Initial Value R/W OVF 0
1
Description
R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] When TCSR is read when OVF = 1* , then 0 is written to OVF When 0 is written to TME
2
6
WT/IT
0
R/W
Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode
5
TME
0
R/W
Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00.
4
PSS
0
R/W
Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided cycle of -based prescaler (PSM) 1: Counts the divided cycle of SUB-based prescaler (PSS)
3
RST/NMI 0
R/W
Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested
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Section 14 Watchdog Timer (WDT)
Bit 2 1 0
Bit Name Initial Value R/W CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W
Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow cycle for = 20 MHz and SUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: /2 (frequency: 25.6 s) 001: /64 (frequency: 819.2 s) 010: /128 (frequency: 1.6 ms) 011: /512 (frequency: 6.6 ms) 100: /2048 (frequency: 26.2 ms) 101: /8192 (frequency: 104.9 ms) 110: /32768 (frequency: 419.4 ms) 111: /131072 (frequency: 1.68 s) When PSS = 1: 000: SUB/2 (cycle: 15.6 ms) 001: SUB/4 (cycle: 31.3 ms) 010: SUB/8 (cycle: 62.5 ms) 011: SUB/16 (cycle: 125 ms) 100: SUB/32 (cycle: 250 ms) 101: SUB/64 (cycle: 500 ms) 110: SUB/128 (cycle: 1 s) 111: SUB/256 (cycle: 2 s)
Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice.
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Section 14 Watchdog Timer (WDT)
14.4
14.4.1
Operation
Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the RESO pin for 132 states, as shown in figure 14.2. If the RST/NMI bit is cleared to 0, when the TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin remains high. An internal reset request from the watchdog timer and a reset input from the RES pin are processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin at the same time.
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Section 14 Watchdog Timer (WDT)
TCNT value Overflow H'FF
H'00 WT/IT = 1 TME = 1 Internal reset signal 518 System clocks WT/IT : Timer mode select bit TME : Timer enable bit OVF : Overflow flag Note * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0. Write H'00 to TCNT OVF = 1*
Time WT/IT = 1 Write H'00 to TME = 1 TCNT
Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation 14.4.2 Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 14.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF flag of TCSR is set to 1. The timing is shown figure 14.4.
TCNT value H'FF Overflow Overflow Overflow Overflow
H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI
Time
WOVI : Interval timer interrupt request occurrence
Figure 14.3 Interval Timer Mode Operation
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Section 14 Watchdog Timer (WDT)
TCNT
H'FF
H'00
Overflow signal (internal signal)
OVF
Figure 14.4 OVF Flag Set Timing 14.4.3 RESO Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF flag in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin. The timing is shown in figure 14.5.
TCNT
H'FF
H'00
Overflow signal (internal signal)
OVF
RESO signal
132 states
Internal reset signal
518 states
Figure 14.5 Output Timing of RESO signal
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Section 14 Watchdog Timer (WDT)
14.5
Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow Table 14.2 WDT Interrupt Source
Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Disable
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Section 14 Watchdog Timer (WDT)
14.6
14.6.1
Usage Notes
Notes on Register Access
The watchdog timer's registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. (1) Writing to TCNT and TCSR (Example of WDT_0)
These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 14.6 to write to TCNT or TCSR. To write to TCNT, the higher bytes must contain the value H'5A and the lower bytes must contain the write data before the transfer instruction execution. To write to TCSR, the higher bytes must contain the value H'A5 and the lower bytes must contain the write data.
15 Address : H'FFA8 H'5A 87 Write data 0
15 Address : H'FFA8 H'A5 87 Write data 0
Figure 14.6 Writing to TCNT and TCSR (WDT_0)
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Section 14 Watchdog Timer (WDT)
(2)
Reading from TCNT and TCSR (Example of WDT_0)
These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT. 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.7 shows this operation.
TCNT write cycle T1 T2
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 14.7 Conflict between TCNT Write and Increment
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Section 14 Watchdog Timer (WDT)
14.6.3
Changing Values of CKS2 to CKS0 Bits
If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of CKS2 to CKS0 bits. 14.6.4 Changing Value of PSS Bit
If the PSS bit in TCSR_1 is written to while the WDT is operating, errors could occur in the operation. Stop the watchdog timer (by clearing the TME bit to 0) before changing the values of PSS bit. 14.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from/to watchdog timer to/from interval timer, while the WDT is operating, errors could occur in the operation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 14.6.6 System Reset by RESO Signal
Inputting the RESO output signal to the RES pin of this LSI prevents the LSI from being initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI. To reset the entire system by the RESO signal, use the circuit as shown in figure 14.8.
This LSI Reset input RES
Reset signal for entire system
RESO
Figure 14.8 Sample Circuit for Resetting the System by the RESO Signal
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Section 15 Serial Communication Interface (SCI, IrDA)
Section 15 Serial Communication Interface (SCI, IrDA)
This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports the smart card (IC card) interface based on ISO/IEC 7816-3 (Identification Card) as an enhanced asynchronous communication function. Communication using the waveform based on the Infrared Data Association (IrDA) standard version 1.0 can also be handled.
15.1
Features
* Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected The External clock can be selected as a transfer clock source (except for the smart card interface). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources transmit-end, transmit-data-empty, receive-data-full, and receive error that can issue requests. The transmit-data-empty and receive-data-full interrupt sources can activate DTC.
SCI0022A_000020020300
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Section 15 Serial Communication Interface (SCI, IrDA)
Asynchronous Mode: Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error * Multiprocessor communication capability Clocked Synchronous Mode: * Data length: 8 bits * Receive error detection: Overrun errors Smart Card Interface: * An error signal can be automatically transmitted on detection of a parity error during reception. * Data can be automatically re-transmitted on detection of an error signal during transmission. * Both direct convention and inverse convention are supported. Figure 15.1 shows a block diagram of SCI. * * * * *
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Section 15 Serial Communication Interface (SCI, IrDA)
Module data bus
RDR
TDR
SCMR SSR SCR
BRR Baud rate generator /4 /16 /64 Clock External clock TEI TXI RXI ERI
RxD1
RSR
TSR
SMR Transmission/ reception control
TxD1 Parity check SCK1
Parity generation
[Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register
SCR: Serial control register SSR: Serial status register SCMR: Smart card mode register BRR: Bit rate register
Figure 15.1 Block Diagram of SCI
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Internal data bus
Bus interface
Section 15 Serial Communication Interface (SCI, IrDA)
15.2
Input/Output Pins
Table 15.1 shows the input/output pins for each SCI channel. Table 15.1 Pin Configuration
Channel 1 Symbol* SCK1 RxD1/IrRxD TxD1/IrTxD 2 SCK2 RxD2 TxD2 Note: * Input/Output Input/Output Input Output Input/Output Input Output Function Channel 1 clock input/output Channel 1 receive data input (normal/IrDA) Channel 1 transmit data output (normal/IrDA) Channel 2 clock input/output Channel 2 receive data input Channel 2 transmit data output
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3
Register Descriptions
The SCI has the following registers for each channel. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modesnormal serial communication interface mode and smart card interface mode; therefore, the bits are described separately for each mode in the corresponding register sections. * * * * * * * * * * Receive shift register (RSR) Receive data register (RDR) Transmit data register (TDR) Transmit shift register (TSR) Serial mode register (SMR) Serial control register (SCR) Serial status register (SSR) Smart card mode register (SCMR) Bit rate register (BRR) Keyboard comparator control register (KBCOMP)*
Note: * KBCOMP is available in SCI_1. 15.3.1 Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 15.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. The initial value of RDR is H'00.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.3
Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. The initial value of TDR is H'FF. 15.3.4 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, and then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 15.3.5 Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode.
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Section 15 Serial Communication Interface (SCI, IrDA)
* Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 2
Bit Name MP
Initial Value 0
R/W R/W
Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode.
1 0
CKS1 CKS0
0 0
R/W R/W
Clock Select 1,0 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)).
* Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu* from the start and the clock output control function is appended. For details, see section 15.7.8, Clock Output Control. 6 BLK 0 R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 15.7.3, Block Transfer Mode. Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode.
5
PE
0
R/W
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 4
Bit Name O/E
Initial Value 0
R/W R/W
Description Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 15.7.2, Data Format (Except in Block Transfer Mode).
3 2
BCP1 BCP0
0 0
R/W R/W
Basic Clock Pulse 1,0 These bits select the number of basic clock cycles in a 1-bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 15.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 15.3.9, Bit Rate Register (BRR).
1 0
CKS1 CKS0
0 0
R/W R/W
Clock Select 1, 0 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)).
Note:
*
etu: Element Time Unit (time taken to transfer one bit)
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.6
Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 15.9, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode. * Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 15.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 1, 0 These bits select the clock source and SCK pin function. * Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1x: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) * Clocked synchronous mode 0x: Internal clock (SCK pin functions as clock output.) 1x External clock (SCK pin functions as clock input.)
[Legend] x: Don't care
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Section 15 Serial Communication Interface (SCI, IrDA)
* Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. 2 1 0 TEIE CKE1 CKE0 0 0 0 R/W R/W R/W Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode. Clock Enable 1, 0 Controls the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 15.7.8, Clock Output Control. * When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) 01: Clock output 1x: Reserved * When GM in SMR = 1 00: Output fixed to low 01: Clock output 10: Output fixed to high 11: Clock output [Legend] x: Don't care
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode. * Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and TDR is ready for data write When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DTC to write data to TDR
[Clearing conditions] * * 6 RDRF 0 R/(W)*
Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When an RXI interrupt request is issued allowing DTC to read data from RDR
[Clearing conditions] * *
The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 5
Bit Name ORER
Initial Value 0
R/W R/(W)*
Description Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 When 0 is written to ORER after reading ORER = 1
[Clearing condition] * 4 FER 0 R/(W)*
Framing Error [Setting condition] * * When the stop bit is 0 When 0 is written to FER after reading FER = 1 [Clearing condition]
In 2-stop-bit mode, only the first stop bit is checked. 3 PER 0 R/(W)* Parity Error [Setting condition] * When a parity error is detected during reception When 0 is written to PER after reading PER = 1
[Clearing condition] * 2 TEND 1 R
Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character When 0 is written to TDRE after reading TDRE =1 When a TXI interrupt request is issued allowing DTC to write data to TDR
[Clearing conditions] * *
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 1
Bit Name MPB
Initial Value 0
R/W R
Description Multiprocessor Bit MPB stores the multiprocessor bit in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit frame.
Note:
*
Only 0 can be written to clear the flag.
* Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR, and TDR can be written to. When 0 is written to TDRE after reading TDRE =1 When a TXI interrupt request is issued allowing DTC to write data to TDR
[Clearing conditions] * *
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 6
Bit Name RDRF
Initial Value 0
R/W R/(W)*
1
Description Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When an RXI interrupt request is issued allowing DTC to read data from RDR
[Clearing conditions] * *
The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)*1 Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 When 0 is written to ORER after reading ORER = 1
[Clearing condition] * 4 ERS 0 R/(W)*1
Error Signal Status [Setting condition] * * When a low error signal is sampled When 0 is written to ERS after reading ERS = 1 [Clearing condition]
3
PER
0
R/(W)*1
Parity Error [Setting condition] * * When a parity error is detected during reception When 0 is written to PER after reading PER = 1 [Clearing condition]
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 2
Bit Name TEND
Initial Value 1
R/W R
Description Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When both TE and EPS in SCR are 0 When ERS = 0 and TDRE = 1 after a specified time passed after the start of 1-byte data transfer. The set timing depends on the register setting as follows. When GM = 0 and BLK = 0, 2.5 etu*2 after transmission start
2 When GM = 0 and BLK = 1, 1.5 etu* after transmission start
* * * *
When GM = 1 and BLK = 0, 1.0 etu*2 after transmission start When GM = 1 and BLK = 1, 1.0 etu*2 after transmission start When 0 is written to TDRE after reading TDRE =1 When a TXI interrupt request is issued allowing DTC to write the next data to TDR
[Clearing conditions] * * 1 0 MPB MPBT 0 0 R R/W
Multiprocessor Bit Not used in smart card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in smart card interface mode.
Notes: 1. Only 0 can be written to clear the flag. 2. etu: Element Time Unit (time taken to transfer one bit)
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.8
Smart Card Mode Register (SCMR)
SCMR selects smart card interface mode and its format.
Bit 7 to 4 Bit Name Initial Value All 1 R/W R Description Reserved These bits are always read as 1 and cannot be modified. 3 SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Receive data is stored as LSB first in RDR. 1: TDR contents are transmitted with MSB-first. Receive data is stored as MSB first in RDR. The SDIR bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. When the parity bit is inverted, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 1 R Reserved This bit is always read as 1 and cannot be modified. 0 SMIF 0 R/W Smart Card Interface Mode Select When this bit is set to 1, smart card interface mode is selected. 0: Normal asynchronous or clocked synchronous mode 1: Smart card interface mode
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Mode Asynchronous mode
B= 64 x 2
Bit Rate
x 106
2n - 1
Error
Error (%) = { x 106 B x 64 x 2
2n - 1
- 1 } x 100
x (N + 1)
x (N + 1)
Clocked synchronous mode
B=
x 106 8x2
2n - 1
x (N + 1)
x 106 BxSx2
2n + 1
Smart card interface mode
B= Sx2
x 106
2n + 1
Error (%) = {
-1 } x 100
x (N + 1)
x (N + 1)
[Legend]
B: N: : n and S: SMR Setting CKS1 0 0 1 1
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Determined by the SMR settings shown in the following table SMR Setting CKS0 0 1 0 1 n 0 1 2 3 BCP1 0 0 1 1 BCP0 0 1 0 1 S 32 64 372 256
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate settable for each frequency. Table 15.6 and 15.8 show sample N settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected. For details, see section 15.7.4, Receive Data Sampling Timing and Reception Margin. Tables 15.5 and 15.7 show the maximum bit rates with external clock input. Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency (MHz) 4 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 1 1 0 0 0 0 0 N 70 Error (%) 0.03 n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 Error (%) 0.31 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 5 Error (%) -0.25 0.16 n 2 2 1 1 0 0 0 0 0 0 0 N 6 Error (%) n 2 2 1 1 0 0 0 0 0 0 0 6.144 N Error (%)
106 -0.44 77 0.16
108 0.08 79 0.00
207 0.16 103 0.16 207 0.16 103 0.16 51 25 12 0.16 0.16 0.16 0.00
255 0.00 127 0.00 255 0.00 127 0.00 63 31 15 7 4 3 0.00 0.00 0.00 0.00 -1.70 0.00
129 0.16 64 0.16
155 0.16 77 0.16
159 0.00 79 0.00
129 0.16 64 32 15 7 4 3 0.16 -1.36 1.73 1.73 0.00 1.73
155 0.16 77 38 19 9 5 4 0.16 0.16 -2.34 -2.34 0.00 -2.34
159 0.00 79 39 19 9 5 4 0.00 0.00 0.00 0.00 2.40 0.00
0 3
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Section 15 Serial Communication Interface (SCI, IrDA)
Operating Frequency (MHz) 7.3728 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 2 2 1 1 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73
[Legend] : Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%.
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency (MHz) 12 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00
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Section 15 Serial Communication Interface (SCI, IrDA)
Operating Frequency (MHz) 16 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 70 Error (%) 0.03 17.2032 nN 3 2 2 1 1 0 0 0 0 0 0 75 Error (%) 0.48 nN 3 2 2 1 1 0 0 0 0 0 0 79 18 Error (%) -0.12 19.6608 nN 3 2 2 1 1 0 0 0 0 0 0 86 Error (%) 0.31 nN 3 3 2 2 1 1 0 0 0 0 0 88 64 20 Error (%) -0.25 0.16
207 0.16 103 0.16 207 0.16 103 0.16 207 0.16 103 0.16 51 25 15 12 0.16 0.16 0.00 0.16
223 0.00 111 0.00 223 0.00 111 0.00 223 0.00 111 0.00 55 27 16 16 0.00 0.00 1.20 0.00
233 0.16 116 0.16 233 0.16 116 0.16 233 0.16 116 0.16 58 28 17 14 -0.69 1.02 0.00 -2.34
255 0.00 127 0.00 255 0.00 127 0.00 255 0.00 127 0.00 63 31 19 15 0.00 0.00 -1.70 0.00
129 0.16 64 0.16
129 0.16 64 0.16
129 0.16 64 32 19 15 0.16 -1.36 0.00 1.73
[Legend] : Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%.
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 230400 250000 307200 312500 Maximum Bit Rate (bit/s) 375000 384000 437500 460800 500000 537600 562500 614400 625000
(MHz) 4 44.9152 5 6 6.144 7.3728 8 9.8304 10
n 0 0 0 0 0 0 0 0 0
N 0 0 0 0 0 0 0 0 0
(MHz) 12 12.288 14 14.7456 16 17.2032 18 19.6608 20
n 0 0 0 0 0 0 0 0 0
N 0 0 0 0 0 0 0 0 0
Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
(MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 External Input Clock (MHz) 1.0000 1.2288 1.2500 15.000 1.5360 1.8432 2.0000 2.4576 2.5000 Maximum Bit Rate (bit/s) 62500 76800 78125 93750 96000 115200 125000 153600 156250 (MHz) 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Maximum Bit Clock (MHz) Rate (bit/s) 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 187500 192000 218750 230400 250000 268800 281250 307200 312500
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M [Legend] Blank: Setting prohibited. : Can be set, but there will be a degree of error. *: Continuous transfer or reception is not possible. 4 n 2 2 1 1 0 0 0 0 0 0 0 0 N 29 124 249 99 199 99 39 19 9 3 1 0 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* 1 1 0 0 0 0 0 0 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 2 1 1 0 0 0 0 0 0 0 0 124 249 124 199 99 49 19 9 4 1 0* n 8 N n 10 N n 16 N n 20 N
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
(MHz) 4 6 8 10 12 External Input Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 Maximum Bit Rate (bit/s) 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 (MHz) 14 16 18 20 External Input Clock (MHz) 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 2333333.3 2666666.7 3000000.0 3333333.3
Table 15.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372)
Operating Frequency (MHz) Bit Rate (bit/s) 9600 7.1424 10.00 13.00 14.2848 16.00 n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 0 0 0.00 0 1 30 0 1 -8.99 0 1 0.00 0 1 12.01
Operating Frequency (MHz) Bit Rate (bit/s) 9600 18.00 20.00 n N Error (%) n N Error (%) 0 2 -15.99 0 2 -6.65
Table 15.9 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372)
Maximum Bit Rate (bit/s) 9600 13441 17473 19200 Maximum Bit Rate (bit/s) n 21505 24194 26882 0 0 0
(MHz) 7.1424 10.00 13.00 14.2848
n 0 0 0 0
N 0 0 0 0
(MHz) 16.00 18.00 20.00
N 0 0 0
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.10 Keyboard Comparator Control Register (KBCOMP) KBCOMP controls IrDA operation of SCI_1.
Bit 7 Bit Name IrE Initial Value 0 R/W R/W Description IrDA Enable Specifies SCI_1 I/O pins for either normal SCI or IrDA. 0: TxD1/IrTxD and RxD1/IrRxD pins function as TxD1 and RxD1 pins, respectively 1: TxD1/IrTxD and RxD1/IrRxD pins function as IrTxD and IrRxD pins, respectively 6 5 4 IrCKS2 IrCKS1 IrCKS0 0 0 0 R/W R/W R/W IrDA Clock Select 2 to 0 Specifies the high-level width of the clock pulse during IrTxD output pulse encoding when the IrDA function is enabled. 000: B x 3/16 (three sixteenths of the bit rate) 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 3 IrTxINV 0 R/W IrTx Data Invert Specifies the inversion of the logic level of the output from IrTxD. When the inversion is specified, IrCKS2 to IrCKS0 specify the low-level width, not the highlevel width. 0: Transmit data is output from IrTxD as it is 1: Transmit data is inverted before being output from IrTxD
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 2
Bit Name IrRxINV
Initial Value 0
R/W R/W
Description IrRx Data Invert Specifies the inversion of the logic level of the input to IrRxD. When the inversion is specified, IrCKS2 to IrCKS0 specify the low-level width, not the high-level width. 0: Input to IrRxD is used as receive data as it is 1: Input to IrRxD is inverted before being used as receive data
1, 0
All 0
R
Reserved These bits are always read as 0 and cannot be modified.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.4
Operation in Asynchronous Mode
Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception.
Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1
Stop bit
Transmit/receive data 7 or 8 bits
1 or 2 bits
One unit of transfer data (character or frame)
Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 15.4.1 Data Transfer Format
Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 15.5, Multiprocessor Communication Function.
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12
8-bit data
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
--
1
0
S
8-bit data
MPB STOP
0
--
1
1
S
8-bit data
MPB STOP STOP
1
--
1
0
S
7-bit data
MPB STOP
1
--
1
1
S
7-bit data
MPB STOP STOP
[Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit
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Section 15 Serial Communication Interface (SCI, IrDA)
15.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 15.3. Thus the reception margin in asynchronous mode is determined by formula (1) below.
M = } (0.5 - M: N: D: L: F:
1 2N
)-
D - 0.5 (1 + F) - (L - 0.5) F } x 100 N
[%]
... Formula (1)
Reception margin (%) Ratio of bit rate to clock (N = 16) Clock duty (D = 0.5 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below.
M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0
Receive data (RxD) Synchronization sampling timing
Start bit
D0
D1
Data sampling timing
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode
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Section 15 Serial Communication Interface (SCI, IrDA)
15.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 15.4.
SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 frame
Figure 15.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode)
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Section 15 Serial Communication Interface (SCI, IrDA)
15.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
[4]
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0)
[1]
Set data transfer format in SMR and SCMR Set value in BRR Wait
[2]
[3]
No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits

Figure 15.5 Sample SCI Initialization Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
15.4.5
Serial Data Transmission (Asynchronous Mode)
Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 15.7 shows a sample flowchart for transmission in asynchronous mode.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1
1
1 Idle state (mark state)
TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt service routine
TEI interrupt request generated
1 frame
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization Start transmission
[1]
Read TDRE flag in SSR
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure:
No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes [3] Read TEND flag in SSR
No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1
To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0.
[4]
Clear TE bit in SCR to 0
Figure 15.7 Sample Serial Transmission Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
15.4.6
Serial Data Reception (Asynchronous Mode)
Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0
1
1 Idle state (mark state)
RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ERI interrupt request generated by framing error
1 frame
Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception. Table 15.11 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception.
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
[2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER FER ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin.
Read ORER, PER, and FER flags in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
[4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. However, the RDRF flag is cleared automatically when the DTC is initiated by an RXI interrupt and reads data from RDR.
Legend : Logical add (OR)
No All data received? Yes Clear RE bit in SCR to 0 [5]
Figure 15.9 Sample Serial Reception Flowchart (1)
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Section 15 Serial Communication Interface (SCI, IrDA)
[3] Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
No PER = 1 Yes Parity error processing
Clear ORER, PER, and FER flags in SSR to 0

Figure 15.9 Sample Serial Reception Flowchart (2)
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Section 15 Serial Communication Interface (SCI, IrDA)
15.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 15.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the RDRF, FER, and ORER status flags in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
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Section 15 Serial Communication Interface (SCI, IrDA)
Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) Receiving station C (ID = 03) H'AA (MPB = 0) Receiving station D (ID = 04)
ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID Legend MPB: Multiprocessor bit
Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
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Section 15 Serial Communication Interface (SCI, IrDA)
15.5.1
Multiprocessor Serial Data Transmission
Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
Initialization Start transmission
[1]
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set port DDR to 1, clear DR to 0, and then clear the TE bit in SCR to 0.
Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] [3]
Clear TE bit in SCR to 0

Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
15.5.2
Multiprocessor Serial Data Reception
Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.12 shows an example of SCI operation for multiprocessor format reception.
Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data 1) D1 D7 Stop MPB bit 0
1
1
1 Idle state (mark state)
MPIE
RDRF
RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state
(a) Data does not match station's ID
1
Start bit 0 D0 D1
Data (ID2) D7
Stop MPB bit 1 1
Start bit 0 D0
Data (Data 2) D1 D7
Stop MPB bit 0
1
1 Idle state (mark state)
MPIE
RDRF
RDR value
ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine
Data 2 MPIE bit set to 1 again
(b) Data matches station's ID
Figure 15.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin [4] value.
Legend : Logical add (OR)
Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR
[2]
FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR
Yes
[3]
FER ORER = 1 No Read RDRF flag in SSR
Yes
No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 (Continued on next page)
[5] Error processing
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 15 Serial Communication Interface (SCI, IrDA)
[5]
Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
Clear ORER, PER, and FER flags in SSR to 0

Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 15 Serial Communication Interface (SCI, IrDA)
15.6
Operation in Clocked Synchronous Mode
Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling fullduplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer.
One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 15.14 Data Format in Synchronous Communication (LSB-First) 15.6.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.6.2
SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags in SSR, or RDR.
Start initialization
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, MPIE, TE, and RE to 0. [2] Set the data transfer format in SMR and SCMR.
[1]
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0)
[3] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
Set data transfer format in SMR and SCMR Set value in BRR Wait
[2]
[3]
No 1-bit interval elapsed? Yes
Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits
[4]

Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously.
Figure 15.15 Sample SCI Initialization Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
15.6.3
Serial Data Transmission (Clocked Synchronous Mode)
Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 15.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags.
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Section 15 Serial Communication Interface (SCI, IrDA)
Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization Start transmission
[1]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR.
Read TDRE flag in SSR
[2]
No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes [3]
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR to 0
Figure 15.17 Sample Serial Transmission Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
15.6.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled.
Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart for serial data reception.
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. However, the RDRF flag is cleared automatically when the DTC is initiated by a receive data full interrupt (RXI) and reads data from RDR.
Read ORER flag in SSR
[2]
Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR [4]
No RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0
No All data received? Yes Clear RE bit in SCR to 0 [5]
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
Figure 15.19 Sample Serial Reception Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
15.6.5
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1, clear the TE bit in SCR to 0. Then simultaneously set the TE and RE bits to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set the TE and RE bits to 1 with a single instruction.
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization Start transmission/reception
[1]
[1]
SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt.
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
[2]
[2]
[3]
Read ORER flag in SSR Yes [3] Error processing
ORER = 1 No
[4]
Read RDRF flag in SSR No RDRF = 1 Yes
[4]
[5] Serial transmission/reception continuation procedure: To continue serial transmission/ Read receive data in RDR, and reception, before the MSB (bit 7) of clear RDRF flag in SSR to 0 the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, No before the MSB (bit 7) of the current All data received? [5] frame is transmitted, read 1 from the TDRE flag to confirm that writing is Yes possible. Then write data to TDR and clear the TDRE flag to 0. However, the TDRE flag is checked Clear TE and RE bits in SCR to 0 and cleared automatically when the DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Similarly, the RDRF flag is cleared automatically when the DTC is initiated by a receive Note: When switching from transmit or receive operation to simultaneous data full interrupt (RXI) and reads transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. data from RDR.
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
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15.7
Smart Card Interface Description
The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register. 15.7.1 Sample Connection
Figure 15.21 shows a sample connection between the smart card and this LSI. As in the figure, since this LSI communicates with the IC card using a single transmission line, interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor. Setting the RE and TE bits in SCR to 1 with the IC card not connected enables closed transmission/reception allowing self diagnosis. To supply the IC card with the clock pulses generated by the SCI, input the SCK pin output to the CLK pin of the IC card. A reset signal can be supplied via the output port of this LSI.
VCC TxD RxD SCK Rx (port) This LSI Main unit of the device to be connected Data line Clock line Reset line I/O CLK RST IC card
Figure 15.21 Pin Connection for Smart Card Interface 15.7.2 Data Format (Except in Block Transfer Mode)
Figure 15.22 shows the data transfer formats in smart card interface mode. * One frame contains 8-bit data and a parity bit in asynchronous mode. * During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. * If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu has passed from the start bit. * If an error signal is sampled during transmission, the same data is automatically re-transmitted after two or more etu.
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Section 15 Serial Communication Interface (SCI, IrDA)
In normal transmission/reception
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
Output from the transmitting station
When a parity error is generated
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Output from the transmitting station Output from the receiving station Start bit Data bits Parity bit Error signal
Legend Ds: D0 to D7 : Dp: DE:
Figure 15.22 Data Formats in Normal Smart Card Interface Mode For communication with the IC cards of the direct convention and inverse convention types, follow the procedure below.
(Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) state
Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 15.23. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard.
(Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) state
Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1)
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Section 15 Serial Communication Interface (SCI, IrDA)
For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 15.24. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SINV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception. 15.7.3 Block Transfer Mode
Block transfer mode is different from normal smart card interface mode in the following respects. * If a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the bit before receiving the parity bit of the next frame. * During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. * Since the same data is not re-transmitted during transmission, the TEND flag in SSR is set 11.5 etu after transmission start. * Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred. 15.7.4 Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the internal baud rate generator can be used as a communication clock in smart card interface mode. In this mode, the SCI can operate using a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the falling edge of the start bit is sampled using the internal basic clock in order to perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in figure 15.25. The reception margin here is determined by the following formula.
M = (0.5 -
1 ) - (L - 0.5) F - 2N D - 0.5 (1 + F) x 100 [%] N
... Formula (1)
M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock rate deviation
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Section 15 Serial Communication Interface (SCI, IrDA)
Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is determined by the formula below.
M = (0.5 - 1/2 x 372) x 100 [%] = 49.866%
372 clock cycles 186 clock cycles 0 Internal basic clock 185 371 0 185 371 0
Receive data (RxD)
Start bit
D0
D1
Synchronization sampling timing
Data sampling timing
Figure 15.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) 15.7.5 Initialization
Before starting transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ORER, ERS, and PER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the SMIF bit is set to 1, the TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output clock pulses.
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Section 15 Serial Communication Interface (SCI, IrDA)
7.
Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least 1 bit interval. Setting prohibited the TE and RE bits to 1 simultaneously except for self diagnosis.
To switch from reception to transmission, first verify that reception has completed, and initialize the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception completion can be verified by reading the RDRF flag or PER and ORER flags. To switch from transmission to reception, first verify that transmission has completed, and initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag. 15.7.6 Serial Data Transmission (Except in Block Transfer Mode)
Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data is re-transmitted. Figure 15.26 shows the data re-transfer operation during transmission. 1. If an error signal from the receiving end is sampled after one frame of data has been transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled. 2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is re-transferred from TDR to TSR allowing automatic data retransmission. 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 15.28 shows a sample flowchart for transmission. All the processing steps are automatically performed using a TXI interrupt request to activate the DTC. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request when TIE in SCR is set. This activates the DTC by a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC. If an error occurs, the SCI automatically re-transmits the same data. During re-transmission, TEND remains as 0, thus not activating the DTC. Therefore, the SCI and DTC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC, be sure to set and enable it prior to making SCI settings. For DTC settings, see section 7, Data Transfer Controller (DTC).
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nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE)
(n + 1) th transfer frame
Ds D0 D1 D2 D3 D4
TDRE
Transfer from TDR to TSR
TEND
[2]
Transfer from TDR to TSR
Transfer from TDR to TSR
[3]
FER/ERS
[1] [3]
Figure 15.26 Data Re-transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR, which is shown in figure 15.27.
I/O data TXI (TEND interrupt)
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Guard time
12.5 etu
GM = 0
11.0 etu
GM = 1
[Legend] Ds: D0 to D7: Dp: DE: etu:
Start bit Data bits Parity bit Error signal Element Time Unit (time taken to transfer one bit)
Figure 15.27 TEND Flag Set Timings during Transmission
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Section 15 Serial Communication Interface (SCI, IrDA)
Start
Initialization Start transmission
ERS = 0? Yes
No
Error processing
No
TEND = 1? Yes
Write data to TDR and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes No ERS = 0? Yes
Error processing
No TEND = 1? Yes
Clear TE bit in SCR to 0
End
Figure 15.28 Sample Transmission Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
15.7.7
Serial Data Reception (Except in Block Transfer Mode)
Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 15.29 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1. 3. If no parity error is detected, the PER bit in SSR is not set to 1. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set. Figure 15.30 shows a sample flowchart for reception. All the processing steps are automatically performed using an RXI interrupt request to activate the DTC. In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates DTC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DTC activate beforehand. The RDRF flag is automatically cleared to 0 at data transfer by DTC. If an error occurs during reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be cleared. If an error occurs, DTC is not activated and receive data is skipped, therefore, the number of bytes of receive data specified in DTC are transferred. Even if a parity error occurs and PER is set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read. Note: For operations in block transfer mode, see section 15.4, Operation in Asynchronous Mode.
(n + 1) th transfer frame (DE) Ds D0 D1 D2 D3 D4
n th transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1]
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
[3]
[3]
Figure 15.29 Data Re-transfer Operation in SCI Reception Mode
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Section 15 Serial Communication Interface (SCI, IrDA)
Start
Initialization
Start reception
ORER = 0 and PER = 0?
No
Yes
Error processing
No
RDRF = 1? Yes
Read data from RDR and clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
Figure 15.30 Sample Reception Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
15.7.8
Clock Output Control
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 15.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 15.31 Clock Output Fixing Timing At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty ratio. * At Power-On: To secure the appropriate clock duty ratio simultaneously with power-on, use the following procedure. A. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. B. Fix the SCK pin to the specified output using the CKE1 bit in SCR. C. Set SMR and SCMR to enable smart card interface mode. D. Set the CKE0 bit in SCR to 1 to start clock output. * At Transition from Smart Card Interface Mode to Software Standby Mode: A. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK pins to the values for the output fixed state in software standby mode. B. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. C. Write 0 to the CKE0 bit in SCR to stop the clock. D. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty ratio retained.
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Section 15 Serial Communication Interface (SCI, IrDA)
E. Make the transition to software standby mode. * At Transition from Software Standby Mode to Smart Card Interface Mode: 1. Cancel software standby mode. 2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty ratio is then generated.
Software standby
Normal operation
Normal operation
[1] [2] [3]
[4] [5]
[1]
[2]
Figure 15.32 Clock Stop and Restart Procedure
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Section 15 Serial Communication Interface (SCI, IrDA)
15.8
IrDA Operation
IrDA operation can be used with SCI_1. Figure 15.33 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in SCICR, the TxD1 and RxD1 signals for SCI_1 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTxD and IrRxD pins). Connecting these pins to the infrared data transceiver achieves infrared data communication based on the system defined by the IrDA standard version 1.0. In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not incorporate the capability of automatic modification of the transfer rate; the transfer rate must be modified through programming.
IrDA TxD1/IrTxD RxD1/IrRxD Phase inversion Pulse encoder Pulse decoder Phase inversion TxD RxD SCI_1
KBCOMP
Figure 15.33 IrDA Block Diagram
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Section 15 Serial Communication Interface (SCI, IrDA)
(1)
Transmission
During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 15.34). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in KBCOMP. The output waveform can also be inverted using the IrTxINV bit in KBCOMP. The high-level pulse width is defined to be 1.41 s at the minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) +1.08 s at the maximum. For example, when the frequency of system clock is 20 MHz, a high-level pulse width of at least 1.41 s to 1.6 s can be specified. For serial data of level 1, no pulses are output.
UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1
0
Transmission
Reception
IR frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1
0
Bit cycle
Pulse width is 1.6 s to 3/16 bit cycle
Figure 15.34 IrDA Transmission and Reception
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Section 15 Serial Communication Interface (SCI, IrDA)
(2)
Reception
During reception, IR frames are converted to UART frames using the IrDA interface before inputting to SCI_1. Here, the input waveform can also be inverted using the IrRxINV bit in SCICR. Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 s, the minimum width allowed, the pulse is recognized as level 0.
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Section 15 Serial Communication Interface (SCI, IrDA)
(3)
High-Level Pulse Width Selection
Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 15.12 IrCKS2 to IrCKS0 Bit Settings
Operating Frequency (MHz) 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 16.9344 17.2032 18 19.6608 20 2400 78.13 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 Bit Rate (bps) (Upper Row) / Bit Interval x 3/16 (s) (Lower Row) 9600 19.53 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 19200 9.77 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 38400 4.88 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 57600 3.26 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 115200 1.63 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101
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Section 15 Serial Communication Interface (SCI, IrDA)
15.9
15.9.1
Interrupt Sources
Interrupts in Normal Serial Communication Interface Mode
Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DTC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 15.13 SCI Interrupt Sources
Channel 1 Name ERI1 RXI1 TXI1 TEI1 2 ERI2 RXI2 TXI2 TEI2 Interrupt Source Receive error Receive data full Transmit data empty Transmit end Receive error Receive data full Transmit data empty Transmit end Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND DTC Activation Disable Enable Enable Disable Disable Enable Enable Disable Low Priority High
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Section 15 Serial Communication Interface (SCI, IrDA)
15.9.2
Interrupts in Smart Card Interface Mode
Table 15.14 shows the interrupt sources in smart card interface mode. A TEI interrupt request cannot be used in this mode. Table 15.14 SCI Interrupt Sources
Channel 1 Name ERI1 RXI1 TXI1 2 ERI2 RXI2 TXI2 Interrupt Source Receive error, error signal detection Receive data full Transmit data empty Receive error, error signal detection Receive data full Transmit data empty Interrupt Flag ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND DTC Activation Priority Disable Enable Enable Disable Enable Enable Low High
Data transmission/reception using the DTC is also possible in smart card interface mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request. This activates the DTC by a TXI interrupt request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC. If an error occurs, the SCI automatically re-transmits the same data. During retransmission, the TEND flag remains as 0, thus not activating the DTC. Therefore, the SCI and DTC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC, be sure to set and enable the DTC prior to making SCI settings. For DTC settings, see section 7, Data Transfer Controller (DTC). In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This activates the DTC by an RXI interrupt request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DTC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DTC. If an error occurs, the RDRF flag is not set but the error flag is set. Therefore, the DTC is not activated and an ERI interrupt request is issued to the CPU instead; the error flag must be cleared.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.10
Usage Notes
15.10.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 24, Power-Down Modes. 15.10.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 15.10.3 Mark State and Break Sending When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR of the port. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) is SSR is set to 1, even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit in SCR is cleared to 0. 15.10.5 Relation between Writing to TDR and TDRE Flag Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.10.6 Restrictions on Using DTC When the external clock source is used as a synchronization clock, update TDR by the DTC and wait for at least five clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 15.35). When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC activation source.
SCK
t
TDRE LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
D7
Note: When external clock is supplied, t must be more than four clock cycles.
Figure 15.35 Sample Transmission using DTC in Clocked Synchronous Mode 15.10.7 SCI Operations during Mode Transitions (1) Transmission
Before making the transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode is cancelled and then the TE is set to 1 again. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 15.36 shows a sample flowchart for mode transition during transmission. Figures 15.37 and 15.38 show the pin states during transmission. Before making the transition from the transmission mode using DTC transfer to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting
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Section 15 Serial Communication Interface (SCI, IrDA)
TE and TIE to 1 after mode cancellation generates a TXI interrupt request to start transmission using the DTC.
Transmission
All data transmitted? Yes Read TEND flag in SSR
No
[1]
TEND = 1 Yes TE = 0 [2]
No
[1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after mode cancellation; however, if the DTC has been initiated, the data remaining in DTC RAM will be transmitted when TE and TIE are set to 1. [2] Also clear TIE and TEIE to 0 when they are 1.
Make transition to software standby mode etc. Cancel software standby mode etc.
[3]
[3] Module stop, watch, sub-active, and sub-sleep modes are included.
Change operating mode? Yes Initialization
No
TE = 1
Start transmission
Figure 15.36 Sample Flowchart for Mode Transition during Transmission
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Section 15 Serial Communication Interface (SCI, IrDA)
Transmission start
Transition to Software standby Transmission end software standby mode cancelled mode
TE bit SCK output pin TxD output pin
Port input/output Port input/output
High output
Start SCI TxD output
Stop
Port input/output Port
High output SCI TxD output
Port
Figure 15.37 Pin States during Transmission in Asynchronous Mode (Internal Clock)
Transition to Software standby software standby mode cancelled mode
Transmission start
Transmission end
TE bit SCK output pin TxD output pin
Port input/output
Port input/output
Marking output SCI TxD output
Last TxD bit retained
Port input/output Port
High output* SCI TxD output
Port Note: Initialized in software standby mode
Figure 15.38 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock)
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Section 15 Serial Communication Interface (SCI, IrDA)
(2)
Reception
Before making the transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 15.39 shows a sample flowchart for mode transition during reception.
Reception
Read RDRF flag in SSR
RDRF = 1 Yes Read receive data in RDR
No
[1]
[1] Data being received will be invalid.
RE = 0 [2]
[2] Module stop, watch, sub-active, and subsleep modes are included.
Make transition to software standby mode etc. Cancel software standby mode etc.
Change operating mode? Yes Initialization
No
RE = 1
Start reception
Figure 15.39 Sample Flowchart for Mode Transition during Reception
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Section 15 Serial Communication Interface (SCI, IrDA)
15.10.8 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 15.40.
Low pulse of half a cycle SCK/Port 1. Transmission end Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 3. C/A = 0 4. Low pulse output
Figure 15.40 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins, specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1. 1. 2. 3. 4. 5. End serial data transmission TE bit = 0 CKE1 bit = 1 C/A bit = 0 (switch to port output) CKE1 bit = 0
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Section 15 Serial Communication Interface (SCI, IrDA)
High output SCK/Port 1. Transmission end Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0
Figure 15.41 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins
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Section 16 I C Bus Interface (IIC)
2
Section 16 I2C Bus Interface (IIC)
This LSI has a two-channel I2C bus interface. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however.
16.1
Features
* Selection of addressing format or non-addressing format I2C bus format: addressing format with an acknowledge bit, for master/slave operation Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master operation only * Conforms to Philips I2C bus interface (I2C bus format) * Two ways of setting slave address (I2C bus format) * Start and stop conditions generated automatically in master mode (I2C bus format) * Selection of the acknowledge output level in reception (I2C bus format) * Automatic loading of an acknowledge bit in transmission (I2C bus format) * Wait function in master mode (I2C bus format) A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. * Wait function (I2C bus format) A wait request can be generated by driving the SCL pin low after data transfer. The wait request is cleared when the next transfer becomes possible. * Interrupt sources Data transfer end (including when a transition to transmit mode with I2C bus format occurs, when ICDR data is transferred from ICDRT to ICDRS or from ICDRS to ICDRR, or during a wait state) Address match: When any slave address matches or the general call address is received in slave receive mode with I2C bus format (including address reception after loss of master arbitration) Arbitration lost Start condition detection (in master mode) Stop condition detection (in slave mode)
IFIIC60B_000020020800
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Section 16 I C Bus Interface (IIC)
2
* Selection of 16 internal clocks (in master mode) * Direct bus drive (SCL/SDA pin) Eight pins--P52/SCL0, P97/SDA0, P86/SCL1, P42/SDA1, PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB --(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected.
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Section 16 I C Bus Interface (IIC)
2
Figure 16.1 shows a block diagram of the I2C bus interface. Figure 16.2 shows an example of I/O pin connections to external circuits. Since I2C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages. For details, see section 26, Electrical Characteristics.
ICXR
* SCL ExSCLA ExSCLB
PS Clock control
ICCR
Noise canceler
ICMR
Bus state decision circuit Arbitration decision circuit * SDA ExSDAA ExSDAB Output data control circuit
ICSR
ICDRT ICDRS ICDRR
Noise canceler Address comparator Note : * An input/output pin can be selected among three pins.
SAR, SARX
[Legend] ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register ICXR: I2C bus extended control register Slave address register SAR: SARX: Slave address register X Prescaler PS:
Interrupt generator
Figure 16.1 Block Diagram of I2C Bus Interface
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Internal data bus
Interrupt request
Section 16 I C Bus Interface (IIC)
2
VDD VCC
VCC
SCL SCL in SCL out SDA
SCL
SDA
SDA in SDA out (Master) This LSI
SCL SDA
SCL in SCL out
SCL in SCL out
SDA in SDA out (Slave 1)
SDA in SDA out (Slave 2)
Figure 16.2 I2C Bus Interface Connections (Example: This LSI as Master)
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SCL SDA
Section 16 I C Bus Interface (IIC)
2
16.2
Input/Output Pins
Table 16.1 summarizes the input/output pins used by the I2C bus interface. One of three pins can be specified as SCL and SDA input/output pin of each channel. Two or more input/output pins should not be specified for one channel. For the method of setting pins, see section 8.17.2, Port Control Register 1 (PTCNT1). Table 16.1 Pin Configuration
Channel 0 Symbol* SCL0 SDA0 1 SCL1 SDA1 ExSCLA ExSDAA ExSCLB ExSDAB Note: * Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Function Serial clock input/output pin of IIC_0 Serial data input/output pin of IIC_0 Serial clock input/output pin of IIC_1 Serial data input/output pin of IIC_1 Serial clock input/output pin of IIC_0 or IIC_1 Serial data input/output pin of IIC_0 or IIC_1 Serial clock input/output pin of IIC_0 or IIC_1 Serial data input/output pin of IIC_0 or IIC_1
In the text, the channel subscript is omitted, and only SCL and SDA are used.
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Section 16 I C Bus Interface (IIC)
2
16.3
Register Descriptions
The I2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). * I2C bus control register (ICCR) * I2C bus status register (ICSR) * I2C bus data register (ICDR) * I2C bus mode register (ICMR) * Slave address register (SAR) * Second slave address register (SARX) * I2C bus extended control register (ICXR) * DDC switch register (DDCSWR)* Note: DDCSWR is available in IIC_0. 16.3.1 I2C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is internally divided into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among these three registers are performed automatically in accordance with changes in the bus state, and they affect the status of internal flags such as ICDRE and ICDRF. In master transmit mode with the I2C bus format, writing transmit data to ICDR should be performed after start condition detection. When the start condition is detected, previous write data is ignored. In slave transmit mode, writing should be performed after the slave addresses match and the TRS bit is automatically changed to 1. If the IIC is in transmit mode (TRS = 1) and ICDRT has the next data (the ICDRE flag is 0), data is transferred automatically from ICDRT to ICDRS, following transmission of one frame of data using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is transferred automatically from ICDRT to ICDRS by writing to ICDR. If I2C is in receive mode (TRS = 0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to ICDR in receive mode. Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR.
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Section 16 I C Bus Interface (IIC)
2
If I2C is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is transferred automatically from ICDRS to ICDRR, following reception of one frame of data using ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from ICDRS to ICDRR. Always set I2C to receive mode before reading from ICDR. If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1. ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value of ICDR is undefined. 16.3.2 Slave Address Register (SAR)
SAR sets the slave address and selects the communication format. If the LSI is in slave mode with the I2C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to 0.
Bit Bit Name 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Format Select Selects the communication format together with the FSX bit in SARX. See table 16.2. This bit should be set to 0 when general call address recognition is performed. Description Slave Address 6 to 0 Set a slave address.
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Section 16 I C Bus Interface (IIC)
2
16.3.3
Second Slave Address Register (SARX)
SARX sets the second slave address and selects the communication format. If the LSI is in slave mode, when received address matches the second slave address, transmission/reception using the DTC is enabled. If the LSI is in slave mode with the I2C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SARX can be accessed only when the ICE bit in ICCR is cleared to 0.
Bit Bit Name 7 6 5 4 3 2 1 0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX Initial Value R/W 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W Format Select X Selects the communication format together with the FS bit in SAR. See table 16.2. Description Second Slave Address 6 to 0 Set the second slave address.
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Section 16 I C Bus Interface (IIC)
2
Table 16.2 Communication Format
SAR FS 0 SARX FSX 0 Operating Mode I2C bus format * * 1
2
SAR and SARX slave addresses recognized General call address recognized SAR slave address recognized SARX slave address ignored General call address recognized SAR slave address ignored SARX slave address recognized General call address ignored
I C bus format * * *
1
0
I C bus format * * *
2
1
Clocked synchronous serial format * * SAR and SARX slave addresses ignored General call address ignored
* I2C bus format: addressing format with an acknowledge bit * Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master mode only
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Section 16 I C Bus Interface (IIC)
2
16.3.4
I2C Bus Mode Register (ICMR)
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1.
Bit Bit Name 7 MLS Initial Value R/W 0 R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit This bit is valid only in master mode with the I C bus format. 0: Data and the acknowledge bit are transferred consecutively with no wait inserted. 1: After the fall of the clock for the final data bit (8th clock), the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. For details, see section 16.4.7, IRIC Setting Timing and SCL Control. 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Transfer Clock Select 2 to 0 These bits are used only in master mode. These bits select the required transfer rate, together with the IICX1 (IIC_1) and IICX0 (IIC_0) bits in STCR. See table 16.3.
2 2
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Bit Bit Name 2 1 0 BC2 BC1 BC0
Initial Value R/W 0 0 0 R/W R/W R/W
Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to B'000 when a start condition is detected. The value returns to B'000 at the end of a data transfer. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits
2
Clocked Synchronous Serial Mode 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits
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Section 16 I C Bus Interface (IIC)
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Table 16.3 I2C Transfer Rate
STCR Bits 5 and 6 IICX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 5 CKS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
ICMR Bit 4 CKS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 3 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 = 5 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz Transfer Rate = 10 MHz = 16 MHz = 20 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 571 kHz* 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 714 kHz* 500 kHz* 417 kHz* 3136 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz
Note:
*
Correct operation cannot be guaranteed since the transfer rate is beyond the I2C bus interface specification (normal mode: maximum 100 kHz, high-speed mode: maximum 400 kHz).
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Section 16 I C Bus Interface (IIC)
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16.3.5
I2C Bus Control Register (ICCR)
ICCR controls the I2C bus interface and performs interrupt flag confirmation.
Bit 7 Bit Name Initial Value R/W ICE 0 R/W Description I2C Bus Interface Enable 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed. 1: I2C bus interface modules can perform transfer operation, and the ports function as the SCL and SDA input/output pins. ICMR and ICDR can be accessed. 6 IEIC 0 R/W I2C Bus Interface Interrupt Enable 0: Disables interrupts from the I C bus interface to the CPU 1: Enables interrupts from the I C bus interface to the CPU. 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select MST TRS 0 0 1 1 0: Slave receive mode 1: Slave transmit mode 0: Master receive mode 1: Master transmit mode
2 2 2 2
Both these bits will be cleared by hardware when they lose 2 in a bus contention in master mode with the I C bus format. 2 In slave receive mode with I C bus format, the R/W bit in the first frame immediately after the start condition sets these bits in receive mode or transmit mode automatically by hardware. Modification of the TRS bit during transfer is deferred until transfer is completed, and the changeover is made after completion of the transfer.
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Section 16 I C Bus Interface (IIC)
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Bit 5 4
Bit Name Initial Value R/W MST TRS 0 0 R/W R/W
Description [MST clearing conditions] 1. When 0 is written by software 2. When lost in bus contention in I2C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2. When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] 1. When 0 is written by software (except for TRS setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (for TRS setting condition 3) 3. When lost in bus contention in I C bus format master mode [TRS setting conditions] 1. When 1 is written by software (except for TRS clearing condition 3) 2. When 1 is written in TRS after reading TRS = 0 (for TRS clearing condition 3) 3. When 1 is received as the R/W bit after the first frame address matching in I2C bus format slave mode
2
3
ACKE
0
R/W
Acknowledge Bit Decision and Selection 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit in ICSR, which is always 0. 1: If the received acknowledge bit is 1, continuous transfer is halted. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance.
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Bit 2 0
Bit Name Initial Value R/W BBSY SCP 0 1 R/W* W
1
Description Bus Busy Start Condition/Stop Condition Prohibit In master mode: * * Writing 0 in BBSY and 0 in SCP: A stop condition is issued Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued Writing to the BBSY flag is disabled.
In slave mode: * [BBSY setting condition] When the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. [BBSY clearing condition] When the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. To issue a start/stop condition, use the MOV instruction. The I C bus interface must be set in master transmit mode before the issue of a start condition. Set MST to 1 and TRS to 1 before writing 1 in BBSY and 0 in SCP. The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. The SCP bit is always read as 1. If 0 is written, the data is not stored.
2 2
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Section 16 I C Bus Interface (IIC)
2
Bit 1
Bit Name Initial Value R/W IRIC 0 R/(W)*
2
Description I2C Bus Interface Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See section 16.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. [Setting conditions] I C bus format master mode: * When a start condition is detected in the bus line state after a start condition is issued (when the ICDRE flag is set to 1 because of first frame transmission) When a wait is inserted between the data and acknowledge bit when the WAIT bit is 1 (fall of the 8th transmit/receive clock) At the end of data transfer (rise of the 9th transmit/receive clock while no wait is inserted) When a slave address is received after bus arbitration is lost (the first frame after the start condition) If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) when the ACKE bit is 1 When the AL flag is set to 1 after bus arbitration is lost while the ALIE bit is 1 When the slave address (SVA or SVAX) matches (when the AAS or AASX flag in ICSR is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (rise of the 9th transmit/receive clock) When the general call address is detected (when 0 is received as the R/W bit and the ADZ flag in ICSR is set to 1) and at the end of data reception up to the subsequent retransmission start condition or stop condition detection (rise of the 9th receive clock) If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) while the ACKE bit is 1 When a stop condition is detected (when the STOP or ESTP flag in ICSR is set to 1) while the STOPIM bit is 0
2 2
*
* * * *
2
I C bus format slave mode: *
*
* *
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Section 16 I C Bus Interface (IIC)
2
Bit Bit Name Initial Value R/W 1 IRIC 0 R/(W) *
2
Description Clocked synchronous serial format mode: * * At the end of data transfer (rise of the 8th transmit/receive) When a start condition is detected
When the ICDRE or ICDRF flag is set to 1 in any operating mode: * When a start condition is detected in transmit mode (when a start condition is detected in transmit mode and the ICDRE flag is set to 1) When data is transferred among the ICDR register and buffer (when data is transferred from ICDRT to ICDRS in transmit mode and the ICDRE flag is set to 1, or when data is transferred from ICDRS to ICDRR in receive mode and the ICDRF flag is set to 1) When 0 is written in IRIC after reading IRIC = 1 When ICDR is read/written by the DTC (in some cases, this condition does not work as clearing condition, therefore, for details see following explanation on the operation of DTC)
*
[Clearing conditions] * *
Notes: 1. The value of the BBSY flag is not changed even though it is written to. 2. Only 0 can be written, to clear the flag.
Using DTC clears the IRIC flag automatically and enables consecutive transfer without CPU. When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag which is a DTC activation source is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (SVA) or general call address match in I2C bus format slave mode. Even if the IRIC and IRTR flags are set, the ICDRE flag or ICDRF flag may not be set. In the case of continuous transfer by using the DTC, the IRIC and IRTR flags are not cleared after the specified number of transfers is completed. While, as the specified number of reading/writing ICDR has been completed, reading/writing of the ICDRE or ICDRF flag is cleared.
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Section 16 I C Bus Interface (IIC)
2
Tables 16.4 and 16.5 show the relationship between the flags and the transfer states. Table 16.4 Flags and Transfer States (Master Mode)
MST 1 TRS 1 BBSY ESTP 0 0 STOP 0 IRTR 0 AASX AL 0 0 AAS 0 ADZ 0 ACKB ICDRF ICDRE State 0 -- 0 Idle state (flag clearing required) Start condition detected Wait state Transmission end (ACKE=1 and ACKB=1) Transmission end with ICDRE=0 ICDR write with the above state Transmission end with ICDRE=1 ICDR write with the above state or after start condition detected Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF=0 ICDR read with the above state Reception end with ICDRF=1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state
1 1 1
1 -- 1
1 1 1
0 0 0
0 0 0
1 -- --
0 0 0
0 0 0
0 0 0
0 0 0
0 -- 1
-- -- --
1 -- --
1
1
1
0
0
1
0
0
0
0
0
--
1
1 1
1 1
1 1
0 0
0 0
-- --
0 0
0 0
0 0
0 0
0 0
-- --
0 1
1
1
1
0
0
--
0
0
0
0
0
--
0
1
1
1
0
0
1
0
0
0
0
0
--
1
1 1 1 1 1
0 0 0 0 0
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0
1 -- -- -- 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
-- -- -- -- --
1 0 1 0 1
-- -- -- -- --
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Section 16 I C Bus Interface (IIC)
MST 0 1 TRS 0 -- BBSY 1 0 ESTP 0 0 STOP 0 0 IRTR -- -- AASX 0 0 AL 1 0 AAS 0 0 ADZ 0 0 ACKB ICDRF ICDRE State -- -- -- -- -- 0 Arbitration lost Stop condition detected
2
[Legend] 0: 0-state retained 1: 1-state retained --: Previous state retained Cleared to 0 0: Set to 1 1:
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Section 16 I C Bus Interface (IIC)
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Table 16.5 Flags and Transfer States (Slave Mode)
MST 0 TRS 0 BBSY ESTP 0 0 STOP 0 IRTR 0 AASX AL 0 0 AAS 0 ADZ 0 ACKB ICDRF ICDRE State 0 -- 0 Idle state (flag clearing required) Start condition detected SAR match in first frame (SARXSAR) General call address match in first frame (SARXH'00) SAR match in first frame (SARSARX) Transmission end (ACKE=1 and ACKB=1) Transmission end with ICDRE=0 ICDR write with the above state Transmission end with ICDRE=1 ICDR write with the above state Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF=0 ICDR read with the above state
0 0
0 1/0 *1 0
1 1
0 0
0 0
0 0
0 0
0 --
0 1
0 0
0 0
-- 1
1 1
0
1
0
0
0
0
--
1
1
0
1
1
0
1/0 *1 1
1
0
0
1
1
--
0
0
0
1
1
0
1
0
0
--
--
--
--
0
1
--
--
0
1
1
0
0
1/0 *2 -- --
--
--
--
0
0
--
1
0 0
1 1
1 1
0 0
0 0
-- --
0 --
0 --
0 1
0 0
--
0 1
0 0
1 1
1 1
0 0
0 0
-- 1/0 *2
-- --
0 0
0 0
0 0
0 0
0 1
0 0
0 0
1 1
0 0
0 0
1/0 *2 --
-- --
-- 0
-- 0
-- 0
-- --
1 0
-- --
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Section 16 I C Bus Interface (IIC)
MST 0 0 TRS 0 0 BBSY 1 1 ESTP 0 0 STOP 0 0 IRTR -- -- AASX -- -- AL -- 0 AAS -- 0 ADZ -- 0 ACKB ICDRF ICDRE State -- -- 1 0 -- -- Reception end with ICDRF=1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state Stop condition detected
2
0
0
1
0
0
1/0 *2
--
0
0
0
--
1
--
0
--
0
1/0 *3
0/1 *3
--
--
--
--
--
--
--
0
[Legend] 0: 0-state retained 1: 1-state retained --: Previous state retained Cleared to 0 0: Set to 1 1: Notes: 1. Set to 1 when 1 is received as a R/W bit following an address. 2. Set to 1 when the AASX bit is set to 1. 3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.
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Section 16 I C Bus Interface (IIC)
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16.3.6
I2C Bus Status Register (ICSR)
ICSR consists of status flags. Also see tables 16.4 and 16.5.
Bit Bit Name 7 ESTP Initial Value R/W 0 Description
2
R/(W)* Error Stop Condition Detection Flag This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer. [Clearing conditions] * * When 0 is written in ESTP after reading ESTP = 1 When the IRIC flag in ICCR is cleared to 0
2
6
STOP
0
R/(W)* Normal Stop Condition Detection Flag This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected after frame transfer completion. [Clearing conditions] * * When 0 is written in STOP after reading STOP = 1 When the IRIC flag is cleared to 0
5
IRTR
0
R/(W)* I C Bus Interface Continuous Transfer Interrupt Request Flag Indicates that the I2C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. [Setting conditions] I C bus format slave mode: * When the ICDRE or ICDRF flag in ICDR is set to 1 when AASX = 1
2
2
Master mode or clocked synchronous serial format mode with I2C bus format: * * *
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When the ICDRE or ICDRF flag is set to 1 When 0 is written after reading IRTR = 1 When the IRIC flag is cleared to 0 while ICE is 1
[Clearing conditions]
Section 16 I C Bus Interface (IIC)
2
Bit Bit Name 4 AASX
Initial Value R/W 0
Description
2
R/(W)* Second Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. [Setting condition] When the second slave address is detected in slave receive mode and FSX = 0 in SARX [Clearing conditions] * * * When 0 is written in AASX after reading AASX = 1 When a start condition is detected In master mode
3
AL
0
R/(W)* Arbitration Lost Flag Indicates that arbitration was lost in master mode. [Setting conditions] When ALSL=0 * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the internal SCL line is high at the fall of SCL in master mode If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the SDA pin is driven low by another device before 2 the I C bus interface drives the SDA pin low, after the start condition instruction was executed in master transmit mode When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AL after reading AL = 1
When ALSL=1 * *
[Clearing conditions] * *
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Section 16 I C Bus Interface (IIC)
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Bit Bit Name 2 AAS
Initial Value R/W 0
Description
2
R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. [Setting condition] When the slave address or general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 in SAR [Clearing conditions] * * * When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AAS after reading AAS = 1 In master mode
2
1
ADZ
0
R/(W)* General Call Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). [Setting condition] When the general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 or FSX = 0 [Clearing conditions] * * * When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in ADZ after reading ADZ = 1 In master mode
If a general call address is detected while FS=1 and FSX=0, the ADZ flag is set to 1; however, the general call address is not recognized (AAS flag is not set to 1).
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Section 16 I C Bus Interface (IIC)
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Bit Bit Name 0 ACKB
Initial Value R/W 0 R/W
Description Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] When 1 is received as the acknowledge bit when ACKE=1 in transmit mode [Clearing conditions] * * When 0 is received as the acknowledge bit when ACKE=1 in transmit mode When 0 is written to the ACKE bit
Receive mode: 0: Returns 0 as acknowledge data after data reception 1: Returns 1 as acknowledge data after data reception When this bit is read, the value loaded from the bus line (returned by the receiving device) is read in transmission (when TRS = 1). In reception (when TRS = 0), the value set by internal software is read. When this bit is written, acknowledge data that is returned after receiving is rewritten regardless of the TRS value. If the ICSR register bit is written using bit-manipulation instructions, the acknowledge data should be re-set since the acknowledge data setting is rewritten by the ACKB bit reading value. Write the ACKE bit to 0 to clear the ACKB flag to 0, before transmission is ended and a stop condition is issued in master mode, or before transmission is ended and SDA is released to issue a stop condition by a master device. Note: * Only 0 can be written to clear the flag.
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Section 16 I C Bus Interface (IIC)
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16.3.7
DDC Switch Register (DDCSWR)
DDCSWR controls IIC internal latch clearance.
Bit Bit Name Initial Value R/W Description All 0 0 1 1 1 1 R/W Reserved The initial value should not be changed. 4 3 2 1 0 -- CLR3 CLR2 CLR1 CLR0 R W* W* W* W* Reserved IIC Clear 3 to 0 Controls initialization of the internal state of IIC_0 and IIC_1. 00--: Setting prohibited 0100: Setting prohibited 0101: IIC_0 internal latch cleared 0110: IIC_1 internal latch cleared 0111: IIC_0 and IIC_1 internal latches cleared 1---: Invalid setting When a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module, and the internal state of the IIC module is initialized. These bits can only be written to; they are always read as 1. Write data to this bit is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. When clearing is required again, all the bits must be written to in accordance with the setting. Note: * This bit is always read as 1.
7 to 5 --
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Section 16 I C Bus Interface (IIC)
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16.3.8
I2C Bus Extended Control Register (ICXR)
ICXR enables or disables the I2C bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations.
Bit Bit Name 7 STOPIM Initial Value R/W 0 R/W Description Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the stop condition is detected in slave mode. 0: Enables IRIC flag setting and interrupt generation when the stop condition is detected (STOP = 1 or ESTP = 1) in slave mode. 1: Disables IRIC flag setting and interrupt generation when the stop condition is detected. 6 HNDS 0 R/W Handshake Receive Operation Select Enables or disables continuous receive operation in receive mode. 0: Enables continuous receive operation 1: Disables continuous receive operation When the HNDS bit is cleared to 0, receive operation is performed continuously after data has been received successfully while ICDRF flag is 0. When the HNDS bit is set to 1, SCL is fixed to the low level and the next data transfer is disabled after data has been received successfully while the ICDRF flag is 0. The bus line is released and next receive operation is enabled by reading the receive data in ICDR.
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Section 16 I C Bus Interface (IIC)
2
Bit Bit Name 5 ICDRF
Initial Value R/W 0 R
Description Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] * When data is received successfully and transferred from ICDRS to ICDRR.
(1) When data is received successfully while ICDRF = 0 (at the rise of the 9th clock pulse). (2) When ICDR is read successfully in receive mode after data was received while ICDRF = 1. [Clearing conditions] * * * When ICDR (ICDRR) is read. When 0 is written to the ICE bit. When the IIC is internally initialized using the CLR3 to CLR0 bits in DDCSWR.
When ICDRF is set due to the condition (2) above, ICDRF is temporarily cleared to 0 when ICDR (ICDRR) is read; however, since data is transferred from ICDRS to ICDRR immediately, ICDRF is set to 1 again. Note that ICDR cannot be read successfully in transmit mode (TRS = 1) because data is not transferred from ICDRS to ICDRR. Be sure to read data from ICDR in receive mode (TRS = 0).
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Bit Bit Name 4 ICDRE
Initial Value R/W 0 R
Description Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to. [Setting conditions] * * When the start condition is detected from the bus line 2 state with I C bus format or serial format. When data is transferred from ICDRT to ICDRS. 1. When data transmission completed while ICDRE = 0 (at the rise of the 9th clock pulse). 2. When data is written to ICDR in transmit mode after data transmission was completed while ICDRE = 1. [Clearing conditions] * * * * When data is written to ICDR (ICDRT). When the stop condition is detected with I2C bus format or serial format. When 0 is written to the ICE bit. When the IIC is internally initialized using the CLR3 to CLR0 bits in DDCSWR.
Note that if the ACKE bit is set to 1 with I2C bus format thus enabling acknowledge bit decision, ICDRE is not set when data transmission is completed while the acknowledge bit is 1. When ICDRE is set due to the condition (2) above, ICDRE is temporarily cleared to 0 when data is written to ICDR (ICDRT); however, since data is transferred from ICDRT to ICDRS immediately, ICDRE is set to 1 again. Do not write data to ICDR when TRS = 0 because the ICDRE flag value is invalid during the time.
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Bit Bit Name 3 ALIE
Initial Value R/W 0 R/W
Description Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost.
2
ALSL
0
R/W
Arbitration Lost Condition Select Selects the condition under which arbitration is lost. 0: When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL, or when the SCL pin is driven low by another device. 1: When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL, or when the SDA line is driven low by another device in idle state or after the start condition instruction was executed.
1 0
FNC1 FNC0
0 0
R/W R/W
Function Bit Cancels some restrictions on usage. For details, see section 16.6, Usage Notes. 00: Restrictions on operation remaining in effect 01: Setting prohibited 10: Setting prohibited 11: Restrictions on operation canceled
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16.4
Operation
The I2C bus interface has an I2C bus format and a serial format. 16.4.1 I2C Bus Data Format
The I2C bus format is an addressing format with an acknowledge bit. This is shown in figure 16.3. The first frame following a start condition always consists of 9 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 16.4. Figure 16.5 shows the I2C bus timing. The symbols used in figures 16.3 to 16.5 are explained in table 16.6.
(a) FS = 0 or FSX = 0 S 1 SLA 7 1 (b) Start condition retransmission FS = 0 or FSX = 0 S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 Upper row: Transfer bit count (n1, n2 = 1 to 8) Lower row: Transfer frame count (m1, m2 = from 1) A/A 1 P 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1)
Figure 16.3 I2C Bus Data Format (I2C Bus Format)
FS=1 and FSX=1 S 1 DATA 8 1 DATA n m P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1)
Figure 16.4 I2C Bus Data Format (Serial Format)
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SDA
SCL 1-7 S SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A/A P
Figure 16.5 I2C Bus Timing Table 16.6 I2C Bus Data Format Symbols
Legend S SLA R/W A Start condition. The master device drives SDA from high to low while SCL is high Slave address. The master device selects the slave device. Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The slave device returns acknowledge in master transmit mode, and the master device returns acknowledge in master receive mode.) Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR. Stop condition. The master device drives SDA from low to high while SCL is high
DATA P
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16.4.2
Initialization
Initialize the IIC by the procedure shown in figure 16.6 before starting transmission/reception of data.
Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) (MSTPCRL) Set IICE = 1 in STCR Set ICE = 0 in ICCR Set SAR and SARX Set ICE = 1 in ICCR Set ICSR Set STCR Set ICMR Set ICXR Set ICCR
Cancel module stop mode
Enable the CPU accessing to the IIC control register and data register Enable SAR and SARX to be accessed Set the first and second slave addresses and IIC communication format (SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX) Enable ICMR and ICDR to be accessed Use SCL/SDA pin as an IIC port Set acknowledge bit (ACKB) Set transfer rate (IICX) Set communication format, wait insertion, and transfer rate (MLS, WAIT, CKS2 to CKS0) Enable interrupt, set communication operation (STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0) Set interrupt enable, transfer mode, and acknowledge decision (IEIC, MST, TRS, and ACKE)
<< Start transmit/receive operation >>
Figure 16.6 Sample Flowchart for IIC Initialization Note: Be sure to modify the ICMR register after transmit/receive operation has been completed. If the ICMR register is modified during transmit/receive operation, bit counter BC2 to BC0 will be modified erroneously, thus causing incorrect operation. 16.4.3 Master Transmit Operation
In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. Figure 16.7 shows the sample flowchart for the operations in master transmit mode.
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Start Initialize IIC Read BBSY flag in ICCR No [2] Test the status of the SCL and SDA lines. BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Set BBSY =1 and SCP = 0 in ICCR Read IRIC flag in ICCR [5] Wait for a start condition generation No IRIC = 1? Yes Write transmit data in ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR No IRIC = 1? Yes Read ACKB bit in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data in ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR [10] Wait for 1 byte to be transmitted. No IRIC = 1? Yes Read ACKB bit in ICSR [11] Determine end of tranfer No
End of transmission? (ACKB = 1?)
[1] Initialization
[3] Select master transmit mode.
[4] Start condition issuance
[6] Set transmit data for the first byte (slave address + R/W). (After writing to ICDR, clear IRIC flag continuously.) [7] Wait for 1 byte to be transmitted.
No
[8] Test the acknowledge bit transferred from the slave device.
No
Master receive mode [9] Set transmit data for the second and subsequent bytes. (After writing to ICDR, clear IRIC flag continuously.)
Yes Clear IRIC flag in ICCR Set BBSY = 0 and SCP = 0 in ICCR End [12] Stop condition issuance
Figure 16.7 Sample Flowchart for Operations in Master Transmit Mode
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The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR (ICDRT) write operations, are described below. 1. 2. 3. 4. Initialize the IIC as described in section 16.4.2, Initialization. Read the BBSY flag in ICCR to confirm that the bus is free. Set bits MST and TRS to 1 in ICCR to select master transmit mode. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. 5. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 6. Write the data (slave address + R/W) to ICDR. With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction (R/W). To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR, clear IRIC continuously so no other interrupt handling routine is executed. If the time for transmission of one frame of data has passed before the IRIC clearing, the end of transmission cannot be determined. The master device sequentially sends the transmission clock and the data written to ICDR. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. 7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the transmit operation. 9. Write the transmit data to ICDR. As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is performed in synchronization with the internal clock. 10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still data to be transmitted, go to step [9] to continue the next transmission operation. When the slave device has not acknowledged (ACKB bit is set to 1), operate step [12] to end transmission.
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12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
Start condition generation SCL (master output) SDA (master output) SDA (slave output) ICDRE 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [7] A 9 1 Bit 7 2 Bit 6
Slave address [5]
Data 1
IRIC
Interrupt request
Interrupt request
IRTR
ICDRT
Address + R/W
Data 1
ICDRS
Address + R/W
Data 1
Note:* Data write in ICDR prohibited User processing [4] BBSY set to 1 [6] ICDR write SCP cleared to 0 (start condition issuance) [6] IRIC clear [9] ICDR write [9] IRIC clear
Figure 16.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)
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Stop condition issuance SCL (master output) 8 9 1 Bit 7 [7] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [10] A 9
SDA Bit 0 (master output) Data 1 SDA (slave output) ICDRE
Data 2
IRIC
IRTR
ICDR
Data 1
Data 2
User processing
[9] ICDR write
[9] IRIC clear
[11] ACKB read
[12] Set BBSY=1and SCP=0 (Stop condition issuance) [12] IRIC clear
Figure 16.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0) 16.4.4 Master Receive Operation
In I2C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. (1) Receive Operation Using the HNDS Function (HNDS = 1)
Figure 16.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1).
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Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 1 in ICXR Clear IRIC flag in ICCR [1] Select receive mode.
Last receive? No Read ICDR
Yes
[2] Start receiving. The first read is a dummy read. [5] Read the receive data (for the second and subsequent read)
Read IRIC flag in ICCR No IRIC = 1? Yes Clear IRIC flag in ICCR
[3] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock for the receive frame)
[4] Clear IRIC flag.
Set ACKB = 1 in ICSR Read ICDR Read IRIC flag in ICCR No IRIC = 1?
[6] Set acknowledge data for the last reception. [7] Read the receive data. Dummy read to start receiving if the first frame is the last receive data. [8] Wait for 1 byte to be received.
Yes Clear IRIC flag in ICCR Set TRS = 1 in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR End
[9] Clear IRIC flag. [10] Read the receive data.
[11] Set stop condition issuance. Generate stop condition.
Figure 16.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)
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The reception procedure and operations using the HNDS function, by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception, are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Set the HNDS bit in ICXR to 1. Clear the IRIC flag to 0 to determine the end of reception. Go to step [6] to halt reception operation if the first frame is the last receive data. 2. When ICDR is read (dummy data read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. (Data from the SDA pin is sequentially transferred to ICDRS in synchronization with the rise of the receive clock pulses.) 3. The master device drives SDA low to return the acknowledge data at the 9th receive clock pulse. The receive data is transferred from ICDRS to ICDRR at the rise of the 9th clock pulse, setting the ICDRF, IRIC, and IRTR flags to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR data reading. 4. Clear the IRIC flag to determine the next interrupt. Go to step [6] to halt reception operation if the next frame is the last receive data. 5. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock continuously to receive the next data. Data can be received continuously by repeating steps [3] to [5]. 6. Set the ACKB bit to 1 so as to return the acknowledge data for the last reception. 7. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock to receive data. 8. When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at the rise of the 9th receive clock pulse. 9. Clear the IRIC flag to 0. 10. Read ICDR receive data after setting the TRS bit. This clears the ICDRF flag to 0. 11. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
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Master transmit mode
Master receive mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6
SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR
9 A
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
Data 1
Data 2
Undefined value
Data 1
User processing
[1] TRS=0 clear [1] IRIC clear
[2] ICDR read (Dummy read)
[4] IRIC clear
[5] ICDR read (Data 1)
Figure 16.11 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)
SCL is fixed low until stop condition is issued 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [8] A 9
SCL is fixed low until ICDR is read SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR Data 1 Data 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4
Stop condition generation
Data 2
Data 3
Data 3 [10] ICDR read (Data 3) [11] Set BBSY=0 and SCP=0 (Stop condition instruction issuance)
User processing
[4] IRIC clear
[7] ICDR read (Data 2) [6] Set ACKB = 1
[9] IRIC clear
Figure 16.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)
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(2)
Receive Operation Using the Wait Function
Figures 16.13 and 16.14 show the sample flowcharts for the operations in master receive mode (WAIT = 1).
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Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 1 in ICMR Read ICDR [2] Start receiving. The first read is a dummy read. [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) or, Wait for 1 byte to be received (Set IRIC at the rise of the 9th clock) [4] Determine end of reception IRTR = 1? Yes Last receive? No Read ICDR Clear IRIC flag in ICCR [5] Read the receive data. [6] Clear IRIC flag. (to end the wait insertion) Yes [1] Select receive mode.
Read IRIC flag in ICCR No IRIC = 1? Yes No
Set ACKB = 1 in ICSR Wait for one clock pulse Set TRS = 1 in ICCR Read ICDR Clear IRIC flag in ICCR
[7] Set acknowledge data for the last reception. [8] Wait for TRS setting [9] Set TRS for stop condition issuance [10] Read the receive data. [11] Clear IRIC flag.
Read IRIC flag in ICCR No IRIC=1? Yes IRTR=1? No Clear IRIC flag in ICCR Yes
[12] Wait for a receive wait (Set IRIC at the fall of the 8th clock) or, Wait for 1 byte to be received (Set IRIC at the rise of the 9th clock) [13] Determine end of reception
[14] Clear IRIC. (to end the wait insertion) [15] Clear wait mode. Clear IRIC flag. ( IRIC flag should be cleared to 0 after setting WAIT = 0.) [16] Read the last receive data. [17] Generate stop condition
Set WAIT = 0 in ICMR Clear IRIC flag in ICCR Read ICDR Set BBSY= 0 and SCP= 0 in ICCR End
Figure 16.13 Sample Flowchart for Operations in Master Receive Mode (receiving multiple bytes) (WAIT = 1)
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Slave receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 0 in ICMR [1] Select receive mode.
Read ICDR
[2] Start receiving. The first read is a dummy read.
Read IRIC flag in ICCR
No
IRIC = 1?
[3] Wait for a receive wait (Set IRIC at the fall of the 8th clock)
Yes
Set ACKB = 1 in ICSR Set TRS = 1 in ICCR Clear IRIC flag in ICCR [7] Set acknowledge data for the last reception. [9] Set TRS for stop condition issuance [14] Clear IRIC flag. (to end the wait insertion) [12] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock)
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Set WAIT = 0 in ICMR Clear IRIC flag in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR [15] Clear wait mode. Clear IRIC flag. ( IRIC flag should be cleared to 0 after setting WAIT = 0.) [16] Read the last receive data [17] Generate stop condition
End
Figure 16.14 Sample Flowchart for Operations in Master Receive Mode (receiving a single byte) (WAIT = 1)
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The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially received in synchronization with ICDR (ICDRR) read operations, are described below. The following describes the multiple-byte reception procedure. In single-byte reception, some steps of the following procedure are omitted. At this time, follow the procedure shown in figure 16.14. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 to set the acknowledge data. Clear the HNDS bit in ICXR to 0 to cancel the handshake function. Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1. 2. When ICDR is read (dummy data is read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. 3. The IRIC flag is set to 1 in either of the following cases. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag clearing. At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. The master device outputs the receive clock continuously to receive the next data. 4. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [6] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and the next data is the last receive data, execute step [7] to halt reception. 5. If IRTR flag is 1, read ICDR receive data. 6. Clear the IRIC flag. When the flag is set as the first case in step [3], the master device outputs the 9th clock and drives SDA low at the 9th receive clock pulse to return an acknowledge signal. Data can be received continuously by repeating steps [3] to [6]. 7. Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception. 8. After the IRIC flag is set to 1, wait for at least one clock pulse until the rise of the first clock pulse for the next receive data. 9. Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. The TRS bit value becomes valid when the rising edge of the next 9th clock pulse is input. 10. Read the ICDR receive data.
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11. Clear the IRIC flag to 0. 12. The IRIC flag is set to 1 in either of the following cases. At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. The master device outputs the receive clock continuously to receive the next data. 13. Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop condition. 14. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state. Execute step [12] to read the IRIC flag to detect the end of reception. 15. Clear the WAIT bit in ICMR to cancel the wait mode. Then, clear the IRIC flag. Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the stop condition may not be issued correctly.) 16. Read the last ICDR receive data. 17. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
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Master tansmit mode
Master receive mode
SCL (master output)
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
SDA (slave output) SDA (master output)
A
Bit 7
Bit 6
Bit 5
Bit 4 Data 1
Bit 3
Bit 2
Bit 1
Bit 0 [3] A [3]
Bit 7
Bit 6
Bit 5 Data 2
Bit 4
Bit 3
IRIC
IRTR
[4]IRTR=0
[4] IRTR=1
ICDR
Data 1
User processing [1] TRS cleared to 0 IRIC cleard to 0
[2] ICDR read (dummy read)
[6] IRIC clear [5] ICDR read [6] IRIC clear (to end wait insertion) (Data 1)
Figure 16.15 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1)
[8] Wait for one clock pulse
Stop condition generation SCL (master output) 8 9 1 Bit 7 [3] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [12] A [12] 9
SDA Bit 0 (slave output) Data 2 [3] SDA (master output) IRIC IRTR ICDR
[4] IRTR=0
Data 3
[4] IRTR=1
[13] IRTR=0
[13] IRTR=1
Data 1
Data 2
Data 3 [15] WAIT cleared to 0, IRIC clear [14] IRIC clear (to end wait [17] Stop condition insertion) issuance [16] ICDR read (Data 3)
User processing
[6] IRIC clear (to end wait insertion)
[11] IRIC clear [10] ICDR read (Data 2) [9] Set TRS=1
[7] Set ACKB=1
Figure 16.16 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1)
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16.4.5
Slave Receive Operation
In I2C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address. (1) Receive Operation Using the HNDS Function (HNDS = 1)
Figure 16.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1).
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Slave receive mode Initialize IIC Set MST = 0 and TRS = 0 in ICCR
Set ACKB = 0 in ICSR and HNDS = 1 in ICXR
[1] Initialization. Select slave receive mode.
Clear IRIC flag in ICCR
ICDRF = 1? Yes No
[2] Read the receive data remaining unread.
Read ICDR, clear IRIC flag Clear IRIC flag in ICCR
No IRIC = 1? Yes
[3] to [7] Wait for one byte to be received (slave address + R/W)
Clear IRIC flag in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1?
No Yes
[8] Clear IRIC flag
General call address processing * Description omitted
Yes
Read TRS in ICCR TRS = 1?
No
Slave transmit mode
Last reception?
No
Yes
Read ICDR
[10] Read the receive data. The first read is a dummy read.
Read IRIC flag in ICCR
No IRIC = 1? Yes
[5] to [7] Wait for the reception to end.
Clear IRIC flag in ICCR Set ACKB = 1 in ICSR Read ICDR Read IRIC flag in ICCR
No IRIC = 1? Yes
[8] Clear IRIC flag. [9] Set acknowledge data for the last reception. [10] Read the receive data. [5] to [7] Wait for reception end. [11] Detect stop condition.
ESTP = 1 or STOP = 1?
No
Yes
[12] Check STOP bit.
Clear IRIC flag in ICCR Clear IRIC flag in ICCR End
[8] Clear IRIC flag. [12] Clear IRIC flag.
Figure 16.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)
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The reception procedure and operations using the HNDS bit function, by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address and transmit/receive direction (R/W), in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit (R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as an acknowledge signal. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive clock pulse until data is read from ICDR. 8. Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0. 9. If the next frame is the last receive frame, set the ACKB bit to 1. 10. If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the master device to transfer the next data. Receive operations can be performed continuously by repeating steps [5] to [10]. 11. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. 12. Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0.
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Start condition generation SCL (Pin waveform) SCL (master output) SCL (slave output) SDA (master output) SDA (slave output)
IRIC 1 1 2 2 3 3 4 4 5 5 6 6 7 7
[7] SCL is fixed low until ICDR is read
8 8 9 9 1 1 2 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Bit 7
Bit 6 Data 1
Slave address
[6]
A
Interrupt request occurrence
ICDRF
ICDRS
Address+R/W
ICDRR
Undefined value
Address+R/W
User processing
[2] ICDR read
[8] IRIC clear
[10] ICDR read (dummy read)
Figure 16.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1)
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[7] SCL is fixed low until ICDR is read SCL (master output) SCL (slave output) SDA (master output) Data (n-1) SDA (slave output) IRIC
Bit 0 Bit 7 Bit 6 Bit 5 Bit 4
8 9 1 2 3 4 5
[7] SCL is fixed low until ICDR is read
6 7 8 9
Stop condition generation
Bit 3
Bit 2
Bit 1
Bit 0
[6]
Data (n)
[6]
[11]
A
A
ICDRF
ICDRS
Data (n-1)
Data (n) Data (n-1) Data (n)
ICDRR
Data (n-2)
User processing
[8] IRIC clear [5] ICDR read (Data (n-1)) [9] Set ACKB=1
[8] IRIC clear
[10] ICDR read (Data (n))
[12] IRIC clear
Figure 16.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) (2) Continuous Receive Operation
Figure 16.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0).
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Slave receive mode Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR ICDRF = 1? Yes Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1? No Read TRS in ICCR TRS = 1? No No Yes Yes No
[1] Select slave receive mode.
[2] Read the receive data remaining unread.
[3] to [7] Wait for one byte to be received (slave address + R/W) (Set IRIC at the rise of the 9th clock)
[8] Clear IRIC
General call address processing * Description omitted
Slave transmit mode
* n: Address + total number of bytes received
(n-2)th-byte reception? Yes Wait for one frame Set ACKB = 1 in ICSR
[9] Wait for ACKB setting and set acknowledge data for the last reception (after the rise of the 9th clock of (n-1)th byte data)
No
ICDRF = 1? Yes Read ICDR Read IRIC in ICCR No IRIC = 1? Yes ESTP = 1 or STOP = 1? No Clear IRIC in ICCR
[10] Read the receive data. The first read is a dummy read.
[11] Wait for one byte to be received (Set IRIC at the rise of the 9th clock)
Yes
[12] Detect stop condition
[13] Clear IRIC
ICDRF = 1? Yes Read ICDR Clear IRIC in ICCR End
No
[14] Read the last receive data
[15] Clear IRIC
Figure 16.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
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The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in section 16.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address and transmit/receive direction (R/W) in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as an acknowledge signal. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, the IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. 8. Confirm that the STOP bit is cleared to 0 and clear the IRIC flag to 0. 9. If the next read data is the third last receive frame, wait for at least one frame time to set the ACKB bit. Set the ACKB bit after the rise of the 9th clock pulse of the second last receive frame. 10. Confirm that the ICDRF flag is set to 1 and read ICDR. This clears the ICDRF flag to 0. 11. At the rise of the 9th clock pulse or when the receive data is transferred from IRDRS to ICDRR due to ICDR read operation, the IRIC and ICDRF flags are set to 1. 12. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP or ESTP flag is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. In this case, execute step [14] to read the last receive data. 13. Clear the IRIC flag to 0. Receive operations can be performed continuously by repeating steps [9] to [13]. 14. Confirm that the ICDRF flag is set to 1, and read ICDR. 15. Clear the IRIC flag.
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Start condition issuance SCL (master output) SDA (master output) SDA (slave output) IRIC 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [6] A 9 1 Bit 7 2 Bit 6 Data 1 3 Bit 5 4 Bit 4
Slave address
ICDRF
ICDRS
Address+R/W [7]
Data 1
ICDRR
Address+R/W
User processing
[8] IRIC clear [10] ICDR read
Figure 16.21 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0)
Stop condition detection SCL (master output) 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SDA (master output) Bit 0 Data n-2 SDA (slave output) IRIC ICDRF ICDRS ICDRR User processing Data n-2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 [11] A Data n-1 [11] A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data n [11] A [11]
Data n-1 Data n-2 [9] Wait for one frame [13] IRIC clear Data n-1
Data n Data n
[13] IRIC clear [10] ICDR read [10] ICDR read (Data n-1) (Data n-2) [9] Set ACKB = 1
[13] IRIC clear [14] ICDR read (Data n) [15] IRIC clear
Figure 16.22 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0)
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16.4.6
Slave Transmit Operation
If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 16.23 shows the sample flowchart for the operations in slave transmit mode.
Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR
[1], [2] If the slave address matches to the address in the first frame following the start condition detection and the R/W bit is 1 in slave recieve mode, the mode changes to slave transmit mode. [3], [5] Set transmit data for the second and subsequent bytes.
[3], [4] Wait for 1 byte to be transmitted.
No
IRIC = 1?
Yes
Read ACKB in ICSR [4] Determine end of transfer.
No
End of transmission (ACKB = 1)?
Yes
Clear IRIC in ICCR [6] Clear IRIC in ICCR [7] Clear acknowledge bit data [8] Set slave receive mode. [9] Dummy read (to release the SCL line). [10] Wait for stop condition
Clear ACKE to 0 in ICCR (ACKB=0 clear)
Set TRS = 0 in ICCR Read ICDR Read IRIC in ICCR
No
IRIC = 1?
Yes
Clear IRIC in ICCR End
Figure 16.23 Sample Flowchart for Slave Transmit Mode
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In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2. When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the ICDRE flag is set to 1. The slave device drives SCL low from the fall of the transmit 9th clock until ICDR data is written, to disable the master device to output the next transfer clock. 3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared to 0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1 again. The slave device sequentially sends the data written into ICDRS in accordance with the clock output by the master device. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. 4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed successfully. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS, transmission starts, and the ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has been set to 1, this slave device drives SCL low from the fall of the 9th transmit clock until data is written to ICDR. 5. To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. Transmit operations can be performed continuously by repeating steps [4] and [5]. 6. Clear the IRIC flag to 0. 7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in the ACKB bit to 0. 8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode. 9. Dummy-read ICDR to release SCL on the slave side.
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10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0.
Slave receive mode SCL (master output) SDA (slave output)
Slave transmit mode
8
9
1
2
3
4
5
6
7
8
9
1
2
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
[2]
Data 1
[4]
Data 2
SDA (master output) R/W
A
IRIC
ICDRE
ICDR User processing
[3] IRIC clear [3] ICDR write [3] IRIC clear
Data 1
Data 2
[5] IRIC clear [5] ICDR write
Figure 16.24 Example of Slave Transmit Mode Operation Timing (MLS = 0)
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16.4.7
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock. Figures 16.25 to 16.27 show the IRIC set timing and SCL control.
When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)
SCL 7 8 9 1 2 3
SDA
7
8
A
1
2
3
IRIC User processing Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL 7 8 9 1
SDA
7
8
A
1
IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 16.25 IRIC Setting Timing and SCL Control (1)
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When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)
SCL 8 9 1 2 3
SDA
8
A
1
2
3
IRIC User processing Clear IRIC Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL 8 9 1
SDA
8
A
1
IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 16.26 IRIC Setting Timing and SCL Control (2)
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When FS = 1 and FSX = 1 (clocked synchronous serial format)
SCL 7 8 1 2 3 4
SDA
7
8
1
2
3
4
IRIC User processing Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
SCL 7 8 1
SDA
7
8
1
IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 16.27 IRIC Setting Timing and SCL Control (3)
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16.4.8
Operation by Using DTC
This LSI provides the DTC to allow consecutive transfer. The DTC is activated when the IRTR flag which is one of two interrupt flags (IRIC and IRTR) is set to 1. When the ACKE bit is cleared to 0, regardless of the acknowledge bit, the ICDRE, IRIC, and IRTR flags are set at the completion of the data transfer. When the ACKE bit is set to 1, if data transmission has been completed with the acknowledge bit of 0, the ICDRE, IRIC, and IRTR flags are set. When the ACKE bit is set to 1, if data transmission has been completed with the acknowledge bit of 1, only the IRIC flag is set. When the DTC is activated, the ICDRE, IRIC, and IRTR flags are cleared to 0 after required transfers has been performed. Therefore, any interrupt is occurred while data is transferred continuously. However, when the ACKE bit is set to 1, if the data transmission has been completed with the acknowledge bit of 1, the DTC is not be activated and an interrupt is occurred if enabled. According to the reception device, the acknowledge bit indicates the completion of receive data processing or is fixed to 1 without any indication. In the I2C bus format, the selection of a slave device and transfer direction by the slave address and R/W bit, and confirming reception and indicating the last frame by the acknowledge bit are performed. Therefore, the consecutive data transfer by the DTC should be executed with the processing of CPU by interrupts. Table 16.7 shows the sample processing by using the DTC. It is supposed that the number of transfer data has been known in the slave mode.
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Table 16.7 Operation by Using DTC
Item Slave address + R/W bit transmission/ reception Master Transmit Mode Master Receive Mode Slave Transmit Mode Slave Receive Mode
Transmission by Transmission by Reception by CPU Reception by CPU DTC (ICDR write) CPU (ICDR write) (ICDR read) (ICDR read)
Dummy data read I2C data transmission/ reception Dummy data (H'FF) write Last frame processing Transfer request processing after last frame processing completed
Processing by CPU (ICDR read)
Transmission by Transmission by DTC (ICDR write) DTC (ICDR read) Not required
Transmission by Reception by DTC DTC (ICDR write) (ICDR read) Processing by DTC (ICDR write) Reception by CPU (ICDR read) Not required
Reception by CPU Not required (ICDR read) Dummy data (H'FF) Stop condition detection and automatic clear during transmission
1st time: Clearing Not required by CPU 2nd time: Stop condition issue by CPU
Set the number of Transmission: The Reception: The frames of DTC number of actual number of actual transfer data data + 1 (+ 1 = data slave address + R/W bit)
Transmission: The Reception: The number of actual number of actual data data + 1 (+ 1 = dummy data (H'FF))
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16.4.9
Noise Canceller
The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched internally. Figure 16.28 shows a block diagram of the noise canceller. The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C SCL or SDA input signal D Latch Q D
C Q Latch Match detector Internal SCL or SDA signal
System clock cycle Sampling clock
Figure 16.28 Block Diagram of Noise Canceller
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16.4.10 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 16.3.7, DDC Switch Register (DDCSWR). (1) Scope of Initialization
The initialization executed by this function covers the following items: * ICDRE and ICDRF internal flags * Transmit/receive sequencer and internal operating clock counter * Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) The following items are not initialized: * Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE and ICDRF flags) * Internal latches used to retain register read information for setting/clearing flags in ICMR, ICCR, and ICSR * The value of the ICMR bit counter (BC2 to BC0) * Generated interrupt sources (interrupt sources transferred to the interrupt controller) (2) Notes on Initialization
* Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. * Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. * When initialization is executed by DDCSWR, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. * Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting.
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* If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 4. Initialize (re-set) the IIC registers.
16.5
Interrupt Sources
The IIC has interrupt source IICI. Table 16.8 shows the interrupt sources and priority. Individual interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the interrupt controller independently. The IIC interrupts are used as on-chip DTC activation sources. Table 16.8 IIC Interrupt Sources
Channel 0 1 Name IICI0 IICI1 Enable Bit IEIC IEIC Interrupt Source I C bus interface interrupt request I2C bus interface interrupt request
2
Interrupt Flag Priority IRIC IRIC Low High
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16.6
Usage Notes
1. In master mode, if an instruction to generate a start condition is issued and then an instruction to generate a stop condition is issued before the start condition is output to the I2C bus, neither condition will be output correctly. To output the stop condition followed by the start condition*, after issuing the instruction that generates the start condition, read DR in each I2C bus output pin, and check that SCL and SDA are both low. The pin states can be monitored by reading DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. Note: * An illegal procedure in the I2C bus specification. 2. Either of the following two conditions will start the next transfer. Pay attention to these conditions when accessing to ICDR. Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) 3. Table 16.9 shows the timing of SCL and SDA outputs in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Table 16.9 I2C Bus Timing (SCL and SDA Outputs)
Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time Note: * tSDAHO Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28tcyc to 256tcyc 0.5tSCLO 0.5tSCLO 0.5tSCLO - 1tcyc 0.5tSCLO - 1tcyc 1tSCLO 0.5tSCLO + 2tcyc 1tSCLLO - 3tcyc 1tSCLL - (6tcyc or 12tcyc*) 3tcyc ns Unit ns ns ns ns ns ns ns ns Notes See figure 26.23
6tcyc when IICX is 0, 12tcyc when 1.
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Section 16 I C Bus Interface (IIC)
2
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in section 26, Electrical Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. 5. The I2C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for high-speed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in table 16.10. Table 16.10 Permissible SCL Rise Time (tsr) Values
Time Indication [ns] I C Bus Specification = (Max.) 5 MHz Standard mode 1000 1000 300 1000 300
2
IICX tcyc Indication 0 7.5 tcyc
= 8 MHz 937 300 1000 300
= 10 MHz 750 300 1000 300
= 16 MHz 468 300 1000 300
= 20 MHz 375 300 875 300
High-speed mode 300 1 17.5 tcyc Standard mode 1000
High-speed mode 300
6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in table 16.9. However, because of the rise and fall times, the I2C bus interface specifications may not be satisfied at the maximum transfer rate. Table 16.11 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the I2C bus.
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Section 16 I C Bus Interface (IIC)
2
Table 16.11 I2C Bus Timing (with Maximum Influence of tSr/tSf)
Time Indication (at Maximum Transfer Rate) [ns] I C Bus SpecifitSr/tSf = Influence cation 5 MHz (Max.) (Min.) Standard mode -1000 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 4000 950 4750 1000* 3800* 750*
1 1 2
Item tSCLHO
tcyc Indication 0.5 tSCLO (-tSr)
= 8 MHz 4000 950 4750 1000* 3875* 825*
1 1
= = = 10 MHz 16 MHz 20 MHz 4000 950 4750 1000* 3900* 850*
1 1
4000 950 4750 1000* 3939* 888*
1 1
4000 950 4750 1000* 3950* 900*
1 1
High-speed mode -300 tSCLLO 0.5 tSCLO (-tSf) Standard mode -250
High-speed mode -250 tBUFO 0.5 tSCLO -1 tcyc (-tSr) 0.5 tSCLO -1 tcyc (-tSf) 1 tSCLO (-tSr) Standard mode -1000
1
1
1
1
1
High-speed mode -300 Standard mode -250
tSTAHO
4550 800 9000 2200 4400 1350 3100 400 1300
4625 875 9000 2200 4250 1200 3325 625 2200
4650 900 9000 2200 4200 1150 3400 700 2500
4688 938 9000 2200 4125 1075 3513 813 2950
4700 900 9000 2200 4100 1050 3550 850 3100
High-speed mode -250 Standard mode -1000
tSTASO
High-speed mode -300 tSTOSO 0.5 tSCLO + 2 tcyc Standard mode -1000 (-tSr) High-speed mode -300 1 tSCLLO* -3 tcyc Standard mode
3
tSDASO
-1000
(master) (-tSr)
High-speed mode -300
3
tSDASO 1 tSCLL* (slave) 2 -12 tcyc* (-tSr) tSDAHO 3 tcyc
Standard mode
-1000
High-speed mode -300 Standard mode 0
100 0 0
-1400* 600 600
1
-500* 375 375
1
-200* 300 300
1
250 188 188
400 150 150
High-speed mode 0
2
Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the 2 maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL - 6 tcyc). 3. Calculated using the I2C bus specification values (standard mode: 4700 ns min.; high-speed mode: 1300 ns min.).
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Section 16 I C Bus Interface (IIC)
2
7. Notes on ICDR read at end of master reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR (ICDRR), and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in ICCR is cleared to 0, the stop condition has been generated, and the bus has been released, then read ICDR with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 16.29 (after confirming that the BBSY bit in ICCR has been cleared to 0).
Stop condition (a) SDA SCL Internal clock BBSY bit Bit 0 8 A 9
Start condition
Master receive mode ICDR read disabled period
Execution of instruction for issuing stop condition (write 0 to BBSY and SCP)
Confirmation of stop condition issuance (read BBSY = 0)
Start condition issuance
Figure 16.29 Notes on Reading Master Receive Data
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Section 16 I C Bus Interface (IIC)
2
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 8. Notes on start condition issuance for retransmission Figure 16.30 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. Write the transmit data to ICDR after the start condition for retransmission is issued and then the start condition is actually generated.
[1] Wait for end of 1-byte transfer IRIC = 1? Yes Clear IRIC in ICCR [3] Issue start condition instruction for retransmission Read SCL pin SCL = Low? Yes Set BBSY = 1, SCP = 0 (ICCR) No Yes Write transmit data to ICDR [5] [3] [4] Note:* Program so that processing from [3] to [5] is executed continuously. No [4] Determine whether start condition is generated or not [2] [5] Set transmit data (slave address + R/W) No [1] [2] Determine whether SCL is low
IRIC = 1?
Start condition generation (retransmission) SCL 9
SDA
ACK
bit7
IRIC
[5] ICDR write (transmit data) [4] IRIC determination [1] IRIC determination [3] (Retransmission) Start condition instruction issuance [2] Determination of SCL = Low
Figure 16.30 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing
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Section 16 I C Bus Interface (IIC)
2
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 9. Note on when I2C bus interface stop condition instruction is issued In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low.
SCL
9th clock VIH
Secures a high period
SCL is detected as low because the rise of the waveform is delayed SDA Stop condition generation IRIC [1] SCL = low determination [2] Stop condition instruction issuance
Figure 16.31 Stop Condition Issuance Timing Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR.
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Section 16 I C Bus Interface (IIC)
2
10. Note on IRIC flag clear when the wait function is used If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be inserted by driving the SCL pin low is used when the wait function is used in I2C bust interface master mode, the IRIC flag should be cleared after determining that the SCL is low, as described below. If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time, the SDA level may change before the SCL goes low, which may generate a start or stop condition erroneously.
Secures a high period SCL VIH SCL = low detected
SDA
IRIC [1] SCL = low determination [2] IRIC clear
Figure 16.32 IRIC Flag Clearing Timing when WAIT = 1 Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR.
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Section 16 I C Bus Interface (IIC)
2
11. Note on ICDR read and ICCR access in slave transmit mode In I2C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 16.33. However, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling. To handle interrupts securely, be sure to keep either of the following conditions. Read ICDR data that has been received so far or read/write from/to ICCR before starting the receive operation of the next slave address. Monitor the BC2 to BC0 bit counter in ICMR; when the count is B'000 (8th or 9th clock pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to ICCR during the time other than the shaded time.
Waveform at problem occurrence ICDR write SDA R/W A Bit 7
SCL
8
9
TRS bit
Address reception
Data transmission
ICDR read and ICCR read/write are disabled (6 system clock period)
The rise of the 9th clock is detected
Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR.
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Section 16 I C Bus Interface (IIC)
2
12. Note on TRS bit setting in slave mode In I2C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 16.34), the bit value becomes valid immediately when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in figure 16.34), the bit value is suspended and remains invalid until the rising edge of the 9th clock pulse or the stop condition is detected. Therefore, when the address is received after the restart condition is input without the stop condition, the effective TRS bit value remains 1 (transmit mode) internally and thus the acknowledge bit is not transmitted after the address has been received at the 9th clock pulse. To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in figure 16.34. To release the SCL low level that is held by means of the wait function in slave mode, clear the TRS bit to and then dummy-read ICDR.
Restart condition (a) SDA (b) A
SCL
8
9
1
2
3
4
5
6
7
8
9
TRS
Data transmission
Address reception
TRS bit setting is suspended in this period ICDR dummy read TRS bit setting The rise of the 9th clock is detected
The rise of the 9th clock is detected
Figure 16.34 TRS Bit Set Timing in Slave Mode Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR.
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Section 16 I C Bus Interface (IIC)
2
13. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode or write to ICDR after setting transmit mode. 14. Note on ACKE and TRS bits in slave mode In the I2C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit mode (TRS = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the address does not match. Similarly, if the start condition or address is transmitted from the master device in slave transmit mode (TRS = 1), the IRIC flag may be set after the ICDRE flag is set and 1 received as the acknowledge bit value (ACKB = 1), thus causing an interrupt source even when the address does not match. To use the I2C bus interface module in slave mode, be sure to follow the procedures below. A. When having received 1 as the acknowledge bit value for the last transmit data at the end of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB bit to 0. B. Set receive mode (TRS = 0) before the next start condition is input in slave mode. Complete transmit operation by the procedure shown in figure 16.23, in order to switch from slave transmit mode to slave receive mode. 15. Note on Arbitration Lost in Master Mode The I2C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the address in the SAR or SARX register, the I2C bus interface erroneously recognizes that the address call has occurred. (See figure 16.35.) In multi-master mode, a bus conflict could happen. When the I2C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures.
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Section 16 I C Bus Interface (IIC)
2
* Arbitration is lost * The AL flag in ICSR is set to 1
I2C bus interface (Master transmit mode)
S
SLA
R/W
A
DATA1
Transmit data does not match
Transmit data match Transmit timing match
Other device (Master transmit mode)
S
SLA
R/W
A
DATA2
A
DATA3
A
Data contention bus interface (Slave receive mode) I2C S SLA R/W A SLA R/W A DATA4 A
* Receive address is ignored
* Automatically transferred to slave receive mode * Receive data is recognized as an address * When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device.
Figure 16.35 Diagram of Erroneous Operation when Arbitration is Lost Though it is prohibited in the normal I2C protocol, the same problem may occur when the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order below. A. Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting the MST bit. B. Set the MST bit to 1. C. To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. Note: Above restriction can be cleared by setting bits FNC1 and FNC0 in the ICXR register.
16.6.1
Module Stop Mode Setting
The IIC operation can be enabled or disabled using the module stop control register. The initial setting is for the IIC operation to be halted. Register access is enabled by canceling module stop mode. For details, see section 24, Power-Down Modes.
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Section 17 Keyboard Buffer Control Unit (KBU)
Section 17 Keyboard Buffer Control Unit (KBU)
This LSI has three on-chip keyboard buffer control unit (KBU) channels. The KBU is provided with functions conforming to the PS/2 interface specifications. Data transfer using the KBU employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc. Figure 17.1 shows a block diagram of the KBU.
17.1
Features
* Conforms to PS/2 interface specifications * Direct bus drive (via the KCLK and KD pins) * Interrupt sources: on completion of data reception/transmission, on detection of clock falling edge, and on detection of the first falling edge of a clock * Error detection: parity error, stop bit monitoring, and receive notify monitoring
IFKEY10A_000020020700
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Section 17 Keyboard Buffer Control Unit (KBU)
KBBR KBTR KD (PS2AD, PS2BD, PS2CD) KCLK (PS2AC, PS2BC, PS2CC) Transmission start KDI Control logic KCLKI Parity Transmit counter nalue KDO KCLKO KBCRL KBCRH KBCR1
Internal data bus
KBCR2
Register counter value KBI interrupt KCI interrupt KTI interrupt [Legend] KD: KBU data I/O pin KCLK: KBU clock I/O pin KBBR: Keyboard data buffer register KBCRH: Keyboard control register H KBCRL: Keyboard control register L KBTR: Keyboard buffer transmit data register KBCR1: Keyboard control register 1 KBCR2: Keyboard control register 2
Figure 17.1 Block Diagram of KBU
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Module data bus
Bus interface
Section 17 Keyboard Buffer Control Unit (KBU)
Figure 17.2 shows how the KBU is connected.
Vcc
Vcc
System side KCLK in Clock KCLK out
Keyboard side KCLK in KCLK out
KD in KD out
Data
KD in KD out
Keyboard buffer control unit (This LSI)
I/F
Figure 17.2 KBU Connection
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Section 17 Keyboard Buffer Control Unit (KBU)
17.2
Input/Output Pins
Table 17.1 lists the input/output pins used by the keyboard buffer control unit. Table 17.1 Pin Configuration
Channel 0 Name KBU clock I/O pin (KCLK0) KBU data I/O pin (KD0) 1 KBU clock I/O pin (KCLK1) KBU data I/O pin (KD1) 2 Note: * KBU clock I/O pin (KCLK2) KBU data I/O pin (KD2) Abbreviation* PS2AC PS2AD PS2BC PS2BD PS2CC PS2CD I/O I/O I/O I/O I/O I/O I/O Function KBU clock input/output KBU data input/output KBU clock input/output KBU data input/output KBU clock input/output KBU data input/output
These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK and data I/O pins as KD, omitting the channel designations.
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Section 17 Keyboard Buffer Control Unit (KBU)
17.3
Register Descriptions
The KBU has the following registers for each channel. * * * * * * Keyboard control register 1 (KBCR1) Keyboard control register 2 (KBCR2) Keyboard control register H (KBCRH) Keyboard control register L (KBCRL) Keyboard data buffer register (KBBR) Keyboard buffer transmit data register (KBTR) Keyboard Control Register 1 (KBCR1)
17.3.1
KBCR1 controls data transmission and interrupt, selects parity, and detects transmit error.
Bit 7 Bit Name Initial Value KBTS 0 R/W R/W Description Transmit Start Selects start of data transmission or disables transmission. 0: Data transmission is disabled [Clearing conditions] * * * When 0 is written When the KBTE is set to 1 When the KBIOE is cleared to 0
1: Starts data transmission [Setting condition] * 6 PS 0 R/W When 1 is written after reading the KBTS = 0 Transmit Parity Selection Selects even or odd parity. 0: Selects odd parity 1: Selects even parity 5 KCIE 0 R/W First KCLK Falling Interrupt Enable Selects whether an interrupt at the first falling edge of KCLK is enabled or disabled. 0: Disables first KCLK falling interrupt 1: Enables first KCLK falling interrupt
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Section 17 Keyboard Buffer Control Unit (KBU)
Bit 4
Bit Name KTIE
Initial Value 0
R/W R/W
Description Transmit Completion Interrupt Enable Selects whether a transmit completion interrupt is enabled or disabled. 0: Disables transmit completion interrupt 1: Enables transmit completion interrupt
3 2
KCIF
0 0
Reserved The initial value should not be changed.
R/(W)* First KCLK Falling Interrupt Flag Indicates that the first falling edge of KCLK is detected. When KCIE and KCIF are set to 1, requests the CPU an interrupt. 0: [Clearing condition] * * After reading KCIF = 1, 0 is written When the first falling edge of KCLK is detected 1: [Setting condition] Note that this flag cannot be set when software standby mode, watch mode, or subsleep mode is cancelled. (However, internal flag is set.)
1
KBTE
0
R/(W)* Transmit Completion Flag Indicates that data transmission is completed. When KTIE and KBTE are set to 1, requests the CPU an interrupt. 0: [Clearing condition] * * After reading KBTE = 1, 0 is written When all KBTR data has been transmitted (Set at the eleventh rising edge of the KCLK signal) 1: [Setting Condition]
0
KTER
0
R
Transmit Error Stores a notification of receive completion. Valid only when KBTE = 1. 0: 0 received as a notification of receive completion. 1: 1 received as a notification of receive completion.
Note:
*
Only 0 can be written for clearing the flag.
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Section 17 Keyboard Buffer Control Unit (KBU)
17.3.2
Keyboard Buffer Control Register 2 (KBCR2)
KBCR2 is a 4-bit counter which performs counting synchronized with the falling edge of KCLK. Transmit data is synchronized with the transmit counter, and data in the KBTR is sent to the KD (LSB-first).
Bit Bit Name Initial Value All 1 R/W R/W Description Reserved These bits are always read as 0. The initial value should not be changed. 3 2 1 0 TXCR3 TXCR2 TXCR1 TXCR0 0 0 0 0 R R R R Transmit Counter Indicates bit of transmit data. Counter is incremented at the falling edge of KCLK. The transmit counter is initialized by a reset, when the KBTS is cleared to 0, the KBIOE is cleared to 0, or the KBTE is set to 1. 0000: Clear 0001: KBT0 0010: KBT1 0011: KBT2 0100: KBT3 0101: KBT4 0110: KBT5 0111: KBT6 1000: KBT7 1001: Parity bit 1010: Stop bit 1011: Transmit completion notification
7 to 4
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Section 17 Keyboard Buffer Control Unit (KBU)
17.3.3
Keyboard Control Register H (KBCRH)
KBCRH indicates the operating status of the keyboard buffer control unit.
Bit 7 Bit Name Initial Value KBIOE 0 R/W R/W Description Keyboard In/Out Enable Selects whether or not the keyboard buffer control unit is used. 0: The keyboard buffer control unit is non-operational (KCLK and KD signal pins have port functions) 1: The keyboard buffer control unit is enabled for transmission and reception (KCLK and KD signal pins are in the bus drive state) 6 KCLKI 1 R Keyboard Clock In Monitors the KCLK I/O pin. This bit cannot be modified. 0: KCLK I/O pin is low 1: KCLK I/O pin is high 5 KDI 1 R Keyboard Data In: Monitors the KDI I/O pin. This bit cannot be modified. 0: KD I/O pin is low 1: KD I/O pin is high 4 KBFSEL 1 R/W Keyboard Buffer Register Full Select Selects whether the KBF bit is used as the keyboard buffer register full flag or as the KCLK fall interrupt flag. When KBF bit is used as the KCLK fall interrupt flag, the KBE bit in KBCRL should be cleared to 0 to disable reception. 0: KBF bit is used as KCLK fall interrupt flag 1: KBF bit is used as keyboard buffer register full flag
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Section 17 Keyboard Buffer Control Unit (KBU)
Bit 3
Bit Name Initial Value KBIE 0
R/W R/W
Description Keyboard Interrupt Enable Enables or disables interrupts from the keyboard buffer control unit to the CPU. 0: Interrupt requests are disabled 1: Interrupt requests are enabled
2
KBF
0
R/(W)*
Keyboard Buffer Register Full Indicates that data reception has been completed and the received data is in KBBR. When both KBIE and KBF are set to1, an interrupt request is sent to the CPU. 0: [Clearing condition] * * Read KBF when KBF =1, then write 0 in KBF When data has been received normally and has been transferred to KBBR while KBFSEL = 1 (keyboard buffer register full flag) When a KCLK falling edge is detected while KBFSEL = 0 (KCLK interrupt flag) 1: [Setting conditions]
* 1 PER 0 R/(W)*
Parity Error Indicates that an odd parity error has occurred. 0: [Clearing condition] * * Read PER when PER =1, then write 0 in PER When an odd parity error occurs 1: [Setting condition]
0
KBS
0
R
Keyboard Stop Indicates the receive data stop bit. Valid only when KBF = 1. 0: 0 stop bit received 1: 1 stop bit received
Note:
*
Only 0 can be written for clearing the flag.
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Section 17 Keyboard Buffer Control Unit (KBU)
17.3.4
Keyboard Control Register L (KBCRL)
KBCRL enables the receive counter count and controls the keyboard buffer control unit pin output.
Bit 7 Bit Name Initial Value KBE 0 R/W R/W Description Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled 6 KCLKO 1 R/W Keyboard Clock Out Controls KBU clock I/O pin output. 0: KBU clock I/O pin is low 1: KBU clock I/O pin is high 5 KDO 1 R/W Keyboard Data Out Controls KBU data I/O pin output. 0: KBU data I/O pin is low 1: KBU data I/O pin is high When the start bit (KDO) is automatically cleared (KDO = 1) by means of automatic transmission, 0 is written after reading 1. 4 -- 1 -- Reserved This bit is always read as 1 and cannot be modified.
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Section 17 Keyboard Buffer Control Unit (KBU)
Bit 3 2 1 0
Bit Name Initial Value RXCR3 RXCR2 RXCR1 RXCR0 0 0 0 0
R/W R R R R
Description Receive Counter These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be modified. The receive counter is initialized by a reset and when 0 is written in KBE. Its value returns to B'0000 after a stop bit is received. 0000: -- 0001: Start bit 0010: KB0 0011: KB1 0100: KB2 0101: KB3 0110: KB4 0111: KB5 1000: KB6 1001: KB7 1010: Parity bit 1011: -- 11- -: --
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Section 17 Keyboard Buffer Control Unit (KBU)
17.3.5
Keyboard Data Buffer Register (KBBR)
KBBR stores receive data. Its value is valid only when KBF = 1.
Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Keyboard Data 7 to 0 8-bit read only data. Initialized to H'00 by a reset, in hardware standby mode or when KBIOE is cleared to 0.
17.3.6
Keyboard Buffer Transmit Data Register (KBTR)
KBTR stores transmit data.
Bit 7 6 5 4 3 2 1 0 Bit Name KBT7 KBT6 KBT5 KBT4 KBT3 KBT2 KBT1 KBT0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Buffer Transmit Data Register 7 to 0 Initialized to H'00 at reset, in hardware standby mode.
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Section 17 Keyboard Buffer Control Unit (KBU)
17.4
17.4.1
Operation
Receive Operation
In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. Value of KD is valid when the KCLK is low. A sample receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4.
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Section 17 Keyboard Buffer Control Unit (KBU)
Start Set KBIOE bit Read KBCRH KCLKI and KDI bits both 1? Yes Set KBE bit Receive enabled state [1] [2] No [1] Set the KBIOE bit to 1 in KBCRL. [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, set the KBE bit (receive enabled state). [3] Detect the start bit output on the keyboard side and receive data in synchronization with the fall of KCLK. [4] When a stop bit is received, the keyboard buffer controller drives KCLK low to disable keyboard transmission (automatic I/O inhibit). If the KBIE bit is set to 1 in KBCRH, an interrupt request is sent to the CPU at the same time. [5] Perform receive data processing. [6] Clear the KBF flag to 0 in KBCRL. At the same time, the system automatically drives KCLK high, setting the receive enabled state. The receive operation can be continued by repeating steps [3] to [6].
Keyboard side in data transmission state. [3] Execute receive abort processing.
KBF = 1? Yes PER = 0? Yes KBS = 1? Yes Read KBBR Receive data processing
No [4]
No
No
Error handling
[5]
Clear KBF flag (receive enabled state)
[6]
Figure 17.3 Sample Receive Processing Flowchart
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Section 17 Keyboard Buffer Control Unit (KBU)
Receive processing/ error handling
KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KB7 to KB0 Previous data PER KBS KBF
Flag cleared
1
2 0
3 1
9 7
10
11
Start bit
Parity bit Stop bit
Automatic I/O inhibit
KB0 KB1
Receive data
[1] [2] [3]
[4] [5]
[6]
Figure 17.4 Receive Timing 17.4.2 Transmit Operation
In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit processing flowchart is shown in figure 17.5, and the transmit timing in figure 17.6.
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Section 17 Keyboard Buffer Control Unit (KBU)
Start Set KBIOE bit Clear KBE bit (reception disabled) Write transmit data to KBTR Read KBCRH Both KCLKI and KDI = 1? Yes Set I/O inhibit (KCLKO = 0) Read KBCRH KDI = 1? Yes Set start bit (KDO = 0) Set KBTS (KBTS = 1) Clear I/O inhibit (KCLKO = 1) Autmatic transmission
(Condition: KBE = 0) [1] [2] [3] [4] [1] Write 1 to the KBIOE bit to enable transmission/ reception. Clear the KBE bit (reception disabled). Write transmit data to KBTR. Read KBCRH, and when both the KCLKI and KDI bits are 1, write 0 to the KCLKO bit to set the I/O inhibit. 60 s or more is required for I/O inhibit. Read KBCRH, and when the KDI bit is 1, write 0 to the KDO (set start bit). Write 1 to the KBTS bit to enter the transmit enabled state. Write 1 to the KCLKO bit to clear the I/O inhibit. Check D0 to D7, the parity bit, the stop bit, and receive completion notification (send data at the falling edge of the KCLK signal). The KBTE bit is set to 1 at the eleventh rising edge of the KCLK signal. When KTIE = 1, a CPU interrupt occurs.
[2] [3] [4]
No [5] Receive termination processing execution KDO retains 1 [6] [5] [7] No Retransmit request processing execution KCLKO retains 0 [6] [9] [8]
[10] When KTER = 0, transmission is successfully completed. [7] KDO retains 0 [8] [9] [11] Clear the KBTE bit to 0.
KBTE = 1 Yes KTER = 0 Yes Clear KBTE bit
No [10] No [11] Error handling
Note: * The start bit (KDO = 0) is automatically initialized (KDO = 1) when automatic transmission is started. After initialization, to write 0 to KDO, read 1 before writing 0 to it.
To transmit operation or receive operation
Figure 17.5 Sample Transmit Processing Flowchart
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Section 17 Keyboard Buffer Control Unit (KBU)
I/O inhibit KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KBTE KTER KBTS I/O inhibit Start bit 1 0 2 1 8 7 9 Parity 10 11
Receive completed Stop bit notification
[4]
[6] [7] [8]
[9] [10]
[11]
[1] to [3] [5]
Figure 17.6 Transmit Timing 17.4.3 Receive Abort
This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc. In this case, the system holds the clock low. During reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is an abort request from the system, and data transmission from the keyboard is aborted. Thus the system can abort reception by holding the clock low for a certain period. A sample receive abort processing flowchart is shown in figure 17.7, and the receive abort timing in figure 17.8.
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Section 17 Keyboard Buffer Control Unit (KBU)
Start
[1] Read KBCRL, and if KBF = 1, perform processing 1. [2] Read KBCRH, and if the value of bits RXCR3 to RXCR0 is less than B'1001, write 0 in KCLKO to abort reception. [3] If the value of bits RXCR3 to RXCR0 is B'1001 or greater, wait until stop bit reception is completed, then perform receive data processing, and proceed to the next operation. If the value of bits RXCR3 to RXCR0 is B'1001 or greater, the parity bit is being received. With the PS2 interface, a receive abort request following parity bit reception is disabled. Wait until stop bit reception is completed, perform receive data processing and clear the KBF flag, then proceed to the next operation. No
Receive state Read KBCRL No
KBF = 0? Yes Read KBCRH
[1]
Processing 1
RXCR3 to RXCR0 B'1001? Yes Disable receive abort requests [3]
No
[2] KCLKO = 0 (receive abort request)
Retransmit command transmission (data)? Yes KBE = 0 (disable KBBR reception and clear receive counter) Set start bit (KDO = 0) Clear I/O inhibit (KCLKO = 1) Transmit data
KBE = 0 (disable KBBR reception and clear receive counter) KBE = 1 (enable KB operation) Clear I/O inhibit (KCLKO = 1)
To transmit operation
To receive operation
Figure 17.7 (1) Sample Receive Abort Processing Flowchart
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Section 17 Keyboard Buffer Control Unit (KBU)
Processing 1
Receive operation ends normally
[1]
[1] On the system side, drive the KCLK pin low, setting the I/O inhibit state.
Receive data processing
Clear KBF flag (KCLK = High)
Transmit enabled state. If there is transmit data, the data is transmitted.
Figure 17.7 (2) Sample Receive Abort Processing Flowchart
Keyboard side monitors clock during receive operation (transmit operation as seen from keyboard), and aborts receive operation during this period. Reception in progress KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KD (input) KD (output) Receive abort request Start bit
Transmit operation
Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover) Timing
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Section 17 Keyboard Buffer Control Unit (KBU)
17.4.4
KCLKI and KDI Read Timing
Figure 17.9 shows the KCLKI and KDI read timing.
T1
T2
*
Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note:*
The clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode.
Figure 17.9 KCLKI and KDI Read Timing
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Section 17 Keyboard Buffer Control Unit (KBU)
17.4.5
KCLKO and KDO Write Timing
Figure 17.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states.
T1 * Internal write signal KCLKO, KDO (register) KCLK, KD (pin state) Note:*
T2
The clock shown here is scaled by 1/N in medium-speed mode.
Figure 17.10 KCLKO and KDO Write Timing
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Section 17 Keyboard Buffer Control Unit (KBU)
17.4.6
KBF Setting Timing and KCLK Control
Figure 17.11 shows the KBF setting timing and the KCLK pin states.
*
KCLK (pin) Internal KCLK Falling edge signal RXCR3 to RXCR0 KBF KCLK (output)
11th fall
B'1010
B'0000
Automatic I/O inhibit
Note:*
The clock shown here is scaled by 1/N in medium-speed mode.
Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing
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Section 17 Keyboard Buffer Control Unit (KBU)
17.4.7
Receive Timing
Figure 17.12 shows the receive timing.
*
KCLK (pin)
KD (pin)
Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 Internal KD (KDI) KBBR7 to KBBR0 N N+1 N+2
Note:*
The clock shown here is scaled by 1/N in medium-speed mode.
Figure 17.12 Receive Counter and KBBR Data Load Timing
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Section 17 Keyboard Buffer Control Unit (KBU)
17.4.8
Operation during Data Reception
If the KBS bit in KBCRH is set to 1 with other keyboard buffer control units in reception*, the KCLK is automatically pulled down. Figure 17.13 shows receive timing and the KCLK. Note: * Period from the first falling edge of KCLK to completion of reception (KBF = 1).
1 KCLK 2 8 9 10 11 Automatic I/O inhibit
KD
Start bit
0
1
7
Parity
Stop bit
KBF KCLK for other PS/2
Figure 17.13 Receive Timing and KCLK
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Section 17 Keyboard Buffer Control Unit (KBU)
17.4.9
KCLK Fall Interrupt Operation
In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRH to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 17.14 shows the setting method and an example of operation.
Start Set KBIOE KBE = 0 (KBBR reception disabled) KBFSEL = 0 KBIE = 1 (KCLK falling edge interrupts enabled)
KCLK (pin state)
KBF bit KCLK pin fall detected? Yes KBF = 1 (interrupt generated) Interrupt handling Clear KBF No
Interrupt generated
Cleared by software
Interrupt generated
Note:* The KBF setting timing is the same as the timing of KBF setting and KCLK automatic I/O inhibit bit generation in figure 17.11. When the KBF bit is used as the KCLK input fall interrupt flag, the automatic I/O inhibit function does not operate.
Figure 17.14 Example of KCLK Input Fall Interrupt Operation
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Section 17 Keyboard Buffer Control Unit (KBU)
17.4.10 First KCLK Falling Interrupt An interrupt can be generated by detecting the first falling edge of KCLK on reception and transmission. Software standby, watch, and subsleep modes can be cancelled by a first KCLK falling interrupt. * Reception When both KBIOE and KBE are set to 1, KCIF is set after the first falling edge of KCLK has been detected. At this time, if KCIE is set to 1, the CPU is requested an interrupt. KCIF is set at the same time when the RXCR3 to RXCR0 bits in KBCRL are incremented from B'0000 to B'0001. * Transmission When both KBIOE and KBTS are set to 1, the KCIF is set after the first falling edge of KCLK has been detected. At this time, if KCIE is set to 1, the CPU is requested an interrupt. KCIF is set at the same time when the TXCR3 to TXCR0 bits in KBCR2 are incremented from B'0000 to B'0001. * Determining interrupt generation By checking the KBE, KBTS, and KBTE bits, it can be determined whether the first KCLK falling interrupt is occurred during reception or transmission. During reception: KBE = 1 During transmission: KBTS = 1 or KBTE = 1 (Check KBTE = 1 because the KBTS is automatically cleared after transfer has been completed.)
KCLK KD
1
2
3
KCLK KD TXCR3 to TXCR0 Interrupt internal signal
I/O inhibit
1
2
Start bit
0 0010
1
Start bit 0000
0 0001
1 0010
RXCR3 0001 to RXCR0 0000 Interrupt internal signal Interrupt generated
Interrupt generated (b) Transmission
(a) Reception
Figure 17.15 Timing of First KCLK Interrupt
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Section 17 Keyboard Buffer Control Unit (KBU)
* Canceling software standby mode, watch mode, and subsleep mode Software standby, watch, and subsleep modes are cancelled by a first KCLK falling interrupt. In this case, an interrupt is generated at the first KCLK since software standby mode, watch mode, or subsleep mode has been shifted (figure 17.17). Notes on canceling operation are explained below. When a transition to software standby mode, watch mode, or subsleep mode is performed while both KBIOE and KCIE are set to 1, canceling the current mode is enabled by an first KCLK falling interrupt (the KBE and KBTS are not affected). When software standby mode, watch mode, and subsleep mode are cancelled by a first KCLK falling interrupt, the KCIF flag is not set (only the internal flag is set). In the first KCLK interrupt handling routine, the KCIF bit is checked. If the KCIF is 0, it indicates that the interrupt is generated after software standby mode, watch mode, and subsleep mode have been cancelled. When software standby mode, watch mode, or subsllep mode is cancelled by receiving a receive clock, the reception is ignored. Execute reception terminating processing by an interrupt handing routine, and then request retransfer. When transition to software standby mode, watch mode, or subsleep mode and canceling the mode by a first KCLK falling interrupt are performed during data transmission, state before performing mode transition is held immediately after canceling the mode. Therefore, initialization by an interrupt handling routine is required. Precautions as (b) and (c) which are shown in figure 17.16 should be applied on interrupt generation. Priority of canceling software standby mode, watch mode, and subsleep mode are decided by the setting of ICR. The interrupt signal path and flag setting of the first KCLK interrupt in normal operation differ from those in software standby mode, watch mode, and subsleep mode. Figure 17.6 shows the interrupt signal paths of the first KCLK interrupt. Signal A: Interrupt signal in normal operation Signal B: Interrupt signal in software standby mode, watch made, and subsleep mode KCLK is input directly to the interrupt control block, not through the KBU, in software standby mode, watch mode, and subsleep mode, and then an interrupt is generated by detection of a falling edge. Therefore, the KCIF flag is not set. In this case, a flag that is in the interrupt control block is set. The internal flag is automatically cleared after an interrupt request is sent to the CPU. Figure 17.18 shows setting and clearing timing.
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Section 17 Keyboard Buffer Control Unit (KBU)
Software standby mode, watch mode, subsleep mode
Interrupt control block B KCLK KBU Interrupt control A Falling edge detection circuit
Interrupt vector generation circuit
Interrupt request to CPU
Figure 17.16 First KCLK Interrupt Path
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Section 17 Keyboard Buffer Control Unit (KBU)
(a) Interrupt timing in software standby mode, watch mode, and subsleep mode 1 KCLK Software standby mode, watch mode, subsleep internal signal Interrupt internal signal Interrupt generated 2
(b) When a transition to software standby mode, watch mode, or subsleep mode is performed while the KCLI is high 4 KCLK Software standby mode, watch mode, subsleep internal signal Interrupt internal signal Interrupt generated 5 6
(c) When a transition to software standby mode, watch mode, or subsleep mode is performed while the KCLK is low 4 KCLK Software standby mode, watch mode, subsleep internal signal Interrupt internal signal Interrupt generated 5 6
Figure 17.17 Interrupt Timing in Software Standby Mode, Watch Mode, and Subsleep Mode
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Section 17 Keyboard Buffer Control Unit (KBU)
1 KCLK First KCLK falling edge
2
3
Internal flag
Automatic clear
Interrupt generated
Interrupt accepted (Accepted at any timing)
Figure 17.18 Internal Flag of First KCLK Falling Interrupt in Software Standby mode, Watch mode, and Subsleep mode
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Section 17 Keyboard Buffer Control Unit (KBU)
17.5
17.5.1
Usage Notes
KBIOE Setting and KCLK Falling Edge Detection
When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected. If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 17.19 shows the timing of KBIOE setting and KCLK falling edge detection.
T1
T2
KCLK (pin) Internal KCLK (KCLKI)
KBIOE
Falling edge signal
KBFSEL KBE
KBF
Figure 17.19 KBIOE Setting and KCLK Falling Edge Detection Timing
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Section 17 Keyboard Buffer Control Unit (KBU)
17.5.2
KD Output by KDO bit (KBCRL) and by Automatic Transmission
Figure 17.20 shows the relationship between the KD output by the KDO bit (KBCRL) and by the automatic transmission. Switch to the KD output by the automatic transmission is performed when KBTS is set to 1 and TXCR is not cleared to 0. In this case, the KD output by the KDO bit (KBCRL) is masked.
Output switch signal KBTS * (TXCR0 + TXCR1 + TXCR2 + TXCR3)
Output by KDO bit (KBCRL) KD output Output by automatic transmission
Figure 17.20 KDO Output 17.5.3 Module Stop Mode Setting
Keyboard buffer control unit operation can be enabled or disabled using the module stop control register. The initial setting is for keyboard buffer control unit operation to be halted. Register access is enabled by canceling module stop mode. For details, see section 24, Power-Down Modes. 17.5.4 Medium Speed Mode
The KBU operates with a medium speed clock in medium speed mode. To operate the KBU normally, use at least 300-kHz medium speed clock. 17.5.5 Transmit Completion Flag (KBTE)
When TXCR3 to TXCR0 are 1011 (transmit completion notification) and then the TXCR3 to TXCR0 are initialized by clearing KBIOE or KBTS to 0, the transmit completion flag (KBTE) is set. In this case, KTER is invalid.
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Section 18 LPC Interface (LPC)
Section 18 LPC Interface (LPC)
This LSI has an on-chip LPC interface. The LPC includes four register sets, each of which comprises data and status registers, control register, the fast Gate A20 logic circuit, and the host interrupt request circuit. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. This LPC module supports I/O read, I/O write, LPC memory read, LPC memory write, firmware (FW) memory read, and firmware (FW) memory write cycle transfers. It is also provided with power-down functions that can control the PCI clock and shut down the LPC interface.
18.1
Features
* Supports LPC interface I/O read and I/O write cycles Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data. Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME). * Four register sets comprising data and status registers The basic register set comprises three bytes: an input register (IDR), output register (ODR), and status register (STR). Fixed I/O addresses of H'60/H'64 are set for channel 1. A fast Gate A20 function is also provided. Fixed I/O addresses of H'62/H'66 are set for channel 2. I/O addresses from H'0000 to H'FFFF is selected for channel 3. Sixteen bidirectional data register bytes can be manipulated in addition to the basic register set. I/O addresses from H'0000 to H'FFFF is selected for channel 4. * Supports SERIRQ Host interrupt requests are transferred serially on a single signal line (SERIRQ). On channel 1, HIRQ1 and HIRQ12 can be generated. On channels 2, 3 and 4, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated. Operation can be switched between quiet mode and continuous mode. The CLKRUN signal can be manipulated to restart the PCI clock (LCLK). * Power-down modes and interrupts The LPC module can be shut down by inputting the LPCPD signal. Three pins, PME, LSMI, and LSCI, are provided for general input/output.
IFHSTL0A_000020020700
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Section 18 LPC Interface (LPC)
* Supports LPC/FW memory cycles Supports LPC memory read, LPC memory write, FW memory read, and FW memory write cycle transfer FW memory read and FW memory write cycles can be transferred in bytes/words/longwords LPC and FW memory cycles support the flash memory programming, flash memory erasing, and user commands * Supports docking LPC LAD3 toLAD0, LFRAME, LRESET, SERIRQ, CLKRUN, and LDRQ can be connected to DLAD3 to DLAD0, DLFRAME, DLRESET, DSERIRQ, DCLKRUN, and DLDRQ, respectively. Resistance is 40 (typ.).
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Section 18 LPC Interface (LPC)
Figure 18.1 shows a block diagram of the LPC.
LDRQ
Module data bus TWR0MW TWR1 to TWR15 IDR4 IDR3 IDR2 IDR1
PTCNT2
DLDRQ
Parallel serial conversion
SERIRQ DSERIRQ
SIRQCR0 SIRQCR1
CLKRUN DCLKRUN
Cycle detection
SIRQCR2
DLAD0 to DLAD3
Serial parallel conversion
Control logic HISEL
LPC/FW memory cycle set register
LPCPD LFRAME DLFRAME LRESET LCLK
Address match
LAD0 to LAD3
H'60/64 H'62/66 LADR3H/L LADR4H/L Serial parallel conversion
LSCIE LSCIB LSCI input LSMIE LSMIB LSMI input PMEE PMEB PME input HICR0
LSCI
LSMI
PME
SYNC output ODR4 TWR0SW TWR1 to TWR15 ODR3 ODR2 ODR1 STR4 STR3 STR2 STR1
HICR1 HICR2 HICR3 HICR4 LMCI LMCUI IBFI4 IBFI3 IBFI2 IBFI1 ERRI GA20
Internal interrupt control
[Legend] HICR0 to HICR4: Host interface control registers 0 to 4 LADR3H, LADR3L: LPC channel 3 address registers H and L LADR4H, LADR4L: LPC channel 4 address registers H and L IDR1 to IDR4: Input data registers 1 to 4 ODR1 to ODR4: Output data registers 1 to 4 STR1 to STR4: Status registers 1 to 4
TWR0MW: Bidirectional data register 0MW TWR0SW: Bidirectional data register 0SW TWR1 to TWR15: Bidirectional data registers 1 to 15 SERIRQ0 to SERIRQ2: SERIEQ control registers 0 to 2 HISEL: Host interface select register PTCNT2: Port control register 2
Figure 18.1 Block Diagram of LPC
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Section 18 LPC Interface (LPC)
18.2
Input/Output Pins
Table 18.1 lists the LPC pin configuration. Table 18.1 Pin Configuration
Name LPC address/ data 3 to 0 LPC frame LPC reset LPC clock Serialized interrupt request Abbreviation Port I/O Function Cycle type/address/data signals serially (4-signal-line) transferred in synchronization with LCLK Transfer cycle start and forced termination signal LPC interface reset signal 33-MHz PCI clock signal Serialized host interrupt request signal (SMI, HIRQ1, HIRQ6, HIRQ9 to HIRQ12) in synchronization with LCLK General output General output General output Gate A20 control signal output LCLK restart request signal when serial host interrupt is requested LPC module shutdown signal Cycle type/address/data signals serially (4-signal-line) transferred in synchronization with LCLK Transfer cycle start and forced termination signal Serialized host interrupt request signal in synchronization with LCLK LCLK restart request signal when serial host interrupt is requested
LAD3 to LAD0 P33 to P30 I/O
LFRAME LRESET LCLK SERIRQ
P34 P35 P36 P37
Input*1 Input*1 Input I/O*
1
LSCI general output LSMI general output PME general output GATE A20 LPC clock run LPC power-down Docking LPC address/ data 3 to 0 Docking LPC frame
LSCI LSMI PME GA20 CLKRUN LPCPD DLAD3 to DLAD0 DLFRAME
PB1 PB0 P80 P81 P82 P83
Output*1, *2 Output*1, *2 Output*1, *2 Output*1, *2 I/O* *
1, 2
Input*1
3
PB4 to PB7 I/O*
PB3 P40 P41
I/O*3 I/O*3 I/O*3
Docking serialized DSERIRQ interrupt request Docking LPC clock run DCLKRUN
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Section 18 LPC Interface (LPC)
Name LPC Encoded DMA request Docking LPC Encoded DMA request
Abbreviation LDRQ DLDRQ
Port PC6 PC7
I/O Output* Input*4
4
Function DMA request signal DMA request signal
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control input/output function. 2. Only 0 can be output. If 1 is output, the pin is in the high-impedance state, so an external resistor is necessary to pull the signal up to VCC. 3. This function becomes available by setting 1 to LPCS in PTCNT2 and one of LPC3E to LPC1E in HICR0 and LPC4E in HICR4. For details, see section 8.17.3, Port Control Register 2 (PTCNT2). 4. This function becomes available by setting 1 to LDRQS in PTCNT2 and one of LPC3E to LPC1E in HICR0 and LPC4E in HICR4. For details, see section 8.17.3, Port Control Register 2 (PTCNT2).
18.3
Register Descriptions
The LPC has the following registers. * * * * * * * * * Host interface control registers 0 to 4 (HICR0 to HICR4) LPC channel 3 address registers H and L (LADR3H, LADR3L) LPC channel 4 address registers H and L (LADR4H, LADR4L) Input data registers 1 to 4 (IDR1 to IDR4) Output data registers 1 to 4 (ODR1 to ODR4) Bidirectional data registers 0 to 15 (TWR0 to TWR15) Status registers 1 to 4 (STR1 to STR4) SERIRQ control registers 0 to 2 (SIRQCR0 to SIRQCR2) Host interface select register (HISEL)
The following registers are needed to use LPC/FW memory cycles. * RAM buffer address register (RBUFAR) * Flash memory programming address registers H and L (FLWARH, FLWARL) * Manufacture and device ID code registers (LMCMIDCR, LMCDIDCR) * Erase block register (EBLKR) * LMC status registers 1 and 2 (LMCST1, LMCST2) * LMC control registers 1 and 2 (LMCCR1, LMCCR2)
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Section 18 LPC Interface (LPC)
* * * * * * * * * * * *
Host base address registers 1H and 1L (HBAR1H, HBAR1L) Host base address registers 2H and 2L (HBAR2H, HBAR2L) On-chip RAM host base address registers H and L (RAMBARH, RAMBARL) Address space set register (ASSR) On-chip RAM address space set register (RAMASSR) Slave address register 1 (SAR1) Slave address register 2 (SAR2) On-chip RAM slave address register (RAMAR) Flash memory write protect registers H, M, and L (FWPRH, FWPRM, FWPRL) Flash memory read protect registers H, M, and L (FRPRH, FRPRM, FRPRL) On-chip RAM protect control register (MPCR) User command data register (UCMDTR)
Notes: R/W in the register description means as follows: 1. R/W slave indicates access from the slave (this LSI). 2. R/W host indicates access from the host.
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Section 18 LPC Interface (LPC)
18.3.1
Host Interface Control Registers 0 and 1 (HICR0 and HICR1)
HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits that determine pin output and the internal state of the LPC interface, and status flags that monitor the internal state of the LPC interface. * HICR0
R/W Bit 7 6 5 Bit Name Initial Value Slave Host Description LPC3E LPC2E LPC1E 0 0 0 R/W R/W R/W LPC Enables 3 to 1 Enable or disable the LPC interface function. When the LPC interface is enabled (one of the three bits is set to 1), processing for data transfer between the slave (this LSI) and the host is performed using pins LAD3 to LAD0, LFRAME, LRESET, LCLK, SERIRQ, CLKRUN, and LPCPD. * LPC3E 0: LPC channel 3 operation is disabled No address (LADR3) matches for IDR3, ODR3, STR3, or TWR0 to TWR15 1: LPC channel 3 operation is enabled * LPC2E 0: LPC channel 2 operation is disabled No address (H'0062, 66) matches for IDR2, ODR2, or STR2 1: LPC channel 2 operation is enabled * LPC1E 0: LPC channel 1 operation is disabled No address (H'0060, 64) matches for IDR1, ODR1, or STR1 1: LPC channel 1 operation is enabled
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Section 18 LPC Interface (LPC)
R/W Bit 4 Bit Name Initial Value Slave Host Description FGA20E 0 R/W Fast Gate A20 Function Enable Enables or disables the fast Gate A20 function. When the fast Gate A20 is disabled, the normal Gate A20 can be implemented by firmware controlling P81 output. 0: Fast Gate A20 function disabled Other function (input/output) of pin P81 is enabled The internal state of GA20 output is initialized to 1 1: Fast Gate A20 function enabled GA20 pin output is open-drain (external pull-up resistor (Vcc) required) 3 SDWNE 0 R/W LPC Software Shutdown Enable Controls LPC interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 18.4.4, LPC Interface Shutdown Function (LPCPD). 0: Normal state, LPC software shutdown setting enabled [Clearing conditions] * * * Writing 0 LPC hardware reset or LPC software reset LPC hardware shutdown release (rising edge of LPCPD signal)
1: LPC hardware shutdown state setting enabled Hardware shutdown state when LPCPD signal is low level [Setting condition] * Writing 1 after reading SDWNE = 0
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Section 18 LPC Interface (LPC)
R/W Bit 2 Bit Name Initial Value Slave Host Description PMEE 0 R/W PME Output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor (Vcc) is needed. PMEE 0 1 1 1 LSMIE 0 R/W PMEB X 0 1 : PME output disabled, other function of pin is enabled : PME output enabled, PME pin output goes to 0 level : PME output enabled, PME pin output is high-impedance
LSMI output Enable Controls LSMI output in combination with the LSMIB bit in HICR1. LSMI pin output is open-drain, and an external pull-up resistor (Vcc) is needed. LSMIE 0 1 1 LSMIB X 0 1 : LSMI output disabled, other function of pin is enabled : LSMI output enabled, LSMI pin output goes to 0 level : LSMI output enabled, LSMI pin output is Hi-Z
0
LSCIE
0
R/W
LSCI output Enable Controls LSCI output in combination with the LSCIB bit in HICR1. LSCI pin output is open-drain, and an external pull-up resistor (Vcc) is needed. LSCIE 0 1 1 LSCIB X 0 1 : LSCI output disabled, other function of pin is enabled : LSCI output enabled, LSCI pin output goes to 0 level : LSCI output enabled, LSCI pin output is high-impedance
[Legend] X: Don't care
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Section 18 LPC Interface (LPC)
* HICR1
R/W Bit 7 Bit Name Initial Value Slave Host Description LPCBSY 0 R LPC Busy Indicates that the LPC interface is processing a transfer cycle. 0: LPC interface is in transfer cycle wait state * * Bus idle, or transfer cycle not subject to processing is in progress Cycle type or address indeterminate during transfer cycle LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown Forced termination (abort) of transfer cycle subject to processing Normal termination of transfer cycle subject to processing
[Clearing conditions] * * * *
1: LPC interface is performing transfer cycle processing [Setting condition] * Match of cycle type and address
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Section 18 LPC Interface (LPC)
R/W Bit 6 Bit Name Initial Value Slave Host Description CLKREQ 0 R LCLK Request Indicates that the LPC interface's SERIRQ output is requesting a restart of LCLK. 0: No LCLK restart request [Clearing conditions] * * * LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown There are no further interrupts for transfer to the host in quiet mode in which SERIRQ is set to continuous mode
1: LCLK restart request issued [Setting condition] * 5 IRQBSY 0 R In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is stopped
SERIRQ Busy Indicates that the LPC interface's SERIRQ is engaged in transfer processing. 0: SERIRQ transfer frame wait state [Clearing conditions] * * * LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown End of SERIRQ transfer frame
1: SERIRQ transfer processing in progress [Setting condition] * Start of SERIRQ transfer frame
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Section 18 LPC Interface (LPC)
R/W Bit 4 Bit Name Initial Value Slave Host Description LRSTB 0 R/W LPC Software Reset Bit Resets the LPC interface. For the scope of initialization by an LPC reset, see section 18.4.4, LPC Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] * * Writing 0 LPC hardware reset
1: LPC software reset state [Setting condition] * 3 SDWNB 0 R/W Writing 1 after reading LRSTB = 0 LPC Software Shutdown Bit Controls LPC interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 18.4.4, LPC Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] * * * * Writing 0 LPC hardware reset or LPC software reset LPC hardware shutdown (falling edge of LPCPD signal when SDWNE = 1) LPC hardware shutdown release (rising edge of LPCPD signal when SDWNE = 0) 1: LPC software shutdown state [Setting condition] * 2 PMEB 0 R/W Writing 1 after reading SDWNB = 0 PME Output Bit Controls PME output in combination with the PMEE bit. For details, refer to description on the PMEE bit in HICR0.
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Section 18 LPC Interface (LPC)
R/W Bit 1 Bit Name Initial Value Slave Host Description LSMIB 0 R/W LSMI Output Bit Controls LSMI output in combination with the LSMIE bit. For details, refer to description on the LSMIE bit in HICR0. 0 LSCIB 0 R/W LSCI output Bit Controls LSCI output in combination with the LSCIE bit. For details, refer to description on the LSCIE bit in HICR0.
18.3.2
Host Interface Control Registers 2 and 3 (HICR2 and HICR3)
HICR2 controls interrupts to an LPC interface slave (this LSI). HICR3 monitors the states of the LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset or in hardware standby mode. The states of other bits are decided by the pin states. The pin states can be monitored by the pin monitoring bits regardless of the LPC interface operating state or the operating state of the functions that use pin multiplexing. * HICR2
R/W Bit 7 6 Bit Name Initial Value Slave Host Description GA20 LRST Undefined 0 R GA20 Pin Monitor LPC Reset Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware reset occurs. 0: [Clearing condition] * * Writing 0 after reading LRST = 1 LRESET pin falling edge detection 1: [Setting condition] R/(W)*
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Section 18 LPC Interface (LPC)
R/W Bit 5 Bit Name Initial Value Slave Host Description SDWN 0 R/(W)* LPC Shutdown Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware shutdown request is generated. 0: [Clearing conditions] * * * * 4 ABRT 0 R/(W)* Writing 0 after reading SDWN = 1 LPC hardware reset (LRESET pin falling edge detection) LPC software reset (LRSTB = 1) LPCPD pin falling edge detection 1: [Setting condition] LPC Abort Interrupt Flag This bit is a flag that generates an ERRI interrupt when a forced termination (abort) of an LPC transfer cycle occurs. 0: [Clearing conditions] * * * * Writing 0 after reading ABRT = 1 LPC hardware reset (LRESET pin falling edge detection) LPC software reset (LRSTB = 1) LPC hardware shutdown (SDWNE = 1 and LPCPD pin falling edge detection) * * LPC software shutdown (SDWNB = 1) LFRAME pin falling edge detection during LPC transfer cycle 1: [Setting condition]
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Section 18 LPC Interface (LPC)
R/W Bit 3 Bit Name Initial Value Slave Host Description IBFIE3 0 R/W IDR3 and TWR Receive Complete interrupt Enable Enables or disables IBFI3 interrupt to the slave (this LSI). 0: Input data register IDR3 and TWR receive complete interrupt requests disabled 1: [When TWRIE = 0 in LADR3] Input data register (IDR3) receive complete interrupt requests enabled [When TWRIE = 1 in LADR3] Input data register (IDR3) and TWR receive complete interrupt requests enabled 2 IBFIE2 0 R/W IDR2 Receive Complete interrupt Enable Enables or disables IBFI2 interrupt to the slave (this LSI). 0: Input data register (IDR2) receive complete interrupt requests disabled 1: Input data register (IDR2) receive complete interrupt requests enabled 1 IBFIE1 0 R/W IDR1 Receive Complete interrupt Enable Enables or disables IBFI1 interrupt to the slave (this LSI). 0: Input data register (IDR1) receive complete interrupt requests disabled 1: Input data register (IDR1) receive complete interrupt requests enabled 0 ERRIE 0 R/W Error Interrupt Enable Enables or disables ERRI interrupt to the slave (this LSI). 0: Error interrupt requests disabled 1: Error interrupt requests enabled Note: * Only 0 can be written to bits 6 to 4, to clear the flag.
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Section 18 LPC Interface (LPC)
* HICR3
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description LFRAME Undefined CLKRUN Undefined SERIRQ LRESET LPCPD PME LSMI LSCI Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R R LFRAME Pin Monitor CLKRUN Pin Monitor SERIRQ Pin Monitor LRESET Pin Monitor LPCPD Pin Monitor PME Pin Monitor LSMI Pin Monitor LSCI Pin Monitor
18.3.3
Host Interface Control Register 4 (HICR4)
HICR4 enables/disables channel 4 and controls interrupts to the channel 4 of an LPC interface slave (this LSI).
R/W Bit 7 6 Bit Name Initial Value Slave Host Description LPC4E 0 0 R/W R/W Reserved The initial value bit should not be changed. LPC Enable 4 0: LPC channel 4 is disabled For IDR4, ODR4, and STR4, address (LADR4) match is not occurred. 1: LPC channel 4 enabled 5 IBFIE4 0 R/W IDR4 Receive Completion Enable Enables or disables IBFI4 interrupt to the slave (this LSI). 0: Input data register (IDR4) receive complete interrupt requests disabled 1: Input data register (IDR4) receive complete interrupt requests enabled 4 to 0 All 0 R/W Reserved The initial value should not be changed.
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Section 18 LPC Interface (LPC)
18.3.4
LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)
LADR3 stores the LPC channel 3 host address and controls the operation of the bidirectional data registers. The contents of the address fields in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1). * LADR3H
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Channel 3 Address Bits 15 to 8 Store the LPC channel 3 host address.
* LADR3L
R/W Bit 7 6 5 4 3 2 1 Bit Name Initial Value Slave Host Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Reserved The initial value should not be changed. Channel 3 Address Bit 1 Sets the LPC channel 3 host address. Channel 3 Address Bits 7 to 3 Set the LPC channel 3 host address.
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Section 18 LPC Interface (LPC)
R/W Bit 0 Bit Name Initial Value Slave Host Description TWRE 0 R/W Bidirectional Data Register Enable Enables or disables bidirectional data register operation. 0: TWR operation is disabled TWR-related I/O address match determination is halted 1: TWR operation is enabled
When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4 in LADR3 is inverted, and the values of bits 3 to 0 are ignored. * Host select register
I/O Address Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 0 0 : 1 Bit 4 Bit 4 0 0 : 1 Note: * Bit 2 0 1 0 1 0 0 : 1 0 0 : 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 0 0 : 1 0 0 : 1 Bit 0 0 0 0 0 0 1 : 1 0 1 : 1 I/O read I/O read TWR0SW read TWR1 to TWR15 read Transfer Cycle I/O write I/O write I/O read I/O read I/O write I/O write
Host Select Register IDR3 write, C/D3 0 IDR3 write, C/D3 1 ODR3 read STR3 read TWR0MW write TWR1 to TWR15 write
When channel 3 is used, the content of LADR3 must be set so that the addresses for channels 1, 2, and 4 are different.
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Section 18 LPC Interface (LPC)
18.3.5
LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)
LADR4 stores the LPC channel 4 host address. The LADR4 contents must not be changed while channel 4 is operating (while LPC4E is set to 1). * LADR4H
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Channel 4 Address Bits 15 to 8 Store the LPC channel 4 host address.
* LADR4L
R/W Bit 7 6 5 4 3 2 Bit Name Initial Value Slave Host Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit2 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Reserved This bit is ignored when an address match is decided. 1 0 Bit 1 Bit 0 0 0 R/W R/W Channel 4 Address Bits 1 and 0 Set the LPC channel 4 host address. Channel 4 Address Bits 7 to 3 Set the LPC channel 4 host address.
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Section 18 LPC Interface (LPC)
* Host select register
I/O Address Bits 5 to 3 Bits 15 to 3 in LADR4 Bits 15 to 3 in LADR4 Bits 15 to 3 in LADR4 Bits 15 to 3 in LADR4 Note: * Bit 2 0 1 0 1 Bits 1 and 0 Bits 1 and 0 in LADR4 Bits 1 and 0 in LADR4 Bits 1 and 0 in LADR4 Bits 1 and 0 in LADR4 Transfer Cycle I/O write I/O write I/O read I/O read
Host Select Register IDR4 write (data) IDR4 write (command) ODR4 read STR4 read
When channel 4 is used, the content of LADR4 must be set so that the addresses for channels 1, 2, and 3 are different.
18.3.6
Input Data Registers 1 to 4 (IDR1 to IDR4)
IDR1 to IDR4 are 8-bit read-only registers for the slave (this LSI), and 8-bit write-only registers for the host. The registers selected from the host according to the I/O address are shown in the following table. For information on IDR3 and IDR4 selection, see the section of the corresponding LADR. Data transferred in an LPC I/O write cycle is written to the selected register. The value of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether the written information is a command or data. The initial values of IDR1 to IDR4 are undefined.
I/O Address Bits 15 to 4 Bits 15 to 4 Bits 15 to 4 n = 1 to 4 Note: In bits 15 to 0, channel 1 corresponds to H'0060/H'0064, channel 2 corresponds to H'0062/H'0066. Bit 3 Bit 3 Bit 3 Bit 2 0 1 Bit 1 Bit 1 Bit 1 Bit 0 Bit 0 Bit 0 Transfer Cycle I/O write I/O write
Host Register Selection IDRn write, C/Dn 0 IDRn write, C/Dn 1
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Section 18 LPC Interface (LPC)
18.3.7
Output Data Registers 1 to 4 (ODR1 to ODR4)
ODR1 to ODR4 are 8-bit readable/writable registers for the slave (this LSI), and 8-bit read-only registers for the host. The registers selected from the host according to the I/O address are shown in the following table. For information on ODR3 and ODR4 selection, see the section of the corresponding LADR. In an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of ODR1 to ODR4 are undefined.
I/O Address Bits 15 to 4 Bits 15 to 4 n = 1 to 4 Note: In bits 15 to 0, channel 1 and channel 2 corresponds to H'0060 and H'0062, respectively. Bit 3 Bit 3 Bit 2 0 Bit 1 Bit1 Bit 0 Bit 0 Transfer Cycle I/O read
Host Register Selection ODRn read
18.3.8
Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave (this LSI) and host. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host and the slave addresses. TWR0MW is a write-only register for the host, and a read-only register for the slave, while TWR0SW is a write-only register for the slave and a read-only register for the host. When the host and slave begin a write, after the respective registers of TWR0 have been written to, arbitration for simultaneous access is performed by checking the status flags whether or not those writes were valid. For the registers selected from the host according to the I/O address, see section 18.3.4, LPC Channel 3 Address Registers H and L (LADR3H and LADR3L). Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of TWR0 to TWR15 are undefined.
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Section 18 LPC Interface (LPC)
18.3.9
Status Registers 1 to 4 (STR1 to STR4)
STR1 to STR4 are 8-bit registers that indicate status information during LPC interface processing. The registers selected from the host according to the I/O address are shown in the following table. For information on STR3 and STR4 selection, see the section of the corresponding LADR. In an LPC I/O read cycle, the data in the selected register is transferred to the host.
I/O Address Bits 15 to 4 Bits 15 to 4 n = 1 to 4 Note: In bits 15 to 0, channel 1 and channel 2 corresponds to H'0064 and H'0066, respectively. Bit 3 Bit 3 Bit 2 1 Bit 1 Bit1 Bit 0 Bit 0 Transfer Cycle I/O read
Host Register Selection STRn read
* STR1
R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave DBU17 DBU16 DBU15 DBU14 C/D1 0 0 0 0 0 R/W R/W R/W R/W R Host Description R R R R R Command/Data When the host writes to IDR1, bit 2 of the I/O address is written into this bit to indicate whether IDR1 contains data or a command. 0: Content of input data register (IDR1) is a data 1: Content of input data register (IDR1) is a command 2 DBU12 0 R/W R Defined by User The user can use this bit as necessary. Defined by User The user can use these bits as necessary.
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Section 18 LPC Interface (LPC)
R/W Bit 1 Bit Name Initial Value Slave IBF1 0 R Host Description R Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). The IBF1 flag setting and clearing conditions are different when the fast Gate A20 is used. For details, see table 18.4. 0: [Clearing condition] When the slave reads IDR1 1: [Setting condition] When the host writes to IDR1 in I/O write cycle 0 OBF1 0 R/(W)* R Output Buffer Full 0: [Clearing conditions] * * * Note: * Only 0 can be written to clear the flag. When the host reads ODR1 in I/O read cycle When the slave writes 0 to the OBF1 bit When the slave writes to ODR1
1: [Setting condition]
* STR2
R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave DBU27 DBU26 DBU25 DBU24 C/D2 0 0 0 0 0 R/W R/W R/W R/W R Host Description R R R R R Command/Data When the host writes to IDR2, bit 2 of the I/O address is written into this bit to indicate whether IDR2 contains data or a command. 0: Content of input data register (IDR2) is a data 1: Content of input data register (IDR2) is a command 2 DBU22 0 R/W R Defined by User The user can use this bit as necessary. Defined by User The user can use these bits as necessary.
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Section 18 LPC Interface (LPC)
R/W Bit 1 Bit Name Initial Value Slave IBF2 0 R Host Description R Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads IDR2 1: [Setting condition] When the host writes to IDR2 in I/O write cycle 0 OBF2 0 R/(W)* R Output Buffer Full 0: [Clearing conditions] * * * Note: * Only 0 can be written to clear the flag. When the host reads ODR2 in I/O read cycle When the slave writes 0 to the OBF2 bit When the slave writes to ODR2
1: [Setting condition]
* STR3 (TWRE = 1 or SELSTR3 = 0)
R/W Bit 7 Bit Name Initial Value Slave IBF3B 0 R Host Description R Bidirectional Data Register Input Buffer Full Flag This is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads TWR15 1: [Setting condition] When the host writes to TWR15 in I/O write cycle 6 OBF3B 0 R/(W)* R Bidirectional Data Register Output Buffer Full Flag 0: [Clearing conditions] * * * When the host reads TWR15 in I/O read cycle When the slave writes 0 to the OBF3B bit When the slave writes to TWR15
1: [Setting condition]
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Section 18 LPC Interface (LPC)
R/W Bit 5 Bit Name Initial Value Slave MWMF 0 R Host Description R Master Write Mode Flag 0: [Clearing condition] When the slave reads TWR15 1: [Setting condition] When the host writes to TWR0 in I/O write cycle while SWMF = 0 4 SWMF 0 R/(W)* R Slave Write Mode Flag In the event of simultaneous writes by the master and the slave, the master write has priority. 0: [Clearing conditions] * * * 3 C/D3 0 R R When the host reads TWR15 in I/O read cycle When the slave writes 0 to the SWMF bit When the slave writes to TWR0 while MWMF = 0
1: [Setting condition]
Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data 1: Content of input data register (IDR3) is a command
2 1
DBU32 IBF3A
0 0
R/W R
R R
Defined by User The user can use this bit as necessary. Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads IDR3 1: [Setting condition] When the host writes to IDR3 in I/O write cycle
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Section 18 LPC Interface (LPC)
R/W Bit 0 Bit Name Initial Value Slave OBF3A 0 Host Description Output Buffer Full 0: [Clearing conditions] * * * Note: * Only 0 can be written to clear the flag. When the host reads ODR3 in I/O read cycle When the slave writes 0 to the OBF3 bit When the slave writes to ODR3
R/(W)* R
1: [Setting condition]
* STR3 (TWRE = 0 and SELSTR3 = 1)
R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU37 DBU36 DBU35 DBU34 C/D3 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data 1: Content of input data register (IDR3) is a command 2 1 DBU32 IBF3 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads IDR3 1: [Setting condition] When the host writes to IDR3 in I/O write cycle Defined by User The user can use these bits as necessary.
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Section 18 LPC Interface (LPC)
R/W Bit 0 Bit Name Initial Value Slave Host Description OBF3 0 R/(W)* R Output Buffer Full 0: [Clearing conditions] * * * Note: * Only 0 can be written to clear the flag. When the host reads ODR3 in I/O read cycle When the slave writes 0 to the OBF3 bit When the slave writes to ODR3
1: [Setting condition]
* STR4
R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU47 DBU46 DBU45 DBU44 C/D4 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data Flag When the host writes to IDR4, bit 2 of the I/O address is written into this bit to indicate whether IDR4 contains data or a command. 0: Content of input data register (IDR4) is a data 1: Content of input data register (IDR4) is a command 2 1 DBU42 IBF4 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads IDR4 1: [Setting condition] When the host writes to IDR4 in I/O write cycle Defined by User The user can use these bits as necessary.
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Section 18 LPC Interface (LPC)
R/W Bit 0 Bit Name Initial Value Slave Host Description OBF4 0 R/(W)* R Output Buffer Full 0: [Clearing conditions] * * * Note: * Only 0 can be written to clear the flag. When the host reads ODR4 in I/O read cycle When the slave writes 0 to the OBF3 bit When the slave writes to ODR4
1: [Setting condition]
18.3.10 SERIRQ Control Register 0 (SIRQCR0) SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources.
R/W Bit 7 Bit Name Initial Value Slave Host Description Q/C 0 R Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame). 0: Continuous mode [Clearing conditions] * * LPC hardware reset, LPC software reset Specification by SERIRQ transfer cycle stop frame
1: Quiet mode [Setting condition] * Specification by SERIRQ transfer cycle stop frame.
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Section 18 LPC Interface (LPC)
R/W Bit 6 Bit Name Initial Value Slave Host Description SELREQ 0 R/W Start Frame Initiation Request Select Selects the condition of a start frame initiation request when a host interrupt request is cleared in quiet mode. 0: Start frame initiation is requested when all interrupt requests are cleared 1: Start frame initiation is requested when one or more interrupt requests are cleared 5 IEDIR2 0 R/W Interrupt Enable Direct Mode Specifies whether LPC channel 2 and channel 3 SERIRQ interrupt source (SMI, IRQ6, IRQ9 to IRQ11) generation is conditional upon OBF, or is controlled only by the host interrupt enable bit. 0: Host interrupt is requested when host interrupt enable and corresponding OBF bits are both set to 1 1: Host interrupt is requested when host interrupt enable bit is set to 1 4 SMIE3B 0 R/W Host SMI Interrupt Enable 3B Enables or disables an SMI interrupt request when OBF3B is set by a TWR15 write. 0: Host SMI interrupt request by OBF3B and SMIE3B is disabled [Clearing conditions] * * * Writing 0 to SMIE3B LPC hardware reset, LPC software reset Clearing OBF3B to 0 (when IEDIR3 = 0) Host SMI interrupt request by setting OBF3B to 1 is enabled [When IEDIR3 = 1] Host SMI interrupt is requested [Setting condition] * Writing 1 after reading SMIE3B = 0
1: [When IEDIR3 = 0]
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Section 18 LPC Interface (LPC)
R/W Bit 3 Bit Name Initial Value Slave Host Description SMIE3A 0 R/W Host SMI Interrupt Enable 3A Enables or disables an SMI interrupt request when OBF3A is set by an ODR3 write. 0: Host SMI interrupt request by OBF3A and SMIE3A is disabled [Clearing conditions] * * * Writing 0 to SMIE3A LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) Host SMI interrupt request by setting is enabled [When IEDIR3 = 1] Host SMI interrupt is requested [Setting condition] * 2 SMIE2 0 R/W Writing 1 after reading SMIE3A = 0 Host SMI Interrupt Enable 2 Enables or disables an SMI interrupt request when OBF2 is set by an ODR2 write. 0: Host SMI interrupt request by OBF2 and SMIE2 is disabled [Clearing conditions] * * * Writing 0 to SMIE2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) Host SMI interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] Host SMI interrupt is requested [Setting condition] * Writing 1 after reading SMIE2 = 0
1: [When IEDIR3 = 0]
1: [When IEDIR2 = 0]
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Section 18 LPC Interface (LPC)
R/W Bit 1 Bit Name Initial Value Slave Host Description IRQ12E1 0 R/W Host IRQ12 Interrupt Enable 1 Enables or disables an HIRQ12 interrupt request when OBF1 is set by an ODR1 write. 0: HIRQ12 interrupt request by OBF1 and IRQ12E1 is disabled [Clearing conditions] * * * Writing 0 to IRQ12E1 LPC hardware reset, LPC software reset Clearing OBF1 to 0
1: HIRQ12 interrupt request by setting OBF1 to 1 is enabled [Setting condition] * 0 IRQ1E1 0 R/W Writing 1 after reading IRQ12E1 = 0 Host IRQ1 Interrupt Enable 1 Enables or disables a host HIRQ1 interrupt request when OBF1 is set by an ODR1 write. 0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled [Clearing conditions] * * * Writing 0 to IRQ1E1 LPC hardware reset, LPC software reset Clearing OBF1 to 0
1: HIRQ1 interrupt request by setting OBF1 to 1 is enabled [Setting condition] * Writing 1 after reading IRQ1E1 = 0
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Section 18 LPC Interface (LPC)
18.3.11 SERIRQ Control Register 1 (SIRQCR1) SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources.
R/W Bit 7 Bit Name Initial Value Slave Host Description IRQ11E3 0 R/W Host IRQ11 Interrupt Enable 3 Enables or disables an HIRQ11 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ11 interrupt request by OBF3A and IRQE11E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ11E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ11 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ11 interrupt is requested [Setting condition] * Writing 1 after reading IRQ11E3 = 0
1: [When IEDIR3 = 0]
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Section 18 LPC Interface (LPC)
R/W Bit 6 Bit Name Initial Value Slave Host Description IRQ10E3 0 R/W Host IRQ10 Interrupt Enable 3 Enables or disables an HIRQ10 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ10 interrupt request by OBF3A and IRQE10E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ10E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ10 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ10 interrupt is requested [Setting condition] * 5 IRQ9E3 0 R/W Writing 1 after reading IRQ10E3 = 0 Host IRQ9 Interrupt Enable 3 Enables or disables an HIRQ9 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ9 interrupt request by OBF3A and IRQE9E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ9E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ9 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ9 interrupt is requested [Setting condition] * Writing 1 after reading IRQ9E3 = 0
1: [When IEDIR3 = 0]
1: [When IEDIR3 = 0]
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Section 18 LPC Interface (LPC)
R/W Bit 4 Bit Name Initial Value Slave Host Description IRQ6E3 0 R/W Host IRQ6 Interrupt Enable 3 Enables or disables an HIRQ6 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ6 interrupt request by OBF3A and IRQE6E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ6E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ6 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ6 interrupt is requested [Setting condition] * 3 IRQ11E2 0 R/W Writing 1 after reading IRQ6E3 = 0 Host IRQ11 Interrupt Enable 2 Enables or disables an HIRQ11 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ11 interrupt request by OBF2 and IRQE11E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ11E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ11 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ11 interrupt is requested [Setting condition] * Writing 1 after reading IRQ11E2 = 0
1: [When IEDIR3 = 0]
1: [When IEDIR2 = 0]
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Section 18 LPC Interface (LPC)
R/W Bit 2 Bit Name Initial Value Slave Host Description IRQ10E2 0 R/W Host IRQ10 Interrupt Enable 2 Enables or disables an HIRQ10 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ10 interrupt request by OBF2 and IRQE10E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ10E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ10 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ10 interrupt is requested [Setting condition] * 1 IRQ9E2 0 R/W Writing 1 after reading IRQ10E2 = 0 Host IRQ9 Interrupt Enable 2 Enables or disables an HIRQ9 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ9 interrupt request by OBF2 and IRQE9E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ9E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ9 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ9 interrupt is requested [Setting condition] * Writing 1 after reading IRQ9E2 = 0
1: [When IEDIR2 = 0]
1: [When IEDIR2 = 0]
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Section 18 LPC Interface (LPC)
R/W Bit 0 Bit Name Initial Value Slave Host Description IRQ6E2 0 R/W Host IRQ6 Interrupt Enable 3 Enables or disables an HIRQ6 interrupt request when OBF2 is set by an oDR2 write. 0: HIRQ6 interrupt request by OBF2 and IRQE6E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ6E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ6 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ6 interrupt is requested [Setting condition] * Writing 1 after reading IRQ6E2 = 0
1: [When IEDIR2 = 0]
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Section 18 LPC Interface (LPC)
18.3.12 SERIRQ Control Register 2 (SIRQCR2) SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host interrupt request outputs.
R/W Bit 7 Bit Name Initial Value Slave Host Description IEDIR3 0 R/W Interrupt Enable Direct Mode 3 Selects whether an SERIRQ interrupt generation of LPC channel 3 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable bit. 0: A host interrupt is generated when both the enable bit and the corresponding OBF flag are set 1: A host interrupt is generated when the enable bit is set 6 IEDIR4 0 R/W Interrupt Enable Direct Mode 4 Selects whether an SERIRQ interrupt generation of LPC channel 4 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable bit. 0: A host interrupt is generated when both the enable bit and the corresponding OBF flag are set 1: A host interrupt is generated when the enable bit is set
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Section 18 LPC Interface (LPC)
R/W Bit 5 Bit Name Initial Value Slave Host Description IRQ11E4 0 R/W Host IRQ11 Interrupt Enable 4 Enables or disables an HIRQ11 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ11 interrupt request by OBF4 and IRQE11E4 is disabled [Clearing conditions] * * * Writing 0 to IRQ11E4 LPC hardware reset, LPC software reset Clearing OBF4 to 0 (when IEDIR4 = 0) HIRQ11 interrupt request by setting OBF4 to 1 is enabled [When IEDIR4 = 1] HIRQ11 interrupt is requested [Setting condition] * 4 IRQ10E4 0 R/W Writing 1 after reading IRQ11E4 = 0 Host IRQ10 Interrupt Enable 4 Enables or disables an HIRQ10 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ10 interrupt request by OBF4 and IRQE10E4 is disabled [Clearing conditions] * * * Writing 0 to IRQ10E4 LPC hardware reset, LPC software reset Clearing OBF4 to 0 (when IEDIR4 = 0) HIRQ10 interrupt request by setting OBF4 to 1 is enabled [When IEDIR4 = 1] HIRQ10 interrupt is requested [Setting condition] * Writing 1 after reading IRQ10E4 = 0
1: [When IEDIR4 = 0]
1: [When IEDIR4 = 0]
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Section 18 LPC Interface (LPC)
R/W Bit 3 Bit Name Initial Value Slave Host Description IRQ9E4 0 R/W Host IRQ9 Interrupt Enable 4 Enables or disables an HIRQ9 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ9 interrupt request by OBF4 and IRQE9E4 is disabled [Clearing conditions] * * * Writing 0 to IRQ9E4 LPC hardware reset, LPC software reset Clearing OBF4 to 0 (when IEDIR4 = 0) HIRQ9 interrupt request by setting OBF4 to 1 is enabled [When IEDIR4 = 1] HIRQ9 interrupt is requested [Setting condition] * 2 IRQ6E4 0 R/W Writing 1 after reading IRQ9E4 = 0 Host IRQ6 Interrupt Enable 4 Enables or disables an HIRQ6 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ6 interrupt request by OBF4 and IRQE6E4 is disabled [Clearing conditions] * * * Writing 0 to IRQ6E4 LPC hardware reset, LPC software reset Clearing OBF4 to 0 (when IEDIR4 = 0) HIRQ6 interrupt request by setting OBF4 to 1 is enabled [When IEDIR4 = 1] HIRQ6 interrupt is requested [Setting condition] * Writing 1 after reading IRQ6E4 = 0
1: [When IEDIR4 = 0]
1: [When IEDIR4 = 0]
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Section 18 LPC Interface (LPC)
R/W Bit 1 Bit Name Initial Value Slave Host Description SMIE4 0 R/W Host SMI Interrupt Enable 4 Enables or disables an SMI interrupt request when OBF4 is set by an ODR4 write. 0: Host SMI interrupt request by OBF4 and SMIE4 is disabled [Clearing conditions] * * * Writing 0 to SMIE4 LPC hardware reset, LPC software reset Clearing OBF4 to 0 (when IEDIR4 = 0) Host SMI interrupt request by setting OBF4 to 1 is enabled [When IEDIR4 = 1] Host SMI interrupt is requested [Setting condition] * 0 0 R/W Writing 1 after reading SMIE4 = 0 Reserved The initial value should not be changed.
1: [When IEDIR4 = 0]
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Section 18 LPC Interface (LPC)
18.3.13 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt request signal of each frame.
Initial Value 0 R/W Slave Host Description R/W Status Register 3 Selection Selects the function of bits 7 to 4 in STR3 in combination with the TWRE bit in LADR3L. For details of STR3, see section 18.3.9, Status Registers 1 to 4 (STR1 to STR4). 0: Bits 7 to 4 in STR3 indicate processing status of the LPC interface. 1: [When TWRE = 1] Bits 7 to 4 in STR3 indicate processing status of the LPC interface. [When TWRE = 0] Bits 7 to 4 in STR3 are readable/writable bits which user can use as necessary 6 5 4 3 2 1 0 SELIRQ11 SELIRQ10 SELIRQ9 SELIRQ6 SELSMI SELIRQ12 SELIRQ1 0 0 0 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W SERIRQ Output Select Select the pin output status of SERIRQ. 0: [When host interrupt request is cleared] SERIRQ pin output is in the Hi-Z state [When host interrupt request is set] SERIRQ pin output is low 1: [When host interrupt request is cleared] SERIRQ pin output is low [When host interrupt request is set] SERIRQ pin output is in the Hi-Z state.
Bit 7
Bit Name SELSTR3
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Section 18 LPC Interface (LPC)
18.3.14 RAM Buffer Address Register (RBUFAR) RBUFAR stores the start address of 256-byte buffer in the on-chip RAM used for the flash memory programming in an LPC/FW memory cycle. The flash memory is programmed in units of 128 bytes. The 128-byte data is stored in the area whose lower address ranges from H'00 to H'7F. Bits 23 to 16 of the RAM buffer start address are fixed H'FF and bits 7 to 0 are fixed H'00. In the case of the initial value, the area to be used as a RAM buffer is from H'FFEF00 to H'FFEFFF (256 bytes). The contents of this register must not be changed in an LPC/FW memory cycle (the LMCE bit is set to 1).
R/W Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value Slave Host Description RBA15 RBA14 RBA13 RBA12 RBA11 RBA10 RBA9 RBA8 * 1 1 1 0 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W RAM Buffer Addresses 15 to 8 Though H'D0 to H'EF can be set, setting only H'D1 to H'EF is valid. Setting other than these values is invalid. When setting is invalid, the previous value is retained.
The value must be selected so that the program area for flash memory programming/erasure is not overlapped.
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Section 18 LPC Interface (LPC)
18.3.15 Flash Memory Programming Address Registers H and L (FLWARH and FLARL) FLWAR stores the start address of the flash memory programming in an LPC/FW memory cycle. Bits 19 to 7 of the start address set by the FLWAR set command are stored in this register. Bits 23 to 20 of the address are fixed H'0, and 6 to 0 are fixed H'00. * FLWARH
R/W Bit Bit Name Initial Value Slave Host Description All 0 0 0 0 0 0 R R R R R R W* W* W* W* W* Reserved These bits are read as 0 and cannot be modified. 4 3 2 1 0 Note: FWA19 FWA18 FWA17 FWA16 FWA15 * Flash Memory Programming Start Address 19 to 15 7 to 5
Can be written to by the FLWAR set command.
* FLWARL
R/W Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value Slave Host Description FWA14 FWA13 FWA12 FWA11 FWA10 FWA9 FWA8 FWA7 * 1 1 1 0 1 1 1 1 R R R R R R R R W* W* W* W* W* W* W* W* Flash Memory Programming Start Addresses 14 to 7
Can be written to by the FLWAR set command.
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Section 18 LPC Interface (LPC)
18.3.16 Manufacture ID Code Register (LMCMIDCR) and Device ID Code Register (LMCDIDCR) LMCMIDCR and LMCDIDCR store the manufacture ID code and device ID code, respectively. The contents of start address of LMCMIDCR and LMCDIDCR are output in response to the ID read command. For details of the ID read command, see descriptions of a list of LMC commands and command addresses. The contents of this register must not be changed in an LPC/FW memory cycle (the LMCE bit is set to 1). * LMCMIDCR
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R Indicate the manufacture ID.
* LMCDIDCR
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R Indicate the device ID.
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Section 18 LPC Interface (LPC)
18.3.17 Erase Block Register (EBLKR) EBLKR stores a block number set by the block erasure command.
R/W Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value Slave Host Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 * 0 0 0 0 0 0 0 0 R R R R R R R R W* W* W* W* W* W* W* W* EB22 EB23 Store a block number ranging from 0 to 23. The block number is specified in BCD code (binary coded decimal code). EB0 EB1 : H'22 H'23 H'00 H'01
H'0A to H'0F, H'1A to H'1F, H'24 to H'FF must not be selected.
Can be written to by the block erasure command.
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Section 18 LPC Interface (LPC)
18.3.18 LMC Status Registers 1 and 2 (LMCST1 and LMCST2) LMCST1 and LMCST2 indicate the processing status of the LMC. The contents of LMCST1 and LMCST2 are output in response to the status read command. For details of the status read command, see section 18.4.8, LPC/FW Memory Access Command. * LMCST1
R/W Bit 7 Bit Name Initial Value Slave FLPI 0
1
Host Description Flash Memory Programming Interrupt/End Flag Setting this bit by the flash memory programming command generates an FLPI interrupt (LMCI). 0: Flash memory programming command wait Flash memory programming end [Clearing condition] When writing 0 after reading FLPI = 1 1: Flash memory programming is in progress [Setting condition] When receiving by the flash memory programming command (BUFTRAN = 1)
R/(W)* R
6
FLEI
0
R/(W)*1 R
Flash Memory Erasing Interrupt/End Flag Setting this bit by the flash memory erasing command generates an FLEI interrupt (LMCI). 0: Flash memory erasing command wait Flash memory erasing end [Clearing condition] When writing 0 after reading FLEI = 1 1: Flash memory erasing is in progress [Setting condition] When receiving by the flash memory erasing command (ERASEE = 1)
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Section 18 LPC Interface (LPC)
R/W Bit 5 Bit Name Initial Value Slave BUFINII 0
1
Host Description 128-Byte Buffer Initialization Interrupt/End Flag Setting this bit by the buffer initialization command generates a BUFINII interrupt (LMCI). 0: Buffer initialization command wait Buffer initialization end [Clearing condition] When writing 0 after reading BUFINII = 1 1: Buffer initialization is in progress [Setting condition] When receiving by the buffer initialization command (BUFINIIE = 1 or BUFFINIE = 1 and HDININE = 0)
R/(W)* R
4
USERI
0
R/(W)*1 R
User Command Interrupt Flag Setting this bit by the user command generates an USERI interrupt. 0: User command wait User command processing end [Clearing condition] When writing 0 after reading USERI = 1 1: User command processing is in progress [Setting condition] When receiving by the user command
3
FLPERR
0
R/(W)* R
2
Flash Memory Programming Error 0: Flash memory has been completed programming [Clearing condition] Clearing by the clear status command 1: Flash memory programming error has been occurred.
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Section 18 LPC Interface (LPC)
R/W Bit 2 Bit Name Initial Value Slave FLEERR 0
2
Host Description Flash Memory Erasing Error 0: Flash memory has been completed erasure [Clearing condition] Clearing by the clear status command 1: Flash memory erasing error has been occurred
R/(W)* R
1, 0
All 0
R
R
Reserved These bits are read as 0 and cannot be modified.
Notes: 1. Only 0 can be written to clear the flag. 2. Only 1 can be written to set the flag.
* LMCST2
R/W Bit 7 Bit Name Initial Value Slave Host Description R R Indicates protect information in an LPC/FW memory cycle. [Updating conditions] * * * Data read command (flash memory/on-chip RAM) FLWAR set command Data write command (flash memory) (except for the case where an receive address does not match the FLWAR) Data write command (on-chip RAM)
PROTECT 0
*
0: Not protected 1: Protected 6 LMCBUSY 0 R R Indicates whether the on-chip RAM or RAM buffer is being written. 0: Wait for write access has been completed or write access has already been completed 1: Write access is in progress
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Section 18 LPC Interface (LPC)
R/W Bit 5 Bit Name ERASEE Initial Value Slave Host Description 0 R R Enables/disables the block erasure command 0: Disables the block erasure command [Clearing conditions] * * Clearing by the block erasure command Clearing by the clear status command
1: Enables the block erasure command [Setting condition] * 4 WRITEE 0 R R Setting by the erasing enable command Enables/disables the on-chip RAM data write command 0: Disables the on-chip RAM data write command [Clearing condition] * Clearing by the WRITEE clear command 1: Enables the on-chip RAM data write command [Setting condition] * 3 BUFTRAN 0 R R Setting by the write enable command Indicates the transfer state of the 128-byte buffer. 0: 128-byte buffer transfer has been completed [Clearing conditions] * * Clearing by the flash memory programming command Clearing by the BUFTRAN clear command
1: 128-byte buffer transfer is in progress [Setting condition] * 2 to 0 All 0 R R Setting by the FLWAR set command when BUFTRAN = 0
Reserved These bits are read as 0 and cannot be modified.
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Section 18 LPC Interface (LPC)
18.3.19 LMC Control Registers 1 and 2 (LMCCR1 and LMCCR2) LMCCR1 enables/disables the LMC host interface function. LMCCR2 enables/disables interrupts requested from the host by the interrupt commands and selects wait-state type. * LMCCR1
R/W Bit 7 Bit Name Initial Value Slave Host Description LMCE 0 R/W LPC/FW Memory Cycle Enable Enables/disables the LPC/FW memory cycles (LPC memory cycle and FW memory cycle). 0: LPC/FW memory cycles are disabled 1: LPC/FW memory cycles are enabled 6 LPCME 0 R/W LPC Memory Cycle Enable Enables/disables the LPC memory read/write interface function. When enabled, data transfer between the slave (this LSI) and host is performed via the LAD3 to LAD0, LFRAME, LRESET, and LCLK pins. 0: LPC memory cycles are disabled 1: LPC memory cycles are enabled 5 FWME 0 R/W Firmware Memory Cycle Enable Enables/disables the FW memory read/write interface function. When enabled, data transfer between the slave (this LSI) and host is performed via the LAD3 to LAD0, LFRAME, LRESET, and LCLK pins. 0: FW memory cycles are disabled 1: FW memory cycles are enabled 4 0 R/W Reserved This bit cannot be modified.
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Section 18 LPC Interface (LPC)
R/W Bit 3 Bit Name Initial Value Slave Host Description FLASHE 0 R/W Flash Memory Programming/Erasing Enable Enables/disables to program/erase the flash memory by the LPC/FW memory cycle. Programming/erasing the flash memory is controlled in combination with the FLPIE and FLEIE bits by the flash memory programming/erasing command. 0: Disables to program/erase the flash memory 1: Enables to program/erase the flash memory 2 HDINIE 0 R/W RAM Buffer Initialization Enable Enables/disables the function which automatically initializes the 128-byte transfer buffer contents to H'FF. This bit is valid when the BUFINIIE bit is cleared to 0. 0: Disables to initialize RAM buffer automatically 1: Enables to initialize RAM buffer automatically 1, 0 All 0 R/W Reserved These bits are read as 0 and cannot be modified.
* LMCCR2
R/W Bit 7 Bit Name Initial Value Slave Host Description FLPIE* 0 R/W Flash Memory Programming Interrupt Enable (LMCI) 0: Disables the flash memory programming command receive complete interrupt 1: Enables the flash memory programming command receive complete interrupt 6 FLEIE* 0 R/W Flash Memory Erasing Interrupt Enable (LMCI) 0: Disables the flash memory erasing command receive complete interrupt 1: Enables the flash memory erasing command receive complete interrupt
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Section 18 LPC Interface (LPC)
R/W Bit 5 Bit Name Initial Value Slave Host Description BUFINIIE 0 R/W RAM Buffer Initialization Interrupt Enable (LMCI) 0: Disables the RAM buffer initialization command receive complete interrupt 1: Enables the RAM buffer initialization command receive complete interrupt 4 USERIE 0 R/W User Command Interrupt Enable (LMCUI) 0: Disables the user command receive complete interrupt 1: Enables the user command receive complete interrupt 3 WAITSEL 0 R/W Wait Select Bit Selects the wait-state type in an LPC/FW memory cycle. 0: Short wait (4b'0101) 1: Long wait (4b'0110) 2 to 0 Note: * All 0 R/W Reserved These bits are read as 0 and cannot be modified. The FLPIE and FLEIE bits are valid when the FLASHE bit is set to 1.
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Section 18 LPC Interface (LPC)
18.3.20 Host Base Address Registers 1H and 1L (HBAR1H and HBAR1L) HBAR1 stores the upper 16 bits of a host start address when a host address is translated into a flash memory address. The inverted signal level of pin LID3 is reflected in the MSB of HBAR1. The lower 16 bits of the host start address are fixed H'0000. The host address space to be translated is decided in combination with bits AS13 to AS10 in ASSR which select the size of the host address space. When the FW memory cycle is used, bits 7 to 4 in HBAR1H (HB1A31 to HB1A28) are used as IDSEL. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1). * HBAR1H
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description HB1A31 HB1A30 HB1A29 HB1A28 HB1A27 HB1A26 HB1A25 HB1A24 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W Host Base Address Bits 31 to 24 Store the host base address 31 to 24. Bit HB1A31 reflects the inverted signal level of pin LID3.
* HBAR1L
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description HB1A23 HB1A22 HB1A22 HB1A20 HB1A19 HB1A18 HB1A17 HB1A16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Host Base Address Bits 23 to 16 Store the host base address 23 to 16.
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Section 18 LPC Interface (LPC)
18.3.21 Host Base Address Registers 2H and 2L (HBAR2H and HBAR2L) HBAR2 stores the upper 16 bits of a host start address when a host address is translated into a flash memory address. The lower 16 bits of the host start address are fixed H'0000. The host address space to be translated is decided in combination with bits AS23 to AS20 in ASSR which select the size of the host address space. When the FW memory cycle is used, bits 7 to 4 in HBAR2H (HB2A31 to HB2A28) are used as IDSEL. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1). * HBAR2H
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description HB2A31 HB2A30 HB2A29 HB2A28 HB2A27 HB2A26 HB2A25 HB2A24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Host Base Address Bits 31 to 24 Store the host base address 31 to 24.
* HBAR2L
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description HB2A23 HB2A22 HB2A22 HB2A20 HB2A19 HB2A18 HB2A17 HB2A16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Host Base Address Bits 23 to 16 Store the host base address 23 to 16.
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Section 18 LPC Interface (LPC)
18.3.22 On-Chip RAM Host Base Address Registers H and L (RAMBARH and RAMBARL) RAMBAR stores the upper 16 bits of the host start address when a host address is translated into an on-chip RAM address. The lower 16 bits of the host start address are fixed H'0000. The host address space to be translated is decided in combination with the RAMASSR contents which select the size of the host address space. When the FW memory cycle is used, bits 7 to 4 in RABAHR (MRA31 to MRA28) are used as IDSEL. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1). The host address space of which lower 16 bits are H'FFF0 to H'FFFF is used as command space. * RAMBARH
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description MRA31 MRA30 MRA29 MRA28 MRA27 MRA26 MRA25 MRA24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W On-Chip RAM Host Base Address Bits 31 to 24 Store the host base address 31 to 24.
* RAMBARL
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description MRA23 MRA22 MRA22 MRA20 MRA19 MRA18 MRA17 RA16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W
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On-Chip RAM Host Base Address Bits 23 to 16 Store the host base address 23 to 16.
Section 18 LPC Interface (LPC)
18.3.23 Address Space Set Register (ASSR) ASSR selects the flash memory address space to be used by the host and slave. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
R/W Bit 7 6 5 4 Bit Name Initial Value Slave Host Description AS13 AS12 AS11 AS10 0 0 0 0 R/W R/W R/W R/W Select flash memory address space 1. AS13 AS12 AS11 AS10 0 0 0 0 0 0 0 0 3 2 1 0 AS23 AS22 AS21 AS20 0 0 0 0 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : 64 kbytes : 128 kbytes : 256 kbytes : 384 kbytes : 512 kbytes : 640 kbytes : 768 kbytes : 1 Mbyte
B'1000 to B'1111 must not be selected. Select flash memory address space 2. AS23 AS22 AS21 AS20 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : 64 kbytes : 128 kbytes : 256 kbytes : 384 kbytes : 512 kbytes : 640 kbytes : 768 kbytes : 1 Mbyte
B'1000 to B'1111 must not be selected.
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Section 18 LPC Interface (LPC)
18.3.24 On-Chip RAM Address Space Set Register (RAMASSR) RAMASSR selects the on-chip RAM address space to be used by the host and slave. The bits 7 to 5 do not affect operations. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Initial Bit Name Value 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W On-Chip RAM Address Space Selection Select the on-chip RAM address space to be used by the host. RAM RAM RAM RAM RAM AS4 0 0 0 0 0 1 AS3 0 0 0 0 0 1 AS2 0 0 0 0 1 : 1 1 1 : 8 kbytes - 256 bytes RAM address space = 256 bytes x RAMAS AS1 0 0 1 1 0 AS0 0 1 0 1 0 : Setting prohibited : 256 bytes : 512 bytes : 768 bytes : 1 kbyte
Bit 7 6 5 4 3 2 1 0
RAMAS4 0 RAMAS3 0 RAMAS2 0 RAMAS1 0 RAMAS0 0
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Section 18 LPC Interface (LPC)
18.3.25 Slave Address Register 1 (SAR1) SAR1 selects the slave start address of the flash memory obtained by translating the host address in HBAR1. The bits 23 to 16 are selected by this register. The lower 16 bits are fixed H'0000. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Initial Bit Name Value SA1R23 SA1R22 SA1R21 SA1R20 SA1R19 SA1R18 SA1R17 SA1R16 0 0 0 0 0 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W Slave Address Bits 23 to 16 Select bits 23 to 16 of the flash memory address obtained by translating the host address. The value H'10 to H'FF should not be selected.
Bit 7 6 5 4 3 2 1 0
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Section 18 LPC Interface (LPC)
18.3.26 Slave Address Register 2 (SAR2) SAR2 selects the upper eight bits of slave start address of the flash memory obtained by translating the host address in HBAR2. The lower 16 bits are fixed H'0000. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Initial Bit Name Value SA2R23 SA2R22 SA2R21 SA2R20 SA2R19 SA2R18 SA2R17 SA2R16 0 0 0 0 0 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W Slave Address Bits 23 to 16 Select bits 23 to 16 of the flash memory address obtained by translating the host address. The value H'10 to H'FF should not be selected.
Bit 7 6 5 4 3 2 1 0
18.3.27 On-Chip RAM Slave Address Register (RAMAR) RAMAR selects the slave start address (bits 15 to 8) of the on-chip RAM obtained by translating the host address. Bits 23 to 16 are fixed H'FF and bits 7 to 0 are fixed H'00. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Initial Bit Name Value RMR15 RMR14 RMR13 RMR12 RMR11 RMR10 RMR9 RMR8 * 1 1 0 1 0 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W On-Chip RAM Slave Address Bits 15 to 8 Select bits 15 to 8 of the on-chip RAM address obtained by translating the host address. Though H'D0 to H'EF can be set, setting only H'D1 to H'EF is valid. Setting other than these values is invalid. When setting is invalid, the previous value is retained.
Bit 7 6 5 4 3 2 1 0 Note:
The value must be selected so that the area selected by RBUFAR is not overlapped. In this case, data in the on-chip RAM may be changed.
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Section 18 LPC Interface (LPC)
18.3.28 Flash Memory Write Protect Registers H, M, and L (FWPRH, FWPRM, and FWPRL) FWPR controls the protect blocks of the flash memory to be accessed in LPC/FW memory write cycles. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1). * FWPRH
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description WPB23 WPB22 WPB21 WPB20 WPB19 WPB18 WPB17 WPB16 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Set to/clear the write protect blocks of the flash memory. WPB23 H'0F0000 to H'0FFFFF WPB22 H'0E0000 to H'0EFFFF WPB21 H'0D0000 to H'0DFFFF WPB20 H'0C0000 to H'0CFFFF WPB19 H'0B0000 to H'0BFFFF WPB18 H'0A0000 to H'0AFFFF WPB17 H'090000 WPB16 H'080000 to H'09FFFF to H'08FFFF
0: Clears the write protect (0 can be written to only once.) 1: Sets to the write protect
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Section 18 LPC Interface (LPC)
* FWPRM
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description WPB15 WPB14 WPB13 WPB12 WPB11 WPB10 WPB9 WPB8 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Set to/clear the write protect blocks of the flash memory. WPB15 H'070000 WPB14 H'060000 WPB13 H'050000 WPB12 H'040000 WPB11 H'030000 WPB10 H'020000 WPB9 WPB8 H'010000 to H'07FFFF to H'06FFFF to H'05FFFF to H'04FFFF to H'03FFFF to H'02FFFF to H'01FFFF
H'00F000 to H'00FFFF
0: Clears the write protect (0 can be written to only once.) 1: Sets to the write protect
* FWPRL
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description WPB7 WPB6 WPB5 WPB4 WPB3 WPB2 WPB2 WPB0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Set to/clear the write protect blocks of the flash memory. WPB7 WPB6 WPB5 WPB4 WPB3 WPB2 WPB1 WPB0 H'00E000 H'00D000 H'00C000 H'004000 H'003000 H'002000 H'001000 H'000000 to H'00EFFF to H'00DFFF to H'00CFFF to H'00BFFF to H'003FFF to H'002FFF to H'001FFF to H'000FFF
0: Clears the write protect (0 can be written to only once.) 1: Sets to the write protect
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Section 18 LPC Interface (LPC)
18.3.29 Flash Memory Read Protect Registers H, M, and L (FRPRH, FRPRM, and FRPRL) FRPR controls the protect blocks of the flash memory to be accessed in LPC/FW memory read cycles. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1). * FRPRH
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description RPB23 RPB22 RPB21 RPB20 RPB19 RPB18 RPB17 RPB16 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Set to/clear the read protect blocks of the flash memory. RPB23 RPB22 RPB21 RPB20 RPB19 RPB18 RPB17 RPB16 H'0F0000 to H'0FFFFF H'0E0000 to H'0EFFFF H'0D0000 to H'0DFFFF H'0C0000 to H'0CFFFF H'0B0000 to H'0BFFFF H'0A0000 to H'0AFFFF H'090000 H'080000 to H'09FFFF to H'08FFFF
0: Clears to the read protect (0 can be written to only once.) 1: Sets the read protect
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Section 18 LPC Interface (LPC)
* FRPRM
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description RPB15 RPB14 RPB13 RPB12 RPB11 RPB10 RPB9 RPB8 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Set to/clear the read protect blocks of the flash memory. RPB15 RPB14 RPB13 RPB12 RPB11 RPB10 RPB9 RPB8 H'070000 H'060000 H'050000 H'040000 H'030000 H'020000 H'010000 to H'07FFFF to H'06FFFF to H'05FFFF to H'04FFFF to H'03FFFF to H'02FFFF to H'01FFFF
H'00F000 to H'00FFFF
0: Clears to the read protect (0 can be written to only once.) 1: Sets the read protect
* FRPRL
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description RPB7 RPB6 RPB5 RPB4 RPB3 RPB2 RPB2 RPB0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Set to/clear the read protect blocks of the flash memory. RPB7 RPB6 RPB5 RPB4 RPB3 RPB2 RPB1 RPB0 H'00E000 H'00D000 H'00C000 H'004000 H'003000 H'002000 H'001000 H'000000 to H'00EFFF to H'00DFFF to H'00CFFF to H'00BFFF to H'003FFF to H'002FFF to H'001FFF to H'000FFF
0: Clears to the read protect (0 can be written to only once.) 1: Sets the read protect
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Section 18 LPC Interface (LPC)
18.3.30 On-Chip RAM Protect Control Register (MPCR) MPCR controls the access to the on-chip RAM in LPC/FW memory RW cycles. The contents of this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
R/W Bit Bit Name Initial Value Slave Host Description All 0 0 R/W R/W Reserved On-Chip RAM Write Access Enable Enables/disables the access to the on-chip RAM in LPC/FW memory write cycles. 0: Access inhibited 1: Access enabled 0 RAMRE 0 R/W On-Chip RAM Read Access Enable Enables/disables the access to the on-chip RAM in LPC/FW memory read cycles. 0: Access inhibited 1: Access enabled 7 to 2 1 RAMWE
18.3.31 User Command Register (UCMDTR) UCMDTR stores the user command data on user command reception.
R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 0 0 R R R R R R R R W W W W W W W W User Command Data Writing operation with the user command
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Section 18 LPC Interface (LPC)
18.4
18.4.1
Operation
LPC interface Activation
The LPC interface is activated by setting one of the following bits to 1: LPC3E to LPC1E in HICR0, LPC4E in HICR4, or LMCCR1 in LMCE. When the LPC interface is activated, the related I/O ports (P37 to P30, P83 and P82) function as dedicated LPC interface input/output pins. In addition, setting the FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (P81, P80, PB0, and PB1) to the LPC interface's input/output pins. Use the following procedure to activate the LPC interface after a reset release. 1. Read the signal line status and confirm that the LPC module can be connected. Also check that the LPC module is initialized internally. 2. When using channel 4, set LADR4 to determine the I/O address 3. When using channel 3, set LADR3 to determine the I/O address and whether bidirectional data registers are to be used. Set the relevant registers when the LPC/FW memory cycle is used. 4. Set the enable bit (LPC4E to LPC1E, and LMCE) for the channel to be used. 5. Set the enable bits (FGA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be used. 6. Set the selection bits for other functions (SDWNE, IEDIR). 7. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF, FLPI, FLEI, BUFINI and USERI). Read IDR or TWR15 to clear IBF. 8. Set receive complete interrupt enable bits (IBFIE4 to IBFIE1, ERRIE, FLPIE, FLEIE, BUFINIE, and USERIE) as necessary. 18.4.2 LPC I/O Cycles
There are 12 types of LPC transfer cycle: LPC memory read, LPC memory write, I/O read, I/O write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O read, bus master I/O write, FW memory read, and FW memory write. Of these, the LPC of this LSI supports I/O read, I/O write, LPC memory read, LPC memory write, FW memory read, and FW memory write cycles. An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of the LPC transfer cycle has been requested.
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Section 18 LPC Interface (LPC)
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the following order, in synchronization with LCLK. The host can be made to wait by sending back a value other than B'0000 in the slave's synchronization return cycle, but with the LPC of this LSI a value of B'0000 always returns. If the received address matches the host address in an LPC register (IDR, ODR, STR, and TWR), the LPC interface enters the busy state; it returns to the idle state by output of a state count 12 turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle forced termination (abort), registers and flags are not changed. The timing of the LFRAME, LCLK, and LAD signals is shown in figures 18.2 and 18.3. Table 18.2 LPC I/O Cycle
I/O Read Cycle State Count 1 2 3 4 5 6 7 8 9 10 11 12 13 Contents Start Cycle type/direction Address 1 Address 2 Address 3 Address 4 Drive Source Host Host Host Host Host Host Value (3 to 0) 0000 0000 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 1111 ZZZZ 0000 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ Contents Start Cycle type/direction Address 1 Address 2 Address 3 Address 4 Data 1 Data 2 I/O Write Cycle Drive Source Host Host Host Host Host Host Host Host Value (3 to 0) 0000 0010 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ 0000 1111 ZZZZ
Turnaround (recovery) Host Turnaround Synchronization Data 1 Data 2 None Slave Slave Slave
Turnaround (recovery) Host Turnaround Synchronization None Slave
Turnaround (recovery) Slave Turnaround None
Turnaround (recovery) Slave Turnaround None
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Section 18 LPC Interface (LPC)
LCLK LFRAME
LAD3 to LAD0
Start Cycle type, direction, and size
ADDR
TAR
Sync
Data
TAR
Start
Number of clocks
1
1
4
2
1
2
2
1
Figure 18.2 Typical LFRAME Timing
LCLK LFRAME
LAD3 to LAD0
Start Cycle type, direction, and size
ADDR
TAR
Sync Slave must stop driving
Master will drive high
Too many Syncs cause timeout
Figure 18.3 Abort Mechanism
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Section 18 LPC Interface (LPC)
18.4.3
Gate A20
The Gate A20 signal can mask address A20 to emulate the address mode of the 8086* architecture CPU used in personal computers. Normally, the Gate A20 signal can be controlled by a firmware. The fast Gate A20 function that realizes high-seed performance by hardware is enabled by setting the FGA20E bit to 1 in HICR0. Note: An Intel microprocessor (1) Regular Gate A20 Operation
Output of the Gate A20 signal can be controlled by an H'D1 command and data. When the slave (this LSI) receives data, it normally reads IDR1 in the interrupt handling routine activated by the IBFI1 interrupt. At this time, firmware copies bit 1 of data following an H'D1 command and outputs it on pin GA20. (2) Fast Gate A20 Operation
The internal state of pin GA20 is initialized to 1 since the initial value of the FGA20E bit is 0. When the FGA20E bit is set to 1, pin P81/GA20 functions as the output of the fast GA20 signal. The state of pin GA20 can be monitored by reading bit GA20 in HICR2. The initial output from this pin is 1, which is the initial value. Afterward, the host can manipulate the output from this pin by sending commands and data. This function is only available via the IDR1. The LPC decodes commands input from the host. When an H'D1 host command is detected, bit 1 of the data following the host command is output from pin GA20. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 18.3 shows the conditions that set and clear pin GA20. Figure 18.4 shows the GA20 output flow. Table 18.4 indicates the GA20 output signal values. Table 18.3 GA20 (P81) Setting/Clearing Timing
Pin Name GA20 Setting Condition When bit 1 of the data that follows an H'D1 host command is 1 Clearing Condition When bit 1 of the data that follows an H'D1 host command is 0
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Section 18 LPC Interface (LPC)
Start
Host write
No
H'D1 command received? Yes Wait for next byte Host write
No
Data byte? Yes Write bit 1 of data byte to the bit of GA20 in DR
Figure 18.4 GA20 Output
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Section 18 LPC Interface (LPC)
Table 18.4 Fast Gate A20 Output Signals
Internal CPU Interrupt Flag (IBF) 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 GA20 (P81) Q 1 Q (1) Q 0 Q (0) Q 1 Q (1) Q 0 Q (0) Q Q Q Q Q 1/0 Q (1/0) Consecutively executed sequences Retriggered sequence Cancelled sequence Turn-off sequence (abbreviated form) Turn-on sequence (abbreviated form) Turn-off sequence
C/D1 Data/Command 1 0 1 1 0 1 1 0 1/0 1 0 1/0 1 1 1 1 1 0 1 H'D1 command 1 data*1 H'FF command H'D1 command 0 data*
2
Remarks Turn-on sequence
H'FF command H'D1 command 1 data*
1
Command other than H'FF and H'D1 H'D1 command 0 data*
2
Command other than H'FF and H'D1 H'D1 command Command other than H'D1 H'D1 command H'D1 command H'D1 command Any data H'D1 command
Notes: 1. Any data with bit 1 set to 1. 2. Any data with bit 1 cleared to 0.
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Section 18 LPC Interface (LPC)
18.4.4
LPC Interface Shutdown Function (LPCPD)
The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the LPC software shutdown state is controlled by the SDWNB bit. In both states, the LPC interface enters the reset state by itself, and is no longer affected by external signals other than the LRESET and LPCPD signals. Placing the slave in sleep mode or software standby mode is effective in reducing current dissipation in the shutdown state. If software standby mode is set, some means must be provided for exiting software standby mode before clearing the shutdown state with the LPCPD signal. If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown state cannot be cleared at the same time as the rising edge of the LPCPD signal. Taking these points into consideration, the following operating procedure uses a combination of LPC software shutdown and LPC hardware shutdown. 1. Clear the SDWNE bit to 0. 2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag. 3. When an ERRI interrupt is generated by the SDWN flag, check the LPC interface internal status flags and perform any necessary processing. 4. Set the SDWNB bit to 1 to set LPC software standby mode. 5. Set the SDWNE bit to 1 and make a transition to LPC hardware standby mode. The SDWNB bit is cleared automatically. 6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during steps 3 to 5. If the signal has risen, clear SDWNE to 0 to return to the state in step 1. 7. Place the slave in sleep mode or software standby mode after confirming the LMCE bit in LMCCR1 cleared to 0, as necessary. 8. If software standby mode has been set, exit software standby mode by some means independent of the LPC. 9. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared to 0. If the slave has been placed in sleep mode, the mode is exited by means of LRESET signal input, on completion of the LPC transfer cycle, or by some other means.
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Section 18 LPC Interface (LPC)
Table 18.5 shows the scope of the LPC interface pin shutdown. Table 18.5 Scope of LPC Interface Pin Shutdown
Abbreviation LAD3 to LAD0 LFRAME LRESET LCLK SERIRQ LSCI LSMI PME GA20 CLKRUN LPCPD Port P33 to P30 P34 P35 P36 P37 PB1 PB0 P80 P81 P82 P83 Scope of Shutdown O O X O O O X I/O I/O Input Input Input I/O I/O I/O I/O I/O Input Input Notes Hi-Z Hi-Z LPC hardware reset function is active Hi-Z Hi-Z Hi-Z, only when LSCIE = 1 Hi-Z, only when LSMIE = 1 Hi-Z, only when PMEE = 1 Hi-Z, only when FGA20E = 1 Hi-Z Needed to clear shutdown state
[Legend] O: Pin that is shutdown by the shutdown function : Pin that is shutdown only when the LPC function is selected by register setting X: Pin that is not shutdown
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order of priority of LPC shutdown and reset states is as follows. 1. System reset (reset by STBY or RES pin input, or WDT0 overflow) All register bits, including bits LPC4E to LPC1E, are initialized. 2. LPC hardware reset (reset by LRESET pin input) LRSTB, SDWNE, and SDWNB bits are cleared to 0. 3. LPC software reset (reset by LRSTB) SDWNE and SDWNB bits are cleared to 0. 4. LPC hardware shutdown SDWNB bit is cleared to 0. 5. LPC software shutdown The scope of the initialization in each mode is shown in table 18.6.
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Section 18 LPC Interface (LPC)
Table 18.6 Scope of Initialization in Each LPC interface Mode
Items Initialized LPC transfer cycle sequencer (internal state), LPCBSY and ABRT flags SERIRQ transfer cycle sequencer (internal state), CLKREQ and IRQBSY flags System Reset Initialized Initialized LPC Reset Initialized Initialized Initialized LPC Shutdown Initialized Initialized Retained
LPC interface flags Initialized (IBF1, IBF2, IBF3A, IBF3B, IBF4, MWMF, C/D1, C/D2, C/D3, C/D4, OBF1, OBF2, OBF3A, OBF3B, OBF4, SWMF, DBU), GA20 (internal state) Host interrupt enable bits Initialized (IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3, SELREQ, SMIE4, IRQ6E4, IRQ9E4 to IRQ11E4, IEDIR2 to IEDIR4), Q/C flag LRST flag SDWN flag LRSTB bit SDWNB bit SDWNE bit
Initialized
Retained
Initialized (0) Can be set/cleared
Can be set/cleared
Initialized (0) Initialized (0) Can be set/cleared Initialized (0) HR: 0 SR: 1 0 (can be set)
Initialized (0) Initialized (0) HS: 0 SS: 1 Initialized (0) Initialized (0) HS: 1 SS: 0 or 1 Retained Retained
Initialized LPC interface operation control bits (LPC4E to LPC1E, FGA20E, LADR4 to LADR1, IBFIE1 to IBFIE4, PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB, TWRE, SELSTR3, SELIRQ1, SELSMI, SELIRQ6, SELIRQ9 to SELIRQ12, HBAR1, HBAR2, RAMBAR, SAR1, SAR2, RAMAR, ASSR, RAMASSR, FWPRH, FWPRM, FWPRL, FRPRH, FRPRM, FRPRL, FLPI, FLEI, BUFINII, USERI, FLPERR, FLEERR, PROTECT, LMCBUSY, LMCE, LPCME, FWE, FLASHE, HDINIE, FLPIE, FLEIE, BUFINIIE, USERIE, WAITSEL, MPCR, RBUFAR, FLWARH, FLWARL, LMCMIDCR, LMCDIDCR, EBLKR, UCMDTR) LPC interface operation control bits ERASEE, WRITEE, RUFTRAN Initialized
Initialized
Retained
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Section 18 LPC Interface (LPC)
Items Initialized LRESET signal LPCPD signal LAD3 to LAD0, LFRAME, LCLK, SERIRQ, CLKRUN signals PME, LSMI, LSCI, GA20 signals (when function is selected) PME, LSMI, LSCI, GA20 signals (when function is not selected)
System Reset Input (port function
LPC Reset Input Input Input Output
LPC Shutdown Input Input Hi-Z Hi-Z
Port function Port function
Note: System reset: Reset by STBY input, RES input, or WDT overflow LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR) LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS)
Figure 18.5 shows the timing of the LPCPD and LRESET signals.
LCLK LPCPD LAD3 to LAD0 LFRAME
At least 30 s
At least 100 s At least 60 s
LRESET
Figure 18.5 Power-Down State Termination Timing
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Section 18 LPC Interface (LPC)
18.4.5
LPC Interface Serialized Interrupt Operation (SERIRQ)
A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 18.6.
SL or H LCLK SERIRQ Drive source IRQ1
Start frame H R T
IRQ0 frame S R T
IRQ1 frame S R T
IRQ2 frame S R T
START Host controller None IRQ1 None
H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample
IRQ14 frame S LCLK SERIRQ Driver None R T
IRQ15 frame S R T
IOCHCK frame S R T I
Stop frame H R T
Next cycle
STOP IRQ15 None Host controller
START
H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle
Figure 18.6 SERIRQ Timing The serialized interrupt transfer cycle frame configuration is as follows. Two of the states comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The recover state must be driven by the host or slave that was driving the preceding state.
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Section 18 LPC Interface (LPC)
Table 18.7 Serialized Interrupt Transfer Cycle Frame Configuration
Serial Interrupt Transfer Cycle Frame Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Contents Start IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK Stop Drive Source Slave Host Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Host Number of States 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Undefined First, 1 or more idle states, then 2 or 3 states 0-driven by host 2 states: Quiet mode next 3 states: Continuous mode next Drive possible in LPC channels 2, 3, and 4 Drive possible in LPC channels 2, 3, and 4 Drive possible in LPC channels 2, 3, and 4 Drive possible in LPC channel 1 Drive possible in LPC channels 2, 3, and 4 Drive possible in LPC channel 1 Drive possible in LPC channels 2, 3, and 4 Notes In quiet mode only, slave drive possible in first state, then next 3 states 0-driven by host
There are two modescontinuous mode and quiet modefor serialized interrupts. The mode initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer cycle that ended before that cycle. In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet mode, the slave with interrupt sources requiring a request can also initiate an interrupt transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the power-down state.
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Section 18 LPC Interface (LPC)
In order for a slave to transfer an interrupt request in this case, a request to restart the clock must first be issued to the host. For details see section 18.4.6, LPC Interface Clock Start Request. 18.4.6 LPC Interface Clock Start Request
A request to restart the clock (LCLK) can be sent to the host by means of the CLKRUN pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host interrupt request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is sent to the host. The timing for this operation is shown in figure 18.7.
CLK 1 CLKRUN 2 3 4 5 6
Pull-up enable Drive by the slave processor
Drive by the host processor
Figure 18.7 Clock Start Request Timing Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a different protocol, using the PME signal, etc. 18.4.7 LPC/FW Memory Cycle
In LPC/FW memory read or LPC/FW memory write cycles, data is transferred via pins LAD3 to LAD0 in the following order, in synchronization with the LCLK. The slave can report an error to the host by sending back a value of B'1010 in the synchronization return cycle of the slave. The LPC of this LSI however a value of B'0000 (ready), B'0101 (short wait), or B'0110(long wait) always returns. If the received address matches an address of the area the host can access (the area selected by the LPC registers: HBAR1, HBAR2, ASSR, RAMBAR, and RAMASSR), the LPC interface enters the busy state; it returns to the idle state by a turnaround output by the slave. Register and flag changes are made at this timing, so in the event of a transfer cycle forced termination (abort), registers and flags are not changed. An on-chip memory, however, is read after receiving an
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Section 18 LPC Interface (LPC)
address, or an on-chip memory is written after receiving an address and data. So, if a transfer cycle forced termination (abort) after receiving an address and data, an on-chip memory may be accessed. Table 18.8 LPC Memory Cycle
LPC Memory Read Cycle State Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Contents Start Cycle type/direction Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Address 8 Drive Source Host Host Host Host Host Host Host Host Host Host Value (3 to 0) 0000 0000 Bits 31 to 28 Bits 27 to 24 Bits 23 to 20 Bits 19 to 16 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 1111 ZZZZ 0101/0110 0000 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ Contents Start Cycle type/direction Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Address 8 Data 1 Data 2 LPC Memory Write Cycle Drive Source Host Host Host Host Host Host Host Host Host Host Host Host Value (3 to 0) 0000 0010 Bits 31 to 28 Bits 27 to 24 Bits 23 to 20 Bits 19 to 16 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ 0000 1111 ZZZZ
Turnaround (recovery) Host Turnaround Wait* Synchronization Data 1 Data 2 None Slave Slave Slave Slave
Turnaround (recovery) Host Turnaround Synchronization None Slave
Turnaround (recovery) Slave Turnaround None
Turnaround (recovery) Slave Turnaround None
Note:
*
The number of wait states differs depending on the length of the time to turn the bus control over and the system clock frequency.
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Section 18 LPC Interface (LPC)
Table 18.9 FW Memory Cycle (Byte Transfer)
FW Memory Read Cycle State Count 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Contents Start Device selection Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Size Drive Source Host Host Host Host Host Host Host Host Host Host Value (3 to 0) 1101 ID3 to ID0 Bits 27 to 24 Bits 23 to 20 Bits 19 to 16 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 0000 1111 ZZZZ 0101/0110 0000 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ Contents Start Device selection Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Size Data 1 Data 2 FW Memory Write Cycle Drive Source Host Host Host Host Host Host Host Host Host Host Host Host Value (3 to 0) 1110 ID3 to ID0 Bits 27 to 24 Bits 23 to 20 Bits 19 to 16 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 0000 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ 0000 1111 ZZZZ
Turnaround (recovery) Host Turnaround Wait* Synchronization Data 1 Data 2 None Slave Slave Slave Slave
Turnaround (recovery) Host Turnaround Synchronization None Slave
Turnaround (recovery) Slave Turnaround None
Turnaround (recovery) Slave Turnaround None
Note:
*
The number of wait states differs depending on the length of the time to turn the bus control over and the system clock frequency.
The LPC supports byte, word, and longword transfer of the FW memory read and write cycle. When transferring in words, the LSB is fixed B'0 and when transferring longwords, the lower two bits are fixed B'00.
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Section 18 LPC Interface (LPC)
18.4.8
LPC/FW Memory Access Command
An LPC/FW memory cycle with a special address can be used as a command. It allows to control flash memory erasure, programming and to read the status register of the flash memory. The host address space of which lower 16 bits are H'FFF0 to H'FFFF can be used as command space according to the RAMBAR setting. Figure 18.8 shows an example of command space setting.
RAMBAR: H1'000 RAMASSR: H'00 (8kbytes) H'10000000 On-chip RAM space H'10001FFF H'1000FFF0 Command space H'1000FFFF CMDF (H'1000FFFF) Host address Note: CMD: Command address CMD0 (H'1000FFF0) CMD1 (H'1000FFF1)
Figure 18.8 Example of Command Space Setting
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Section 18 LPC Interface (LPC)
Table 18.10 lists the LPC/FW memory access commands. Table 18.10 List of LPC/FW Memory Access Commands
Command Data read ID read Status read Clear status Erasing enable Block erasure Write enable Data write (on-chip RAM) WRITEE clear FLWAR set Data write (flash memory) Operation R R R W W W W W W W W Address FL/RM CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 RM CMD8 FL FL CMD9 CMDA CMDB CMDC Size B/W/L B/W B/W B B B B B/W/L B B B/W/L B B B B Data Read data MID DID ST1 ST2 Block number Write data H'80 Write data Wait State O X X X X X X X X X X X X X X Memory Access Interrupt O X X X X X X O X X O X X X/O* X X X X X X O X X X X X O X O/X* O
Flash memory programming W BUFTRAN clear Buffer initialization User command W W W
[Legend] O: Available X: Not available FL: Flash memory address MID/DID: ID codes (LMCMIDCR/LMCDIDCR) RM: On-chip RAM address ST1/2: LMCST (LMCST1/LMCST2) CMDx: Command address Block number: Erase block number : Any data Note: * The HDINIE and BUFINIIE bits select whether or not memory is accessed and whether or not an interrupt is generated with the buffer initialization command.
1. Data read command When receiving an FL/RM address in an LPC/FW memory read cycle, the LPC sends back data of the address in the memory. Byte, word, and longword transfers are supported in FW memory read cycles.
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Section 18 LPC Interface (LPC)
2. ID read command When receiving the CMD0 or CMD1 address in an LPC/FW memory read cycle, the LPC sends back an MID/DID. Byte and word transfers are supported by the ID read command. In word transfer, an MID is sent back before a DID. In longword transfer, the SYNC field is not sent back. 3. Status read command When receiving the CMD2 or CMD3 address in an LPC/FW memory read cycle, the slave sends back an LMCST1/LMCST2. Byte and word transfers are supported by the status read command. In word transfer, an LMCST1 is sent back before an LMCST2. In longword transfer, the SYNC field is not sent back. 4. Clear Status command When receiving the CMD4 address in an LPC/FW memory write cycle, the slave clears the FLPERR, FLEERR, and ERASEE bits. 5. Erasing enable command When receiving the CMD5 address in an LPC/FW memory write cycle, the slave sets the ERASEE bit. Setting the ERASEE bit allows to receive the block erasure command. 6. Block erasure command When receiving the CMD6 address and a block number data with ERASEE = 1 in an LPC/FW memory write cycle, the LPC performs a block erasure. The LPC stores the erase block number in EBLKR, sets the FLEI interrupt flag (one of the LMCI interrupt sources) and clears the ERASEE bit when receiving the block erasure command. The LPC must clear the FLEI flag to 0 after reading FLEI = 1. The host reads LMCST1, waiting for the FLEI bit cleared. After reading FLEI = 0 and checking the FLERR bit, the host starts the next command. During block erasure, the commands for a memory access or an interrupt generation are prohibited. 7. Write enable command When receiving the CMD7 address in an LPC/FW memory write cycle, the LPC sets the WRITEE bit. Setting the WRITEE bit allows to receive the data write (on-chip RAM) command. 8. Data write (on-chip RAM) command When receiving an RM address and the data write command with WRITEE = 1 in an LPC/FW memory write cycle, the LPC writes data of the address in the on-chip RAM. Byte, word, and longword transfers are supported in FW memory write cycles. Since receiving the data write command to the on-chip RAM generates a memory access, confirm the LMCBUSY bit cleared to 0 after completion of an LPC/FW memory write cycle. It is needed to decide the internal memory access status since a wait state is not inserted in a write cycle. When the LMCBUSY is set, the commands for a memory access or an interrupt generation are prohibited. The WRITEE bit is not cleared after the data write command is completed. To clear the WRITEE bit, the WRITEE clear command must be executed.
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Section 18 LPC Interface (LPC)
9. WRITEE clear command When receiving the CMD8 address in an LPC/FW memory write cycle, the LPC clears the WRITEE bit. Clearing the WRITEE bit avoids unintentional write accesses to the on-chip RAM. 10. FLWAR set command When receiving an FL address and the data of H'80 in an LPC/FW memory write cycle, the LPC stores the FL address in FLWAR and set the BUFTRAN bit to 1 for the data write command (flash memory). The BUFTRAN bit must be cleared to 0 to set data in FLWAR. If the data of H'80 is written to the FL address, the data write command (flash memory) is executed. The BUFTRAN bit must be cleared to 0 to set data in FLWAR. Bits 4 to 0 in FLWARH store bits 19 to 15 of the transfer address and bits 7 to 0 in FLWARL store the bits 14 to 7 of the transfer address. Bits 7 to 5 in FLWARH are fixed B'000. 11. Data write (flash memory) When receiving an address which matches the FLWAR contents and data to be written to with the BUFTRAN bit set to 1 in an LPC/FW memory write cycle, the LPC stores the data to be written to the address selected by the RBUFAR contents. Byte, word, and longword transfers are supported in FW memory write cycles. Since receiving the data write command to the flash memory generates a memory access, confirm the LMCBUSY bit cleared to 0 after completion of an LPC/FW memory write cycle. It is needed to decide the internal memory access status since a wait state is not inserted in a write cycle. When the LMCBUSY is set, the commands for an interrupt generation are prohibited. The BUFTRAN bit is not cleared after the data write command is completed. To clear the BUFTRAN bit, the BUFTRAN clear command must be executed. The addresses are compared between bits 7 to 0 in FLWARH and bits 22 to 15 of the transfer address, or between bits 7 to 0 in FLWARH and bits 14 to 7 of the transfer address. The lower six bits are not compared and are used as a buffer address without any change. 12. Flash Programming memory When receiving the CMD9 address with the BUFTRAN set to 1 in an LPC/FW memory write cycle, the LPC programs the flash memory. When receiving the flash memory programming command, the LPC set the FLPI interrupt flag (one of the LMCI interrupt sources) and clears the BUFTRAN bit at the same time. The slave must clear the FLPI bit to 0 after reading FLPI = 1 on completion of programming the flash memory. The host reads LMCST1, waiting for the FLPI bit cleared. After reading FLPI = 0 and checking the FLPERR bit, the host starts the next command. During programming, the commands for a memory access or an interrupt generation are prohibited. 13. BUFTRAN clear When receiving the CMDA address in an LPC/FW memory write cycle, the LPC clears the BUFTRAN bit. FLWAR can store another data after clearing the BUFTRAN bit.
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Section 18 LPC Interface (LPC)
14. Buffer initialization command When receiving the CMDB address in an LPC/FW memory write cycle, the LPC initializes the buffer. When BUFINIIE = 1, or BUFINIIE = 0 and HDINIE = 0, the LPC sets the BUFINII interrupt flag (one of the LMCI interrupt sources) to 1 on reception of the buffer initialization command. The slave must clear the BUFINIIE bit to 0 after reading BUFINII = 1 on completion of the buffer initialization. The host reads LMCST1, waiting for the BUFINIIE bit cleared. During initialization, the commands for a memory access or an interrupt generation are prohibited. When BUFINIIE = 0 and HDINIE = 1, the LPC initializes the buffer. In this case, the buffer contents of 128 bytes are initialized to H'FF by generation of memory cycles. To decide whether or not to complete the initialization, check the LMCBUSY bit. During LMCBUSY = 1, the commands for a memory access or an interrupt generation are prohibited. 15. User command When receiving the CMDC address in an LPC/FW memory write cycle, the LPC executes the user command. When receiving the user command, the LPC sets the USERI interrupt flag. The slave must clear the USERI bit to 0 after reading USERI = 1. The host reads LMCST1, waiting for the USERI bit cleared. During execution, the commands for an interrupt generation are prohibited.
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Section 18 LPC Interface (LPC)
Table 18.11 lists the factors that prevent the SYNC from being sent back in an LPC/FW memory read cycle. Table 18.11 List of Factors that Prevents SYNC Field being Sent Back
Command Factor Remarks
Common to all Start not match commands Device selection not match Address not match Size error Data read In FW memory access cycle (other than byte, word, longword) In FW memory access cycle
Reading address which has already been According to the FRPR/RAMRE register accessed disabled settings Accessing on-chip memory is in progress LMCBUSY = 1 Interrupt processing is in progress While following processes are in progress: * * * * Programming flash memory (FLPI = 1) Erasing flash memory (FLEI = 1) Initializing buffer (BUFINII = 1) Processing user command (USERI = 1)
Block erasure Erasure command disabled Erasure protect blocks Erase block number error On-chip memory access is in progress Interrupt processing is in progress
ERASEE = 0 According to the FWPR register setting Other than 0 to 23 LMCBUSY = 1 While following processes are in progress: * * * * Programming flash memory (FLPI = 1) Erasing flash memory (FLEI = 1) Initializing buffer (BUFINII = 1) Processing user command (USERI = 1)
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Section 18 LPC Interface (LPC)
Command
Factor
Remarks WRITEE = 0 RAMWE = 0 LMCBUSY = 1 While following processes are in progress: * * * * Programming flash memory (FLPI = 1) Erasing flash memory (FLEI = 1) Initializing buffer (BUFINII = 1) Processing user command (USERI = 1)
Data write On-chip RAM data write command (on-chip RAM) disabled On-chip RAM write access disabled O-chip memory access is in progress Interrupt processing is in progress
FLWAR set
Flash memory write protect Data error On-chip memory access is in progress Interrupt processing is in progress
According to the FWPR register Other than H'80 LMCBUSY = 1 While following processes are in progress: * * * * Programming flash memory (FLPI = 1) Erasing flash memory (FLEI = 1) Initializing buffer (BUFINII = 1) Processing user command (USERI = 1)
Data write Flash memory write protect (flash memory) Address not match FLWAR (128 bytes) On-chip memory access is in progress Interrupt processing is in progress
According to the FWPR register 128 bytes LMCBUSY = 1 While following processes are in progress: * * * * Programming flash memory (FLPI = 1) Erasing flash memory (FLEI = 1) Initializing buffer (BUFINII = 1) Processing user command (USERI = 1)
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Section 18 LPC Interface (LPC)
Command
Factor
Remarks BUFTRAN = 0 LMCBUSY = 1 While following processes are in progress: * * * * Programming flash memory (FLPI = 1) Erasing flash memory (FLEI = 1) Initializing buffer (BUFINII = 1) Processing user command (USERI = 1)
Flash memory FLWAR setting command not issued programming On-chip memory access is in progress Interrupt processing is in progress
Buffer initialization
On-chip memory access is in progress Interrupt processing is in progress
LMCBUSY = 1 While following processes are in progress: * * * * Programming flash memory (FLPI = 1) Erasing flash memory (FLEI = 1) Initializing buffer (BUFINII = 1) Processing user command (USERI = 1)
User command
On-chip memory access is in progress Interrupt processing is in progress
LMCBUSY = 1 While following processes are in progress: * * * Programming flash memory (FLPI = 1) Erasing flash memory (FLEI = 1) Initializing buffer (BUFINII = 1)
Processing user command (USERI = 1)
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Section 18 LPC Interface (LPC)
18.4.9
Flash Memory Address Translation (Host Slave)
A host address is translated into a flash memory address by the settings of HBAR1, HBAR2, ASSR, SAR1, and SAR2. The slave address which exceeds H'0FFFFF must not be specified. The host addresses within the range of H'00000000 to H'FFFFFFFF are available for translation and the flash memory addresses within the range of H'000000 to H'0FFFFF are available. Figure 18.9 shows an example of the flash memory address translation.
HBAR1: H'000E, HBAR2: H'FFE, SAR1: H'05, SAR2: H'07, ASSR: H'14 (128 k, 512k), Host address 1: H'000FFFF0 Host address 2: H'FFE00000
H'000E0000 128 kbytes H'000FFFFF H'050000 128 kbytes H'06FFFF H'070000 On-chip ROM 512 kbytes H'FFE00000 512 kbytes H'FFE7FFFF Host address H'0EFFFF
H'0FFFFF Slave address
Figure 18.9 Example of Flash Memory Address Translation The host address space is specified by the settings of HBAR1, HBAR2, and ASSR as shown in figure 18.9. The host must use addresses within this range. Addresses which are not within this range will cause an address exception and any memory access is not performed. The slave address space is specified by the settings of SAR1, SAR2, and ASSR as shown in figure 18.9. The host and slave address spaces are specified by the settings of HBAR1, bits 7 to 4 in ASSR, and SAR1, or HBAR2, bits 3 to 0 in ASSR, and SAR2. Each of those two areas must be specified so that they are not overlapped. If two areas are overlapped, address space 1 has priority. The host address of H'000FFF0 is translated shown below.
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Section 18 LPC Interface (LPC)
1. Host address - HBAR1 = H'000FFFF0 - H'000E0000 = H'0001FFF0 2. H'0001FFF0 + SAR1 = H'0001FFF0 + H'050000 = H'06FFF0 (slave address) 18.4.10 On-Chip RAM Address Translation (Host Slave) A host address is translated into an on-chip RAM address by the settings of RAMBAR, RAMSSR, and RAMAR. The slave address which exceeds H'FFEFFF must not be specified. The host addresses within the range of H'00000000 to H'FFFFFFFF are available for translation and the on-chip RAM addresses within the range of H'FFD100 to H'FFEFFF are available. Figure 18.10 shows an example of the on-chip RAM address translation.
RAMBAR: H1'000 RAMASSR: H'FF (8 kbytes to 256 bytes) RAMAR: H'D1 Host address: H'10000100
H'10000000 H'10001EFF
8 kbytes to 256 bytes Host address
H'FFD100 On-chip RAM H'FFEFFF Slave address
Figure 18.10 Example of On-Chip RAM Address Translation The host address space is specified by the settings of RAMBAR and RAMASSR as shown in figure 18.10. The host must use addresses within this range. An access to the addresses which are not within this range will cause an address exception and any memory access is not performed. The slave address space is specified by the settings of RAMAR and RAMASSR as shown in figure 18.10. The host address of H'10000100 is translated shown below. 1. Host address - RAMBAR = H'10000100 - H'10000000 = H'00000100 2. H'0000100 + RAMAR = H'00000100 + H'FFD100 = H'FFD200 (slave address)
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Section 18 LPC Interface (LPC)
18.4.11 Address Space Priority The host addresses can be specified from H'00000000 to H'FFFF0000 by the settings of HBAR1, HBAR2, and RAMBAR. The host address spaces, however, may be overlapped depending on the ASSR setting. Moreover, the slave address spaces may be overlapped depending on the settings of SAR1, SAR2, and ASSR. For this, individual address spaces are given priority. The priority is as follows: Command space > address space 1 > on-chip RAM space > address space 2 Notes: 1. Please keep in mind that the slave on-chip RAM space may be overlapped with the RBUFAR space. 2. Only the flash memory can be accessed in address spaces 1 and 2.
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Section 18 LPC Interface (LPC)
18.4.12 Example 1 of Address Space Priority Figure 18.11 shows an example of an address translation when the host address spaces are overlapped. When an address is translated with the settings shown in figure 18.11, host address spaces 1 and 2 are overlapped and host address space 2 and the on-chip RAM space are overlapped. In this case, since command space has priority over others, it is translated into slave command space. Then address space 1 is translated into slave address space 1. Next, the on-chip RAM which has priority over address space 2 and is not overlapped with address space 1 is translated into the slave on-chip RAM space.
HBAR1: H'0000, HBAR2: H'0008, RAMBAR: H'000D SAR1: H'00, SAR2: H'10, RAMAR: H'E0 ASSR: H'64 (768 k, 512 k), RAMASSR: H'10 (4 k)
H'00_0000
H'0000_0000
Address space 1
Address space 1 H'0007_FFFF H'0008_0000 H'000B_FFFF H'000C_0000 H'000C_FFFF H'000D_0000 H'000D_0FFF H'000D_1000 H'000D_FFEF H'000D_FFF0 H'000D_FFFF H'000E_0000 H'000F_FFFF Host address Address space 2 On-chip RAM space
H'0B_FFFF H'0C_0000 H'13_FFFF H'14_0000 H'15_FFFF H'15_0000 H'15_1FFF H'15_2000 H'15_FFEF H'15_FFF0 H'15_FFFF H'16_0000 H'17_FFFF
Address space 2
Command space
Command space
H'FF_E000 H'FF_EFFF
On-chip RAM space
Slave address Notes: Addresses of H'000D_FFF0 to H'000D_FFFF in the host address are used as command space. Addresses of H'15_FFF0 to H'15_FFFF in the slave address are used as command space.
Figure 18.11 Example 1 of Address Space Priority
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Section 18 LPC Interface (LPC)
18.4.13 Example 2 of Address Space Priority Figure 18.12 shows another example of an address translation when the slave address spaces are overlapped. In the case of the settings shown in figure 18.12, slave address spaces 1 and 2 are overlapped. Since host address spaces 1 and 2, however, are not overlapped, those addresses are always translated into the corresponding slave addresses. As long as the host address spaces are not overlapped, host addresses are translated into the corresponding slave addresses even if the slave address spaces are overlapped. In this example, addresses of H'040000 to H'0BFFFF in the slave address space are accessed from both host address spaces 1 and 2.
HBAR1: H'0000, HBAR2: H'000C, SAR1: H'00, SAR2: H'04, ASSR: H'66 (768 k, 512 k) H'00000000 H'000000 Address space 1 Address space 1 H'03FFFF H'040000 Address space 2 H'000BFFFF H'000C0000 H'0BFFFF H'0C0000
Address space 2
H'0FFFFF
H'0017FFFF
Slave address
Host address
Figure 18.12 Example 2 of Address Space Priority
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Section 18 LPC Interface (LPC)
18.4.14 Flash Memory Protection To protect the flash memory contents, the flash memory is divided into blocks given in figure 18.13. Protection for each block can be enabled or disabled by the setting of the WPB or RPB bits. The write blocks are used in LPC/FW memory write cycles and the read blocks are used in LPC/FW memory read cycles. Access to the flash memory with other than LPC/FW memory cycles are not supported. The write block protection by the WPB bit is used to set/clear erase block protection in the block erasure command. All the blocks are protected by the initial values. When accessing to the flash memory, the protection must be disabled. When the protection is disabled, 0 can be written to only once after system reset. If the protection is enabled again after it has been disabled, the protection can be disabled only by the system reset.
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Section 18 LPC Interface (LPC)
H'000000 H'001000 H'002000 H'003000 H'004000 H'00C000 H'00D000 H'00E000 H'00F000 H'010000 H'020000 H'030000 H'040000 H'050000 H'060000 H'070000 H'080000 H'090000 H'0A0000 H'0B0000 H'0C0000 H'0D0000 H'0E0000 H'0F0000
4 kbytes (0) 4 kbytes (1) 4 kbytes (2) 4 kbytes (3) 32 kbytes (4) 4 kbytes (5) 4 kbytes (6) 4 kbytes (7) 4 kbytes (8) 64 kbytes (9) 64 kbytes (10) 64 kbytes (11) 64 kbytes (12) 64 kbytes (13) 64 kbytes (14) 64 kbytes (15) 64 kbytes (16) 64 kbytes (17) 64 kbytes (18) 64 kbytes (19) 64 kbytes (20) 64 kbytes (21) 64 kbytes (22) 64 kbytes (23) Write block
4 kbytes (0) 4 kbytes (1) 4 kbytes (2) 4 kbytes (3) 32 kbytes (4) 4 kbytes (5) 4 kbytes (6) 4 kbytes (7) 4 kbytes (8) 64 kbytes (9) 64 kbytes (10) 64 kbytes (11) 64 kbytes (12) 64 kbytes (13) 64 kbytes (14) 64 kbytes (15) 64 kbytes (16) 64 kbytes (17) 64 kbytes (18) 64 kbytes (19) 64 kbytes (20) 64 kbytes (21) 64 kbytes (22) 64 kbytes (23) Read block
Figure 18.13 Flash Memory Protection
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Section 18 LPC Interface (LPC)
18.4.15 On-Chip RAM Protection The on-chip RAM protection to the host access can be enabled or disabled by the setting of the RAMWE or RAMRE bits. The on-chip RAM is protected by the initial value. When accessing to the on-chip RAM, the protection must be disabled. Figure 18.14 shows the protected address space in the on-chip RAM.
H'000000 H'0FFFFF H'100000
On-chip ROM WPB/RRB
H'FFD0FF H'FFD100 H'FFEFFF H'FFF000 H'FFFFFF
On-chip RAM RAMWE/RAMRE
Figure 18.14 Protected Address Space in On-Chip RAM 18.4.16 Flash Memory Programming Figure 18.15 shows an example of flowchart for programming the flash memory in the LPC/FW memory write cycle.
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Section 18 LPC Interface (LPC)
Start Initial settings Read LMCST1 and LMCST2 No Flag clear ? [3] Specify the start address of the user MAT programming [4] Wait for ready for flash memory programming [1] Specify the start address of buffer in the on-chip RAM used for the flash memory programming (RBUFAR) etc. [2] Check LPC/FW memory write cycle processing state
Yes Issue FLWAR setting command Read BUFTRAN bit in LMCST2 No BUFTRAN = 1? Yes Issue data write command Read LMCBSY flag in LMCST2 No LMCBSY = 0? Yes Data write end? Yes Issue flash memory programming command Read BUFTRAN bit in LMCST2 No BUFTRAN = 0? Yes Read FLPI flag in LMCST1 No No
[5] Write data to be programmed to the flash memory to RAM
[6] Wait for the completion of transferring data to be written to RAM
[7] Start programming data to the flash memory
[8] Wait for completion of programming data to the flash memory
FLPI = 0? Yes Read FLPERR flag in LMCST1 FLPERR = 0? Yes End Error processing No [9] Check whether programming flash memory has been completed
Figure 18.15 Example of Programming Flash Memory
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Section 18 LPC Interface (LPC)
18.4.17 Flash Memory Erasing Figure 18.16 shows a flowchart example of erasing the flash memory in the LPC/FW memory write cycle.
Start Initial settings Read LMCST1 and LMCST2 No Flag clear? Yes Issue erasing enable command Read ERASEE bit in LMCST2 No [2] Enable erasing flash memory [1] Check the LPC/FW memory write cycle processing state
ERASEE = 1? [3] Start erasing flash memory block
Yes Issue block erasure command Read ERASEE bit in LMCST2 No
ERASEE = 0? Yes
Read FLEI bit in LMCST1 No
[4] Wait for completion of erasing flash memory block
FLEI = 0? Yes
Read FLEERR flag in LMCST1
[5] Check whether flash memory block has been erased
FLEERR = 0? Yes End
No
Error processing
Figure 18.16 Example of Erasing Flash Memory
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Section 18 LPC Interface (LPC)
18.5
18.5.1
Interrupt Sources
IBFI1, IBFI2, IBFI3, IBFI4, LMC, LMCUI, and ERRI
The host has seven interrupt requests for the slave (this LSI): IBF1, IBF2, IBF3, IBF4, LMC, LMCUI, and ERRI. IBFI1, IBFI2, IBFI3, and IBFI4 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset, LPC shutdown, or transfer cycle abort. The LMCI and LMCUI interrupts are command receive complete interrupts. An interrupt request is enabled by setting the corresponding enable bit. Table 18.12 Receive Complete Interrupts and Error Interrupt
Interrupt IBFI1 IBFI2 IBFI3 IBFI4 LMCI Description When IBFIE1 is set to 1 and IDR1 reception is completed When IBFIE2 is set to 1 and IDR2 reception is completed When IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and IBFIE3 are set to 1 and reception is completed up to TWR15 When IBFIE4 is set to 1 and IDR4 reception is completed * * * LMCUI ERRI When the FLPI bit is set to 1 with the FLPIE and FLASHE bits set to 1 When the FLEI bit is set to 1 with the FLEIE and FLASHE bits set to 1 When the BUFINI bit is set to 1 with the BUFINIE bit set to 1
When the USERI bit is set to 1 with the USERIE bit set to 1. When ERRIE is set to 1 and one of LRST, SDWN and ABRT is set to 1
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Section 18 LPC Interface (LPC)
18.5.2
SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12
The LPC interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can be requested from LPC channel 2, 3, or 4. There are two ways of clearing a host interrupt request. When the IEDIR bit in SIRQCR0is cleared to 0, host interrupt sources and LPC channels are all linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read of ODR or TWR15 by the host in the corresponding LPC channel, the corresponding host interrupt enable bit is automatically cleared to 0, and the host interrupt request is cleared. When the IEDIR bit is set to 1 in SIRQCR0, a host interrupt is requested by the only upon the host interrupt enable bits. The host interrupt enable bit is not cleared when OBF is cleared. Therefore, SMIE1, SMIE2, SMIE3A and SMIE3B, SMIE, IRQ10En, and IRQ11En lose their respective functional differences. In order to clear a host interrupt request, it is necessary to clear the host interrupt enable bit. (n = 2 to 4.) Table 18.13 summarizes the methods of setting and clearing these bits, and figure 18.17 shows the processing flowchart.
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Section 18 LPC Interface (LPC)
Table 18.13 HIRQ Setting and Clearing Conditions
Host Interrupt HIRQ1 (independent from IEDIR) HIRQ12 (independent from IEDIR) SMI (IEDIR2 = 1, IEDIR3 = 1, or IEDIR4 = 1) Setting Condition Clearing Condition
Internal CPU writes to ODR1, then reads 0 Internal CPU writes 0 to bit IRQ1E1, from bit IRQ1E1 and writes 1 or host reads ODR1 Internal CPU writes to ODR1, then reads 0 Internal CPU writes 0 to bit from bit IRQ12E1 and writes 1 IRQ12E1, or host reads ODR1 Internal CPU * * * * writes to ODR2, then reads 0 from bit SMIE2 and writes 1 writes to ODR3, then reads 0 from bit SMIE3A and writes 1 Internal CPU * * writes 0 to bit SMIE2, or host reads ODR2 writes 0 to bit SMIE3A, or host reads ODR3 writes 0 to bit SMIE3B, or host reads TWR15 writes 0 to bit SMIE4, or host reads ODR4 writes 0 to bit SMIE2 writes 0 to bit SMIE3A writes 0 to bit SMIE3B writes 0 to bit SMIE4 writes 0 to bit IRQiE2, or host reads ODR2 CPU writes 0 to bit IRQiE3, or host reads ODR3 CPU writes 0 to bit IRQiE4, or host reads ODR4 writes 0 to bit IRQiE2 writes 0 to bit IRQiE3 writes 0 to bit IRQiE4
writes to TWR15, then reads 0 from bit * SMIE3B and writes 1 writes to ODR4, then reads 0 from bit SMIE4 and writes 1 reads 0 from bit SMIE2, then writes 1 *
SMI (IEDIR2 = 1, IEDIR3 = 1, or IEDIR4 = 1)
Internal CPU * * * *
Internal CPU *
reads 0 from bit SMIE3A, then writes 1 * reads 0 from bit SMIE3B, then writes 1 * reads 0 from bit SMIE4, then writes 1 * * * *
HIRQi Internal CPU (i = 6, 9, 10, 11) * writes to ODR2, then reads 0 from bit (IEDIR2 = 1, IRQiE2 and writes 1 IEDIR3 = 1, or * writes to ODR3, then reads 0 from bit IEDIR4 = 1) IRQiE3 and writes 1 * HIRQi (i = 6, 9, 10, 11) (IEDIR2 = 1, IEDIR3 = 1, or IEDIR4 = 1) writes to ODR4, then reads 0 from bit IRQiE4 and writes 1 reads 0 from bit IRQiE2, then writes 1 reads 0 from bit IRQiE3, then writes 1 reads 0 from bit IRQiE4, then writes 1
Internal CPU
Internal CPU * * *
Internal CPU * * *
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Section 18 LPC Interface (LPC)
Slave CPU
Master CPU
ODR1 write Interrupt initiation ODR1 read
Write 1 to IRQ1E1
SERIRQ IRQ1 output SERIRQ IRQ1 source clear
No
OBF1 = 0? Yes All bytes transferred? Hardware operation Yes Software operation
No
Figure 18.17 HIRQ Flowchart (Example of Channel 1)
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Section 18 LPC Interface (LPC)
18.6
18.6.1
Usage Note
Data Conflict
The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid data conflict. For example, if the host and slave both try to access IDR or ODR at the same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to data for which writing has finished. Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to TWR15 has been obtained. Table 18.14 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3, TWR0MW, TWR0SW, and TWR1 to TWR15.
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Section 18 LPC Interface (LPC)
Table 18.14 Host Address Example
Register IDR3 ODR3 STR3 TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3FD0 H'A24A and H'A24E H'A24A H'A24E H'A250 H'A250 H'A251 H'A252 H'A253 H'A254 H'A255 H'A256 H'A257 H'A258 H'A259 H'A25A H'A25B H'A25C H'A25D H'A25E H'A25F H'3FD0 and H'3FD4 H'3FD0 H'3FD4 H'3FC0 H'3FC0 H'3FC1 H'3FC2 H'3FC3 H'3FC4 H'3FC5 H'3FC6 H'3FC7 H'3FC8 H'3FC9 H'3FCA H'3FCB H'3FCC H'3FCD H'3FCE H'3FCF
18.6.2
Module Stop Mode Setting
Module stop mode should not be set to the LPC while the LPC/FW memory write cycle is enabled. Specify module stop mode after confirming that the LMCE bit in LMCCR1 is cleared to 0. 18.6.3 Operating Mode in LPC/FW Memory Write Cycle
The LPC/FW memory cycle should be enabled in advanced mode; disabled in normal mode.
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Section 18 LPC Interface (LPC)
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Section 19 A/D Converter
Section 19 A/D Converter
This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to eight analog input channels to be selected.
19.1
Features
* 10-bit resolution * Input channels: Eight analog input channels * Analog conversion voltage range can be specified using the reference power supply voltage pin (AVref) as an analog reference voltage. * Conversion time: 13.4 s per channel (at 20-MHz operation) * Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on one to four channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of A/D conversion start Software Timer (TPU or 8-bit timer) conversion start trigger External trigger signal * Interrupt source A/D conversion end interrupt (ADI) request can be generated * Module stop mode can be set A block diagram of the A/D converter is shown in figure 19.1.
ADCMS33A_000020020300
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Section 19 A/D Converter
Module data bus
Internal data bus
AVCC AVref AVSS 10-bit D/A
Successive approximations register
A D D R A
A D D R B
A D D R C
A D D R D
A D C S R
A D C R
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
+
Bus interface
/8 Control circuit /16 ADI interrupt signal Conversion start trigger from TPU or 8-bit timer
Multiplexer
Comparator Sample-and-hold circuit
ADTRG [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D
Figure 19.1 Block Diagram of A/D Converter
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Section 19 A/D Converter
19.2
Input/Output Pins
Table 19.1 summarizes the pins used by the A/D converter. The eight analog input pins are divided into two groups consisting of four channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group1. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. Table 19.1 Pin Configuration
Pin Name Symbol I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger input pin for starting A/D conversion Group 1 analog input pins Function Analog block power supply Analog block ground and reference voltage Analog block reference voltage Group 0 analog input pins
Analog power supply AVCC pin Analog ground pin Reference power supply pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin AVSS AVref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG
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Section 19 A/D Converter
19.3
Register Descriptions
The A/D converter has the following registers. * * * * * * A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) A/D Data Registers A to D (ADDRA to ADDRD)
19.3.1
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers which store a conversion result for each channel are shown in table 19.2. The 10-bit conversion data is stored in bits 15 to 6. The lower six bits are always read as 0. The data bus between the CPU and A/D converter is eight bits wide. The upper byte can be read directly from the CPU. However, when the lower byte is read from, data that was transferred to a temporary register at reading of the upper byte is read. Accordingly, when reading from ADDR, access in word units or access upper byte first, and then lower byte. Table 19.2 Analog Input Channels and Corresponding ADDR
Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register to Store A/D Conversion Results ADDRA ADDRB ADDRC ADDRD
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Section 19 A/D Converter
19.3.2
A/D Control/Status Register (ADCSR)
ADCSR controls A/D converter operation.
Bit 7 Bit Name Initial Value ADF 0 R/W R/(W)* Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all channels specified in scan mode When 0 is written after reading ADF = 1 When DTC is activated by an ADI interrupt and ADDR is read
[Clearing conditions] * * 6 5 ADIE ADST 0 0 R/W R/W
A/D Interrupt Enable Enables ADI interrupt by ADF when this bit is set to 1. A/D Start Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel ends. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode.
4
SCAN
0
R/W
Scan Mode Selects the A/D converter operating mode. 0: Single mode 1: Scan mode Switch the operating mode when ADST = 0.
3
CKS
0
R/W
Clock Select Sets A/D conversion time. 0: Conversion time is 266 states (max) 1: Conversion time is 134 states (max) (when the system clock () is 16 MHz or lower) Switch conversion time while the ADST bit is cleared to 0.
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Section 19 A/D Converter
Bit 2 1 0
Bit Name Initial Value CH2 CH1 CH0 0 0 0
R/W R/W R/W R/W
Description Channel Select 2 to 0 Select analog input channels. When SCAN = 0 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 When SCAN = 1 000: AN0 001: AN0 and AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN4 101: AN4 and AN5 110: AN4 to AN6 111: AN4 to AN7
Switch input channels when ADST = 0. Note: * Only 0 can be written for clearing the flag.
19.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit 7 6 Bit Name Initial Value TRGS1 TRGS0 0 0 R/W R/W R/W Description Timer Trigger Select 1 and 0 Enable the start of A/D conversion by a trigger signal. Set these bits only while A/D conversion is stopped (ADST = 0). 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by conversion trigger from TPU 10: A/D conversion start by conversion trigger from TMR 11: A/D conversion start by ADTRG pin 5 to 0 All 1 R/W Reserved The initial value should not be changed.
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Section 19 A/D Converter
19.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion. The ADST bit can be set at the same time the operating mode or analog input channel is changed. 19.4.1 Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel. Operations are as follows. 1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1 by software or an external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is automatically cleared to 0, and the A/D converter enters wait state. 19.4.2 Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels (max. four channels). Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D conversion starts on the first channel in the group (AN0 when the CH2 bit in ADCSR is 0, or AN4 when the CH2 bit in ADCSR is 1). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion from the first channel in the group starts again. 4. The ADST bit is not automatically cleared to 0 so steps [2] and [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
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Section 19 A/D Converter
19.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 19.2 shows the A/D conversion timing. Table 19.3 indicates the A/D conversion time. As indicated in figure 19.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of write to ADCSR. The total conversion time therefore varies within the ranges indicated in table 19.3. In scan mode, the values shown in table 19.3 become those for the first conversion time. For the second and subsequent conversions, the conversion time is 266 states (fixed) when CKS = 0 and 134 states (fixed) when CKS = 1. Use the conversion time of 134 states only when the system clock () is 16 MHz or lower.
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Section 19 A/D Converter
(1)
Address
(2)
Write signal
Input sampling timing
ADF tD tSPL tCONV [Legend] (1) : ADCSR write cycle (2) : ADCSR address tD : A/D conversion start delay tSPL : Input sampling time tCONV : A/D conversion time
Figure 19.2 A/D Conversion Timing
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Section 19 A/D Converter
Table 19.3 A/D Conversion Time (Single Mode)
CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min. 10 259 Typ. 63 Max. 17 266 Min. 6 131 CKS = 1* Typ. 31 Max. 9 134
Notes: Values in the table indicate the number of states. * in the table indicates that the system clock () is 16 MHz or lower.
19.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B11 in ADCR, an external trigger is input to the ADTRG pin. The ADST bit in ADCSR is set to 1 at the falling edge of the ADTRG pin, thus starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 19.3 shows the timing.
ADTRG
Internal trigger signal
ADST A/D conversion
Figure 19.3 External Trigger Input Timing
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Section 19 A/D Converter
19.5
Interrupt Source
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. If the ADF bit in ADCSR has been set to 1 after A/D conversion ends and the ADIE bit is set to 1, an ADI interrupt request is enabled. The ADI interrupt can be used to activate the on-chip DTC. Table 19.4 A/D Converter Interrupt Source
Name ADI Interrupt Source A/D conversion end Interrupt Flag ADF DTC Activation Enable
19.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 19.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristics when the digital output changes from the minimum voltage value B'00 0000 0000 (H'000) to B'00 0000 0001 (H'001) (see figure 19.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristics when the digital output changes from B'11 1111 1110 (H'3FE) to B'11 1111 1111 (H'3FF) (see figure 19.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 19.5). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error.
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Section 19 A/D Converter
Digital output
H'3FF H'3FE H'3FD H'004 H'003 H'002 H'001 H'000
Ideal A/D conversion characteristic
Quantization error
1 2 1024 1024
1022 1023 FS 1024 1024 Analog input voltage
Figure 19.4 A/D Conversion Accuracy Definitions
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error Actual A/D conversion characteristic
FS
Offset error
Analog input voltage
Figure 19.5 A/D Conversion Accuracy Definitions
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Section 19 A/D Converter
19.7
19.7.1
Usage Notes
Permissible Signal Source Impedance
This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., voltage fluctuation ratio of 5 mV/s or greater) (see figure 19.6). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 19.7.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not interfere with digital signals on the mounting board, so acting as antennas.
This LSI Sensor output impedance up to 5 k Sensor input Low-pass filter C up to 0.1 F
Cin = 15 pF
A/D converter equivalent circuit
10 k
20 pF
Figure 19.6 Example of Analog Input Circuit
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Section 19 A/D Converter
19.7.3
Setting Range of Analog Power Supply and Other Pins
If conditions shown below are not met, the reliability of this LSI may be adversely affected. Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ANn AVref (n = 0 to 7). * Relation between AVcc, AVss and Vcc, Vss For the relationship between AVcc, AVss and Vcc, Vss, set AVss = Vss, but AVcc = Vcc is not necessary and which one is greater does not matter. Even when the A/D converter is not used, the AVcc and AVss pins must on no account be left open. * AVref pin range The reference voltage of the AVref pin should be in the range AVref AVcc. 19.7.4 Notes on Board Design *
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input pins (AN0 to AN7), analog reference voltage (AVref), and analog power supply voltage (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. 19.7.5 Notes on Noise Countermeasures
A protection circuit connected to prevent damage of the analog input pins (AN0 to AN7) and analog reference voltage pin (AVref) due to an abnormal voltage such as an excessive surge should be connected between AVcc and AVss, as shown in figure 19.7. Also, the bypass capacitors connected to AVcc and AVref, and the filter capacitors connected to AN0 to AN7 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants.
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Section 19 A/D Converter
AVCC AVref
*1 *1
Rin *2
100 AN0 to AN7 0.1 F AVSS
Notes: Values are reference values.
*1
10 F
0.01 F
*2
Rin: Input impedance
Figure 19.7 Example of Analog Input Protection Circuit
10 k AN0 to AN7 20 pF
To A/D converter
Note: Values are reference values.
Figure 19.8 Analog Input Pin Equivalent Circuit 19.7.6 Module Stop Mode Setting
A/D converter operation can be enabled or disabled by the module stop control register. In the initial state, A/D converter operation is disabled. Access to A/D converter registers is enabled when module stop mode is cancelled. For details, see section 24, Power-Down Modes.
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Section 19 A/D Converter
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Section 20 RAM
Section 20 RAM
This LSI has 8 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU for both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR).
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Section 20 RAM
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Section 21 Flash Memory (0.18-m F-ZTAT Version)
The flash memory has the following features. Figure 21.1 shows a block diagram of the flash memory.
21.1
* Size
Features
Product Classification H8S/2114R R4F2114R
ROM Size 1 Mbyte
ROM Addresses H'000000 to H'0FFFFF (mode 2) H'0000 to H'DFFF (mode 3)
* Two flash-memory MATs according to LSI initiation mode The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs). The mode setting at initiation determines which memory MAT is initiated first. The MAT can be switched by using the bank-switching method after initiation. The user MAT is initiated at a power-on reset in user mode: 1 Mbyte The user boot memory MAT is initiated at a power-on reset in user boot mode: 8 kbytes * Programming/erasing interface by the download of on-chip program This LSI has a dedicated programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the argument parameter. * Programming/erasing time The flash memory programming time is 3 ms (typ) in 128-byte simultaneous programming, and approximately 25 s per byte. The erasing time is 1000 ms (typ) per 64-kbyte block. * Number of programming The number of flash memory programming can be up to 100 times at the minimum. (The value ranged from 1 to 100 is guaranteed.) * Three on-board programming modes Boot mode This mode is a program mode that uses an on-chip SCI interface. The user MAT and user boot MAT can be programmed. In this mode, the bit rate between the host and this LSI can be automatically adjusted. User program mode The user MAT can be programmed by using the optional interface.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
User boot mode The user boot program of the optional interface can be made and the user MAT can be programmed. * Programming/erasing protection Sets protection against flash memory programming/erasing via hardware, software, or error protection. * Programmer mode This mode uses the PROM programmer. The user MAT and user boot MAT can be programmed.
Internal address bus
Internal data bus (16 bits)
FCCS FPCS
Module bus
FECS FKEY FMATS FTDAR Control unit
Memory MAT unit User MAT: 1 Mbyte User boot MAT: 8 kbytes
Flash memory
FWE pin Mode pins
Operating mode
[Legend] FCCS: Flash code control status register FPCS: Flash program code select register FECS: Flash erase code select register FKEY: Flash key code register FMATS: Flash MAT select register FTDAR: Flash transfer destination address register Note: To read from or write to the registers, the FLSHE bit in the serial timer control register (STCR) must be set to 1.
Figure 21.1 Block Diagram of Flash Memory
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.1.1
Mode Transitions
When each mode pin and the FWE pin are set in the reset state and the reset is started, this LSI enters each operating mode as shown in figure 21.2. * Flash memory can be read in user mode, but cannot be programmed or erased. * Flash memory can be read, programmed, or erased on the board only in user program mode, user boot mode, and boot mode. * Flash memory can be read, programmed, or erased by means of the PROM programmer in programmer mode.
RES = 0
Reset state
Programmer mode setting
Programmer mode
=0
S RE
Us er
=0
m od es
in ett
g
Bo
RE
ot mo de
S
=0
ot g bo tin er set Us de mo
RE S
RES
se
ttin g
=0
FLSHE = 0 FWE = 0
User mode
FWE = 1 FLSHE = 1
User program mode
User boot mode On-board programming mode
Boot mode
Figure 21.2 Mode Transition for Flash Memory
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.1.2
Mode Comparison
The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 21.1. Table 21.1 Comparison of Programming Modes
Boot Mode Programming/ erasing environment Programming/ erasing enable MAT All erasure Block division erasure Program data transfer Reset initiation MAT Transition to user mode On-board User Program Mode On-board User Boot Mode On-board Programmer Mode PROM programmer User MAT User boot MAT (Automatic)
User MAT User boot MAT (Automatic) *
1
User MAT
User MAT
x
From host via SCI Via optional device Via optional device Via programmer Embedded program storage MAT Changing mode setting and reset User MAT User boot MAT*2
Changing FLSHE bit and FWE pin
Changing mode setting and reset
Notes: 1. All erasure is performed. After that, the specified block can be erased. 2. First, the reset vector is fetched from the embedded program storage MAT. After the flash memory related registers are checked, the reset vector is fetched from the user boot MAT.
* The user boot MAT can be programmed or erased only in boot mode and programmer mode. * In boot mode, the user MAT and user boot MAT are totally erased. Then, the user MAT or user boot MAT can be programmed by means of commands. Note that the contents of the MAT cannot be read until this state. Boot mode can be used for programming only the user boot MAT and then programming the user MAT in user boot mode. Another way is to program only the user MAT since user boot mode is not used. * In user boot mode, boot operation of the optional interface can be performed with mode pin settings different from those in user program mode.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.1.3
Flash Memory MAT Configuration
This LSI's flash memory is configured by the 1-Mbyte user MAT and 8-kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when program execution or data access is performed between two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes. However, the user boot MAT can be programmed only in boot mode and programmer mode.
Address H'000000 Address H'000000 8 kbytes Address H'001FFF
1 Mbyte
Address H'0FFFFF
Figure 21.3 Flash Memory Configuration The size of the user MAT is different from that of the user boot MAT. An address that exceeds the size of the 8-kbyte user boot MAT should not be accessed. If the attempt is made, data is read as an undefined value. 21.1.4 Block Division
The user MAT is divided into 64 kbytes (15 blocks), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 21.4. The user MAT can be erased in this divided-block units by specifying the erase-block number of EB0 to EB23 when erasing.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
H'000000 H'000F80
H'000001 H'000F81 H'001001
H'000002 H'000F82 H'001002
EB1 Erase unit: 4 kbytes
H'001000
H'001F80 EB2 Erase unit: 4 kbytes H'002000
H'001F81 H'002001
H'001F82 H'002002
H'002F80 EB3 Erase unit: 4 kbytes H'003000
H'002F81 H'003001
H'002F82 H'003002
H'003F80 EB4 Erase unit: 32 kbytes H'004000
H'003F81 H'004001
H'003F82 H'004002 H'00BF82 H'00C002 H'00CF82 H'00D002 H'00DF82 H'00E002 H'00EF82 H'00F002
H'00BF80 H'00BF81 EB5 Erase unit: 4 kbytes H'00C000 H'00C001 H'00CF80 H'00CF81 EB6 Erase unit: 4 kbytes H'00D000 H'00D001 H'00DF80 H'00DF81 EB7 Erase unit: 4 kbytes H'00E000 H'00E001 H'00EF80 H'00EF81 EB8 Erase unit: 4 kbytes H'00F000 H'00F001
H'00FF80 H'00FF81 EB9 Erase unit: 64 kbytes H'010000 H'010001
H'00FF82 H'010002 H'01FF82 H'020002
H'01FF80 H'01FF81 EB10 Erase unit: 64 kbytes H'020000 H'020001
H'02FF80 H'02FF81 EB11 Erase unit: 64 kbytes H'030000 H'030001
H'02FF82 H'030002 H'03FF82
H'03FF80 H'03FF81
Figure 21.4 Block Division of User MAT (1)
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EB0 Erase unit: 4 kbytes
Programming unit: 128 bytes
H'00007F H'000FFF H'00107F H'001FFF H'00207F
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
H'002FFF H'00307F H'003FFF H'00407F H'00BFFF H'00C07F H'00CFFF H'00D07F H'00DFFF H'00E07F
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
H'00EFFF H'00F07F H'00FFFF H'01007F
Programming unit: 128 bytes
Programming unit: 128 bytes
H'01FFFF H'02007F H'02FFFF H'03007F
Programming unit: 128 bytes
H'03FFFF
Section 21 Flash Memory (0.18-m F-ZTAT Version)
EB12 Erase unit: 64 kbytes
H'040000
H'040001
H'040002 H'04FF82 H'050002
Programming unit: 128 bytes
H'04FF80 H'04FF81 EB13 Erase unit: 64 kbytes H'050000 H'050001
H'05FF80 H'05FF81 EB14 Erase unit: 64 kbytes H'060000 H'060001
H'05FF82 H'060002
H'06FF80 H'06FF81 EB15 Erase unit: 64 kbytes H'070000 H'070001
H'06FF82 H'070002
H'07FF80 H'07FF81 EB16 Erase unit: 64 kbytes H'080000 H'080001
H'07FF82 H'080002 H'08FF82 H'900002 H'09FF82
H'08FF80 H'08FF81 EB17 Erase unit: 64 kbytes H'090000 H'900001
H'09FF80 H'09FF81 EB18 Erase unit: 64 kbytes
H'0A0000 H'A0D001 H'0A0002 H'0AFF80 H'0AFF81 H'0AFF82 H'0B0002 H'0BFF82 H'0C0002
EB19 Erase unit: 64 kbytes
H'0B0000 H'0B0001 H'0BFF80 H'0BFF81
EB20 Erase unit: 64 kbytes
H'0C0000 H'0C0001
H'0CFF80 H'0CFF81 H'0CFF82 EB21 Erase unit: 64 kbytes H'0DFF80 H'0DFF81 H'0DFF82 EB22 Erase unit: 64 kbytes H'0E0000 H'0E0001 H'0E0002 H'0D0000 H'0D0001 H'0D0002
H'0EFF80 H'0EFF81 EB23 Erase unit: 64 kbytes H'0F0000 H'0F0001
H'0EFF82 H'0F0002 H'0FFF82
H'0FFF80 H'0FFF81
Figure 21.4 Block Division of User MAT (2)

H'04007F H'04FFFF H'05007F H'05FFFF H'06007F
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
H'06FFFF H'07007F H'07FFFF H'08007F H'08FFFF H'09007F H'09FFFF H'0A007F H'0AFFFF H'0B007F
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
H'0BFFFF H'0C007F H'0CFFFF H'0D007F
Programming unit: 128 bytes
Programming unit: 128 bytes
H'0DFFFF H'0E007F H'0EFFFF H'0F007F
Programming unit: 128 bytes
H'0FFFFF
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.1.5
Programming/Erasing Interface
Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program is made by the user in user program mode and user boot mode. An overview of the procedure is given as follows. For details, see section 21.4.2, User Program Mode.
Start user procedure program for programming/erasing Select on-chip program to be downloaded and specify the destination Download on-chip program by setting the FKEY and SCO bits Initialization execution (downloaded program execution)
Programming (in 128-byte units) or erasing (in one-block units) (downloaded program execution)
No
Programming/erasing completed? Yes End user procedure program
Figure 21.5 Overview of User Procedure Program
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
1. Selection of on-chip program to be downloaded For programming/erasing execution, set the FLSHE bit in STCR to 1 to make a transition to user program mode. This LSI has programming/erasing programs that can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface register. The address of the download destination is specified by the flash transfer destination address register (FTDAR). 2. Download of on-chip program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control status register (FCCS), which are programming/erasing interface registers. The flash memory MAT is replaced with the embedded program storage MAT during downloading. Since the flash memory cannot be read during programming/erasing, the procedure program that executes download to completion of programming/erasing must be executed in a space other than flash memory (for example, on-chip RAM). Since the result of download is returned to the programming/erasing interface parameter, whether download has succeeded or not can be confirmed. 3. Initialization of programming/erasing Set the operating frequency before execution of programming/erasing. This setting is performed by using the programming/erasing interface parameter. 4. Execution of programming/erasing For programming/erasing execution, set the FLSHE bit in STCR and the FWE pin to 1 to make a transition to user program mode. The program data/programming destination address is specified in 128-byte units for programming. The block to be erased is specified in erase-block units for erasing. Make these specifications by using the programming/erasing interface parameter, and then initiate the on-chip program. The on-chip program is executed by using the JSR or BSR instruction to execute the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameter. The area to be programmed must be erased in advance when programming flash memory. All interrupts must be disabled during programming and erasing. Interrupts must be masked within the user system.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
5. Consecutive execution of programming/erasing When the 128-byte programming or one-block erasure does not end the processing, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program remains in the on-chip RAM even after the processing ends, download and initialization are not required when the same processing is executed consecutively.
21.2
Input/Output Pins
Flash memory is controlled by the pins listed in table 21.2. Table 21.2 Pin Configuration
Pin Name RES FWE MD2 MD1 MD0 TxD1 RxD1 Input/Output Input Input Input Input Input Output Input Function Reset Flash memory programming/erasing enable pin Sets operating mode of this LSI Sets operating mode of this LSI Sets operating mode of this LSI Serial transmit data output (used in boot mode) Serial receive data input (used in boot mode)
21.3
Register Descriptions
The registers/parameters that control flash memory are shown below. To read from or write to these registers/parameters, the FLSHE bit in STCR must be set to 1. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). * * * * * * * * Flash code control status register (FCCS) Flash program code select register (FPCS) Flash erase code select register (FECS) Flash key code register (FKEY) Flash MAT select register (FMATS) Flash transfer destination address register (FTDAR) Download pass/fail result (DPFR) Flash pass/fail result (FPFR)
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
* Flash multipurpose address area (FMPAR) * Flash multipurpose data destination area (FMPDR) * Flash erase block select (FEBS) * Flash programming/erasing frequency control (FPEFEQ) There are several operating modes for accessing flash memory, for example, read mode/program mode. There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence between operating modes and registers/parameters for use is shown in table 21.3. Table 21.3 Register/Parameter and Target Mode
Download Initialization Programming/ FCCS erasing interface FPCS registers FECS FKEY FMATS FTDAR Programming/ DPFR erasing interface FPFR parameters FPEFEQ FMPAR FMPDR FEBS Programming *
1
Erasure *
1
Read *2
Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target MAT.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.3.1
Programming/Erasing Interface Registers
The programming/erasing interface registers are all 8-bit registers that can be accessed in bytes. These registers are initialized at a reset or in hardware standby mode. * Flash Code Control Status Register (FCCS) FCCS is configured by bits which request monitoring of the FWE pin state and error occurrence during programming or erasing flash memory, and the download of an on-chip program.
Bit 7 Initial Bit Name Value FWE 1/0 R/W R Description Flash Program Enable Monitors the signal level input to the FWE pin. 0: A low level signal is input to the FWE pin. (Hardware protection state) 1: A high level signal is input to the FWE pin. 6, 5 All 0 R/W Reserved The initial value should not be changed.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Bit 4
Initial Bit Name Value FLER 0
R/W R
Description Flash Memory Error Indicates an error has occurred during programming or erasing flash memory. When this bit is set to 1, flash memory enters the error-protection state. In case this bit is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset must be released after a reset period of 100 s which is longer than normal. 0: Flash memory operates normally. Programming/erasing protection (error protection) for flash memory is invalid. [Clearing condition] * At a reset or in hardware standby mode 1: An error occurs during programming/erasing flash memory. Programming/erasing protection (error protection) for flash memory is valid. [Setting conditions] * * When an interrupt, such as NMI, occurs during programming/erasing flash memory. When flash memory is read during programming/erasing flash memory (including a vector read or an instruction fetch). When the SLEEP instruction is executed during programming/erasing flash memory (including software standby mode) When a bus master other than the CPU, such as the DTC or LPC, gets bus mastership during programming/erasing flash memory.
*
*
3 to 1
All 0
R/W
Reserved The initial value should not be changed.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Bit 0
Initial Bit Name Value SCO 0
R/W (R)/W*
Description Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM specified by FTDAR. In order to set this bit to 1, H'A5 must be written to FKEY and this operation must be executed in the on-chip RAM. Immediately after setting this bit to 1, four NOP instructions must be executed. Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. All interrupts must be disabled during downloading. Interrupts must be masked within the user system. 0: Download of the on-chip programming/erasing program to the on-chip RAM is not executed. [Clearing condition] When download is completed 1: Request to download the on-chip programming/erasing program to the on-chip RAM has occurred. [Setting conditions] When all of the following conditions are satisfied and this bit is set to 1 * H'A5 is written to FKEY * During execution in the on-chip RAM
Note:
*
This bit is a write only bit. This bit is always read as 0.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
* Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded.
Bit 7 to 1 0 Initial Bit Name Value PPVS All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Program Pulse Verify Selects the programming program. 0: On-chip programming program is not selected. [Clearing condition] When transfer is completed 1: On-chip programming program is selected.
* Flash Erase Code Select Register (FECS) FECS selects the on-chip erasing program to be downloaded.
Bit 7 to 1 0 Initial Bit Name Value EPVB All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Erase Pulse Verify Block Selects the erasing program. 0: On-chip erasing program is not selected. [Clearing condition] When transfer is completed 1: On-chip erasing program is selected.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
* Flash Key Code Register (FKEY) FKEY is for software protection that enables download of an on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 to download an on-chip program or before executing the downloaded programming/erasing program, the key code must be written, otherwise the processing cannot be executed.
Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Key Code Only when H'A5 is written, writing to the SCO bit is valid. When a value other than H'A5 is written to FKEY, 1 cannot be set to the SCO bit. Therefore downloading to the on-chip RAM cannot be executed. Only when H'5A is written, programming/erasing can be executed. Even if the on-chip programming/erasing program is executed, the flash memory cannot be programmed or erased when a value other than H'5A is written to FKEY. H'A5: Writing to the SCO bit is enabled. (The SCO bit cannot be set by a value other than H'A5.) H'5A: Programming/erasing is enabled. (Software protection state is entered for a value other than H'5A.) H'00: Initial value
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
* Flash MAT Select Register (FMATS) FMATS specifies whether the user MAT or user boot MAT is selected.
Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 0/1* 0 0/1* 0 0/1* 0 0/1* 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description MAT Select The user MAT is selected when a value other than H'AA is written, and the user boot MAT is selected when H'AA is written. The MAT is switched by writing a value in FMATS. When the MAT is switched, follow section 21.6, Switching between User MAT and User Boot MAT. (The user boot MAT cannot be programmed in user program mode even if the user boot MAT is selected by FMATS. The user boot MAT must be programmed in boot mode or programmer mode.) H'AA: User boot MAT is selected (user MAT is selected when the value of these bits is other than H'AA). Initial value when initiated in user boot mode. H'00: Initial value when initiated in a mode except for user boot mode (user MAT is selected) [Programmable condition] In the execution state in the on-chip RAM Note: * Set to 1 in user boot mode, otherwise cleared to 0.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
* Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address where an on-chip program is downloaded. This register must be specified before setting the SCO bit in FCCS to 1.
Bit 7 Initial Bit Name Value TDER 0 R/W R/W Description Transfer Destination Address Setting Error This bit is set to 1 when the address specified by bits TDA6 to TDA0, which is the start address where an onchip program is downloaded, is over the range. Whether or not the address specified by bits TDA6 to TDA0 is within the range of H'00 to H'03 is determined when an on-chip program is downloaded by setting the SCO bit in FCCS to 1. Make sure that this bit is cleared to 0 and the value specified by bits TDA6 to TDA0 is within the range of H'00 to H'03 before setting the SCO bit to 1. 0: The value specified by bits TDA6 to TDA0 is within the range. 1: The value specified by bits TDA6 to TDA0 is over the range (H'04 to H'7F) and download is stopped. 6 5 4 3 2 1 0 TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Transfer Destination Address Specifies the start address where an on-chip program is downloaded. A value of H'00 can be specified as the download start address in the on-chip RAM. H'00: H'FFD080 is specified as the download start address. H'01: H'FFD880 is specified as the download start address. H'02: H'FFE080 is specified as the download start address. H'03 to H'7F: Setting prohibited. Specifying this value sets the TDER bit to 1 during downloading and stops the download.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.3.2
Programming/Erasing Interface Parameters
The programming/erasing interface parameters specify the operating frequency, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. These parameters use the CPU general registers (ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a reset or in hardware standby mode. In download, initialization, or execution of the on-chip program, registers of the CPU except for R0L are stored. The return value of the processing result is written in R0L. Since the stack area is used for storing the registers except for R0L, the stack area must be saved at the processing start. (A maximum size of a stack area to be used is 128 bytes.) The programming/erasing interface parameters is used for the following four functions: 1. 2. 3. 4. Download control Initialization before programming or erasing Programming Erasing
These items use different parameters. The correspondence table is shown in table 21.4. The meaning of bits in FPFR varies in each processing: initialization, programming, or erasure. For details, see descriptions of FPFR for each processing.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Table 21.4 Parameters and Target Modes
Abbrevia- Download Parameter Name tion Download pass/fail result Flash pass/fail result DPFR FPFR Initialization Programming Erasure R/W R/W R/W R/W Initial Value Allocation

Undefined On-chip RAM* Undefined R0L of CPU Undefined ER0 of CPU

FPEFEQ Flash programming/ erasing frequency control Flash multipurpose address area FMPAR

R/W
Undefined ER1 of CPU
FMPDR Flash multipurpose data destination area Flash erase block select FEBS

R/W
Undefined ER0 of CPU

R/W
Undefined R0L of CPU
Note:
*
A single byte of the download start address specified by FTDAR.
(1)
Download Control
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area where the program is to be downloaded is the 2-kbyte area starting from the address specified by FTDAR. Download control is set by the programming/erasing interface registers, and the DPFR parameter indicates the return value. (a) Download pass/fail result parameter (DPFR: single byte of start address specified by FTDAR)
This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading was executed or not. Since confirmation whether the SCO bit is set to 1 or not is difficult, certain determination must be gained by setting a value other than the return value of download (for example, H'FF) to the single byte of the start address specified by FTDAR before download starts (before setting the SCO bit to 1).
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Bit 7 to 3 2
Initial Bit Name Value SS
R/W R/W
Description Unused The return value is 0. Source Select Error Detect Only one type can be specified for the on-chip program that can be downloaded. When more than two types of programs are selected, the program is not selected, or the program is selected without mapping, an error occurs. 0: Download program selection is normal 1: Download error has occurred (multi-selection or program which is not mapped is selected)
1
FK
R/W
Flash Key Register Error Detect Returns the check result whether the FKEY value is set to H'A5. 0: FKEY setting is normal (FKEY = H'A5) 1: FKEY setting is abnormal (FKEY = value other than H'A5)
0
SF
R/W
Success/Fail Returns the result whether download has ended normally or not. Determines the result whether the program was correctly downloaded to the on-chip RAM by way of the confirming reading of it. 0: Download to on-chip program has ended normally (no error) 1: Download to on-chip program has ended abnormally (error occurred)
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(2)
Programming/Erasing Initialization
The on-chip programming/erasing program to be downloaded includes the initialization program. A pulse of the specified width must be applied when programming or erasing. The specified pulse width is made by the method in which a wait loop is configured by CPU instructions. The operating frequency of the CPU must be set too. The initialization program is used to set the above values as parameters of the programming/erasing program that was downloaded. (a) Flash programming/erasing frequency control parameter (FPEFEQ: general register ER0 of CPU)
This parameter sets the operating frequency of the CPU. The settable range of the operating frequency in this LSI is 4 to 20 MHz.
Bit Initial Bit Name Value R/W R/W Description Unused These bits should be cleared to 0. 15 to 0 F15 to F0 Frequency Set These bits set the operating frequency of the CPU. The setting value must be calculated with the following procedure. 1. The operating frequency shown in MHz units must be rounded off to two decimals. 2. The value multiplied by 100 is converted to the hexadecimal numeral and written to the FPEFEQ parameter (general register ER0). For example, when the operating frequency of the CPU is 20.000 MHz, the setting value is as follows: 1. 20.000 is rounded off to two decimals, thus becoming 20.00. 2. The formula of 20.00 x 100 = 2000 is converted to the hexadecimal numeral and H'07D0 is set to ER0.
31 to 16
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(b)
Flash pass/fail result parameter (FPFR: general register R0L of CPU)
This parameter indicates the return value of the initialization result.
Bit 7 to 2 1 Initial Bit Name Value FQ R/W R/W Description Unused The return value is 0. Frequency Error Detect Returns the check result whether the specified CPU operating frequency is in the range of the supported operating frequency. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal 0 SF R/W Success/Fail Indicates whether initialization has ended normally or not. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurred)
(3)
Programming Execution
When flash memory is programmed, the programming destination address on the user MAT must be passed to the programming program in which the program data has been downloaded. 1. The start address of the programming destination on the user MAT must be set in general register ER1. This parameter is called the flash multipurpose address area parameter (FMPAR). Since the program data is always in 128-byte units, the lower eight bits (A7 to A0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT. 2. The program data for the user MAT must be prepared in a consecutive area. The program data must be in the consecutive space that can be accessed by using the MOV.B instruction of the CPU and in an address space other than flash memory. When data to be programmed does not satisfy 128 bytes, 128-byte program data must be prepared by filling in the dummy code H'FF. The start address of the area in which the prepared program data is stored must be set in general register ER0. This parameter is called the flash multipurpose data destination area parameter (FMPDR).
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
For details on the programming procedure, see section 21.4.2, User Program Mode. (a) Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU)
This parameter stores the start address of the programming destination on the user MAT. When the address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in the FPFR parameter.
Bit Initial Bit Name Value R/W R/W Description These bits store the start address of the programming destination on the user MAT. Consecutive 128-byte programming is executed starting from the specified start address of the user MAT. Therefore, the specified programming start address becomes a 128-byte boundary and the MOA6 to MOA0 bits are always 0.
31 to 0 MOA31 to MOA0
(b)
Flash multipurpose data destination area parameter (FMPDR: general register ER0 of CPU)
This parameter stores the start address of the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit in the FPFR parameter.
Bit Initial Bit Name Value R/W R/W Description These bits store the start address of the area which stores the program data for the user MAT. Consecutive 128-byte data is programmed to the user MAT starting from the specified start address.
31 to 0 MOD31 to MOD0
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(c)
Flash pass/fail result parameter (FPFR: general register R0L of CPU)
This parameter indicates the return value of the programming processing result.
Bit 7 6 Initial Bit Name Value MD R/W R/W Description Unused The return value is 0. Programming Mode Related Setting Error Detect Returns the check result whether a high level signal is input to the FWE pin or whether the error-protection state is not entered. When a low-level signal is input to the FWE pin or the error-protection state is entered, 1 is written to this bit. These states can be confirmed with the FWE and FLER bits in FCCS. For conditions to enter the error-protection state, see section 21.5.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: Programming cannot be performed because FWE = 0 or FLER = 1 5 EE R/W Programming Execution Error Detect 1 is returned to this bit when the specified data could not be written because the user MAT was not erased. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT are not rewritten. Programming of the user boot MAT should be performed in boot mode or programmer mode. 0: Programming has ended normally 1: Programming has ended abnormally and programming result is not guaranteed
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Bit 4
Initial Bit Name Value FK
R/W R/W
Description Flash Key Register Error Detect Returns the check result of the FKEY value before the start of the programming processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is abnormal (FKEY = value other than H'5A)
3 2
WD

R/W
Unused The return value is 0. Write Data Address Detect When an address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. 0: Setting of program data address is normal 1: Setting of program data address is abnormal
1
WA
R/W
Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. * * When the specified programming destination address is in an area other than flash memory When the specified address is not at a 128-byte boundary (the lower eight bits of the address are other than H'00 or H'80)
0: Setting of programming destination address is normal 1: Setting of programming destination address is abnormal 0 SF R/W Success/Fail Indicates whether the programming processing has ended normally or not. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurred)
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(4)
Erasure Execution
When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program that is downloaded. This is set to the FEBS parameter (general register ER0). One block is specified from the block numbers 0 to 23. For details on the erasing procedure, see section 21.4.2, User Program Mode. (a) Flash erase block select parameter (FEBS: general register ER0 of CPU)
This parameter specifies the erase-block number. Several block numbers cannot be selected at one time.
Bit Initial Bit Name Value R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Unused These bits should be cleared to 0. 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Erase Block These bits set the erase-block number in the range from 0 to 23. 0 corresponds to the EB0 block and 23 corresponds to the EB23 block. An error occurs when a number other than 0 to 23 (H'00 to H'17) is set.
31 to 8
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(b)
Flash pass/fail result parameter (FPFR: general register R0L of CPU)
This parameter indicates the return value of the erasing processing result.
Bit 7 6 Initial Bit Name Value MD R/W R/W Description Unused The return value is 0. Erasing Mode Related Setting Error Detect Returns the check result whether a high level signal is input to the FWE pin or whether the error-protection state is not entered. When a low-level signal is input to the FWE pin or the error-protection state is entered, 1 is written to this bit. These states can be confirmed with the FWE and FLER bits in FCCS. For conditions to enter the error-protection state, see section 21.5.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: Erasing cannot be performed because FWE = 0 or FLER = 1 5 EE R/W Erasure Execution Error Detect 1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT are not erased. Erasing of the user boot MAT should be performed in boot mode or programmer mode. 0: Erasure has ended normally 1: Erasure has ended abnormally and erasure result is not guaranteed 4 FK R/W Flash Key Register Error Detect Returns the check result of the FKEY value before the start of the erasing processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is abnormal (FKEY = value other than H'5A)
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Bit 3
Initial Bit Name Value EB
R/W R/W
Description Erase Block Select Error Detect Returns the check result whether the specified eraseblock number is in the block range of the user MAT. 0: Setting of erase-block number is normal 1: Setting of erase-block number is abnormal
2, 1 0
SF

R/W
Unused The return value is 0. Success/Fail Indicates whether the erasing processing has ended normally or not. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurred)
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.4
On-Board Programming
When the pins are set to on-board programming mode and the reset start is executed, a transition is made to an on-board programming state in which the on-chip flash memory can be programmed/erased. On-board programming mode has three operating modes: boot mode, user program mode, and user boot mode. For details on the pin setting for entering each mode, see table 21.5. For details of the state transition of each mode for flash memory, see figure 21.2. Table 21.5 On-Board Programming Mode Setting
Mode Setting Boot mode User program mode User boot mode Note: * FWE 1 1* 1 MD2 1 0 1 MD1 0 1 0 MD0 0 0/1 0 NMI 1 0/1 0
Before downloading a programming/erasing program, the FLSHE bit must be set to 1 to make a transition to user program mode.
21.4.1
Boot Mode
Boot mode executes programming/erasing of the user MAT and user boot MAT by means of the control commands and program data transmitted from the host via the on-chip SCI. The tool for transmitting the control commands, and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI's pins have been set to boot mode, the boot program built in the microcomputer beforehand is initiated. After the SCI bit rate is automatically adjusted, communication with the host is executed by means of control commands. A system configuration diagram in boot mode is shown in figure 21.6. For details on the pin settings in boot mode, see table 21.5. The NMI and other interrupts are ignored in boot mode. However, the NMI and other interrupts should be disabled within the user system.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
This LSI Analysis execution software (on-chip) Control command and program data RxD1 On-chip SCI_1 TxD1 Reply response On-chip RAM
Flash memory
Host Boot programming tool and program data
Figure 21.6 System Configuration in Boot Mode (1) SCI Interface Setting by Host
When boot mode is initiated, this LSI measures the low period of asynchronous SCI communication data (H'00) which is transmitted consecutively from the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received normally and then transmits 1 byte of H'55 to this LSI. When reception has not been executed normally, boot mode is initiated again (reset) and the operation described above must be performed. The bit rates of the host and this LSI do not match due to the bit rate of transmission by the host and the system clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be set to 4,800 bps, 9,600 bps, or 19,200 bps. The system clock frequency, which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI, is shown in table 21.6. Boot mode must be initiated in the range of this system clock.
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop bit
Measure low period (9 bits) (data is H'00)
High period of at least 1 bit
Figure 21.7 Automatic-Bit-Rate Adjustment Operation of SCI
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Table 21.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI
Bit Rate of Host 4,800 bps 9,600 bps 19,200 bps System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI 4 to 20 MHz 4 to 20 MHz 8 to 20 MHz
(2)
State Transition Diagram
The overview of the state transition diagram after boot mode is initiated is shown in figure 21.8. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2. Waiting for inquiry set command For inquiries about the user MAT size and configuration, MAT start address, and support state, the required information is transmitted to the host. 3. Automatic erasure of all user MATs and user boot MATs After inquiries have finished, all user MATs and user boot MATs are automatically erased. 4. Waiting for programming/erasing command When the program preparation notice is received, the state for waiting for program data is entered. The programming start address and program data must be transmitted following the programming command. When programming is finished, the programming start address must be set to H'FFFFFFFF and transmitted. Then the state of program data wait is returned to the state of programming/erasing command wait. When the erasure preparation notice is received, the state for waiting for erase-block data is entered. The erase-block number must be transmitted following the erasing command. When the erasure is finished, the erase-block number must be set to H'FF and transmitted. Then the state of erase-block data wait is returned to the state of programming/erasing command wait. This erasing operation should be used in a case where after programming has been executed in boot mode, a specific block is to be reprogrammed without a reset start. When programming can be executed by only one operation, since all blocks are erased before entering the state for waiting for a programming/erasing/other command, the erasing operation is not required. There are many commands other than programming/erasing. For example, sum check, blank check (erasure check), and memory read of the user MAT and user boot MAT, and acquisition of current status information. Note that memory read of the user MAT or user boot MAT can only read out the programmed data after all user MATs or user boot MATs have been automatically erased.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(Bit rate adjustment) H'00, ..., H'00 reception H'00 transmission (adjustment completed)
n eptio
Boot mode initiation (reset in boot mode)
Bit rate adjustment
1
rec H'55
Inquiry command reception 2 Wait for inquiry setting command Inquiry command response
Processing of inquiry setting command
3
Erasure of all user MATs and all user boot MATs
4
Wait for programming/erasing command
Read/check command reception Command response
Processing of read/check command
(Erasure end) (Programming end)
(Erasure selection command reception)
(Erase-block specification)
(Programming selection command reception) (Program data transmission)
Wait for erase-block data
Wait for program data
Figure 21.8 Overview of Boot Mode State Transition Diagram
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.4.2
User Program Mode
The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program built in the microcomputer beforehand. The programming/erasing overview flow is shown in figure 21.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, a transition to the reset state or hardware standby mode must not be made. Doing so may damage and destroy flash memory. If a reset is executed accidentally, the reset must be released after a reset input period of 100 s which is longer than normal.
Programming/erasing start
1. Make sure the program data does not overlap the download destination specified by FTDAR.
When programming, program data is prepared
2. The FWE bit is set to 1 by inputting a high level signal to the FWE pin.
Programming/erasing procedure program is transferred to the on-chip RAM and executed
3. Programming/erasing can be executed only in the on-chip RAM. However, if the program data is in a consecutive area and can be accessed by the MOV.B instruction of the CPU like RAM or ROM, the program data can be in an external space.
Programming/erasing end
4. After programming/erasing is finished, input a low level signal to the FWE pin and enter the hardware protection state.
Figure 21.9 Programming/Erasing Overview Flow
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(1)
On-Chip RAM Address Map when Programming/Erasing is Executed
Part of the procedure program that is made by the user, like the download request, programming/erasing procedure, and determination of the result, must be executed in the on-chip RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that areas in the on-chip RAM must be controlled so that these parts do not overlap. Figure 21.10 shows the area where a program is downloaded.

Area that can be used by user* DPFR (Return value: 1 byte) Area where program is downloaded (Size: 2 kbytes) This area cannot be used during the programming/ erasing processing. System area (15 bytes) FTDAR setting + 16 Programming/erasing program entry FTDAR setting + 32 Initialization program entry Initialization + programming program or Initialization + erasing program FTDAR setting + 2 kbytes Area that can be used by user* RAMEND FTDAR setting Address RAMTOP
Note: * Differs according to the area specified by FTDAR since the on-chip RAM area in this LSI is split into H'FFD080 to H'FFEFFF and H'FFFF00 to H'FFFF7F.
Figure 21.10 RAM Map when Programming/Erasing is Executed
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(2)
Programming Procedure in User Program Mode
The procedures for download, initialization, and programming are shown in figure 21.11.
Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5
1 (a) (b)
Programming
Disable interrupts and bus master operation other than CPU Set FKEY to H'5A
(i) (j) (k) (l) (m)
No
Download
Set SCO to 1 and execute download
(c) (d)
No
Set the parameters to ER1 and ER0 (FMPAR, FMPDR) Programming JSR FTDAR setting + 16 FPFR = 0?
Clear FKEY to 0
DPFR = 0?
(e)
Yes
Set the FPEFEQ parameter
Download error processing
Yes No
Required block programming is completed?
Clear FKEY Programming error processing
(f) (g) (h)
Initialization
(n) (o)
Initialization JSR FTDAR setting + 32 FPFR = 0 ?
Yes
Clear FKEY to 0 End programming procedure program
No Yes Initialization error processing
1
Figure 21.11 Programming Procedure The procedure program must be executed in an area other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 21.4.4, Storable Areas for Procedure Program and Program Data. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing has not been done yet, execute erasing before writing.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
128-byte programming is performed in one programming processing. To program more than 128 bytes, update the programming destination address/program data parameter in 128-byte units and repeat programming. When less than 128 bytes of programming is performed, the program data must amount to 128 bytes by filling in invalid data. If the invalid data to be added is H'FF, the programming processing time can be shortened. (a) Select the on-chip program to be downloaded and specify a download destination
When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the SS bit in DPFR. The start address of the download destination is specified by FTDAR. (b) Write H'A5 in FKEY
If H'A5 is not written to FKEY for protection, 1 cannot be set to the SCO bit for a download request. (c) Set the SCO bit in FCCS to 1 to execute download.
To set 1 to the SCO bit, the following conditions must be satisfied. * H'A5 is written to FKEY. * The SCO bit writing is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. When execution returns to the user procedure program, the SCO bit is already cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure program. The download result can be confirmed only by the return value of DPFR. To prevent incorrect determination, before the SCO bit is set to 1, set the single byte of the on-chip RAM start address (to be used as the DPFR parameter) specified by FTDAR to a value (e.g. H'FF) other than the return value. When download is executed, particular interrupt processing, which is accompanied by bank switchover as described below, is performed as a microcomputer internal processing. Execute four NOP instructions immediately after the instruction that sets the SCO bit to 1.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
* The user MAT space is switched to the embedded program storage MAT. * After the selection condition of the download program and the FTDAR address setting are checked, the transfer processing to the on-chip RAM specified by FTDAR is executed. * The SCO bit in FPCS, FECS, and FCCS is cleared to 0. * The return value is set to the DPFR parameter. * After the embedded program storage MAT is returned to the user MAT space, execution returns to the user procedure program. * In the download processing, the values of CPU general registers are retained. * In the download processing, all interrupts are not accepted. However, interrupt requests except for NMI are held. Therefore, when execution returns to the user procedure program, the interrupts will occur. * When the level-detection interrupt requests are to be held, interrupts must be input until the download is ended. * When hardware standby mode is entered during the download processing, normal download to the on-chip RAM cannot be guaranteed. Therefore, download must be executed again. * Since a stack area of 128 bytes at the maximum is used, the stack area must be allocated before setting the SCO bit to 1. * If a flash memory access by the DTC is requested during downloading, the operation cannot be guaranteed. Therefore, access by the DTC must not occur. (d) (e) Clear FKEY to H'00 for protection. Check the value of the DPFR parameter to confirm the download result.
* Check the value of the DPFR parameter (single byte of start address of the download destination specified by FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. * If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the address setting of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit in FTDAR. * If the value of the DPFR parameter is different from before downloading, check the SS bit and FK bit in the DPFR parameter to ensure that the download program selection and FKEY setting were normal, respectively.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(f)
Set the operating frequency to the FPEFEQ parameter for initialization.
The current frequency of the CPU clock is set to the FPEFEQ parameter (general register ER0). The settable range of the FPEFEQ parameter is 4 to 20 MHz. When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on the frequency setting, see the description in 21.3.2 (2) (a), Flash programming/erasing frequency control parameter (FPEFEQ). (g) Initialization
When a programming program is downloaded, the initialization program is also downloaded to the on-chip RAM. There is an entry point for the initialization program in the area from the start address of a download destination specified by FTDAR + 32 bytes. The subroutine is called and initialization is executed by using the following steps. MOV.L JSR NOP #DLTOP+32,ER2 @ER2 ; Set entry address to ER2 ; Call initialization routine
* The general registers other than R0L are saved in the initialization program. * R0L is a return value of the FPFR parameter. * Since the stack area is used in the initialization program, a 128-byte stack area at the maximum must be allocated in RAM. * Interrupts can be accepted during the execution of the initialization program. Note however that the program storage area and stack area in the on-chip RAM, and register values must not be rewritten. (h) The return value in the initialization program, FPFR (general register R0L) is determined. All interrupts and the use of a bus master other than the CPU are prohibited.
(i)
The stipulated voltage is applied for the stipulated time when programming or erasing. If interrupts occur or a bus master other than the CPU gets the bus during this period, a voltage pulse exceeding the regulation may be applied, thus damaging flash memory. Accordingly, interrupts must be disabled and a bus master other than the CPU, such as the DTC or LPC, must not be allowed. To disable interrupts, bit 7 (I) in the condition code register (CCR) of the CPU should be set to B'1 in interrupt control mode 0, or bits 7 and 6 (I and UI) in the condition code register (CCR) of the
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
CPU should be set to B'11 in interrupt control mode 1. This enables interrupts other than NMI to be held and not executed. The NMI interrupt must be masked within the user system. The interrupts that are held must be executed after all programming processings. When a bus master other than the CPU, such as the DTC or LPC, acquires the bus, the errorprotection state is entered. Therefore, the DTC or LPC acquiring the bus must also be prohibited. (j) (k) Set H'5A in FKEY and prepare the user MAT for programming. Set the parameters required for programming.
The start address of the programming destination of the user MAT (FMPAR) is set to general register ER1, and the start address of the program data area (FMPDR) is set to general register ER0. * Example of FMPAR setting FMPAR specifies the programming destination address. When an address other than one in the user MAT area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value parameter FPFR. Since the programming unit is 128 bytes, the lower eight bits of the address must be at the 128-byte boundary of H'00 or H'80. * Example of FMPDR setting When the storage destination of the program data is flash memory, even if the programming execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM before programming is executed.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(l)
Programming
There is an entry point for the programming program in the area from the start address of a download destination specified by FTDAR + 16 bytes. The subroutine is called and programming is executed by using the following steps. MOV.L JSR NOP #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call programming routine
* The general registers other than R0L are saved in the programming program. * R0L is a return value of the FPFR parameter. * Since the stack area is used in the programming program, a 128-byte stack area at the maximum must be allocated in RAM. (m) The return value in the programming program, FPFR (general register R0L) is determined. (n) Determine whether programming of the necessary data has finished.
If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128-byte units, and repeat steps (l) to (n). Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address that has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. (o) After programming finishes, clear FKEY and specify software protection.
If this LSI is restarted by a reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) of 100 s which is longer than normal.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(3)
Erasing Procedure in User Program Mode
The procedures for download, initialization, and erasing are shown in figure 21.12.
Start erasing procedure program
1
Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5
(a)
Disable interrupts and bus master operation other than CPU Set FKEY to H'5A
Download
Set SCO to 1 and execute download
Set the FEBS parameter Erasing JSR FTDAR setting + 16 FPFR = 0?
(b) (c) (d)
No
DPFR = 0?
No
Download error processing
Yes
Set the FPEFEQ parameter
Erasing
Clear FKEY to 0
Yes No
Required block erasing is completed?
Clear FKEY Erasing error processing
Initialization
(e) (f)
Initialization JSR FTDAR setting + 32 FPFR = 0 ?
Yes
Clear FKEY to 0
No Yes Initialization error processing
End erasing procedure program
1
Figure 21.12 Erasing Procedure The procedure program must be executed in an area other than the user MAT to be erased. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 21.4.4, Storable Areas for Procedure Program and Program Data. For the downloaded on-chip program area, see the RAM map for programming/erasing in figure 21.10.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
A single divided block is erased by one erasing processing. For block divisions, refer to figure 21.4. To erase two or more blocks, update the erase-block number and perform the erasing processing for each block. (a) Select the on-chip program to be downloaded
Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is reported to the SS bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure. For details, see section 21.4.2 (2), Programming Procedure in User Program Mode. The procedures after setting parameters for erasing programs are as follows: (b) Set the FEBS parameter necessary for erasure
Set the erase-block number of the user MAT in the flash erase block select parameter FEBS (general register ER0). If a value other than an erase-block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter FPFR. (c) Erasure
Similar to as in programming, there is an entry point for the erasing program in the area from the start address of a download destination specified by FTDAR + 16 bytes. The subroutine is called and erasing is executed by using the following steps. MOV.L JSR NOP #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call erasing routine
* The general registers other than R0L are saved in the erasing program. * R0L is a return value of the FPFR parameter. * Since the stack area is used in the erasing program, a 128-byte stack area at the maximum must be allocated in RAM.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(d) (e)
The return value in the erasing program, FPFR (general register R0L) is determined. Determine whether erasure of the necessary blocks has completed.
If more than one block is to be erased, update the FEBS parameter and repeat steps (b) to (e). Blocks that have already been erased can be erased again. (f) After erasure completes, clear FKEY and specify software protection.
If this LSI is restarted by a reset immediately after user MAT erasure has completed, secure a reset period (period of RES = 0) of 100 s which is longer than normal. (4) Erasing and Programming Procedure in User Program Mode
By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 21.13 shows a repeating procedure of erasing and programming.
Start procedure program Specify a download destination for erasing program by FTDAR
Erasing program download
1
Erasing/ Programming
Erase relevant block (execute erasing program) Set FMPDR to program relevant block (execute programming program)
Download erasing program
Initialize erasing program
Programming program download
Specify a download destination for programming program by FTDAR Download programming program Initialize programming program
Confirm operation
End ?
No Yes
1
End procedure program
Figure 21.13 Repeating Procedure of Erasing and Programming
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
In the above procedure, download and initialization are performed only once at the beginning. In this kind of operation, note the following: * Be careful not to damage on-chip RAM with overlapped settings. In addition to the erasing program area and programming program area, areas for the user procedure programs, work area, and stack area are allocated in the on-chip RAM. Do not make settings that will overwrite data in these areas. * Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ parameter must be performed for both the erasing program and programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes and (download start address for programming program) + 32 bytes. 21.4.3 User Boot Mode
This LSI has user boot mode that is initiated with different mode pin settings than those in boot mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) User Boot Mode Initiation
For the mode pin settings to start up user boot mode, see table 21.5. When the reset start is executed in user boot mode, the built-in check routine runs. The user MAT and user boot MAT states are checked by this check routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, H'AA is set to FMATS because the execution target MAT is the user boot MAT.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(2)
User MAT Programming in User Boot Mode
For programming the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after programming completes. Figure 21.14 shows the procedure for programming the user MAT in user boot mode.
Start programming procedure program
Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5
1
Set FMATS to value other than H'AA to select user MAT
MAT switchover
User-boot-MAT selection state
Download
Set SCO to 1 and execute download
Set FKEY to H'5A
User-MAT selection state
Clear FKEY to 0
DPFR = 0? Yes
Set parameter to ER0 and ER1 (FMPAR and FMPDR)
No
Programming
Programming JSR FTDAR setting + 16
FPFR = 0?
Download error processing
Initialization
Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32
FPFR = 0?
No Yes Clear FKEY and programming error processing*
No
Required data programming is completed?
Yes
No
Clear FKEY to 0
Yes Initialization error processing
Disable interrupts and bus master operation other than CPU
Set FMATS to H'AA to select user boot MAT
End programming procedure program
MAT switchover
1
User-boot-MAT selection state
Note: * The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT.
Figure 21.14 Procedure for Programming User MAT in User Boot Mode
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 21.14. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background. The user MAT and user boot MAT are switched only while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be executed in an area other than flash memory. After the programming procedure completes, switch the MATs again to return to the first state. MAT switching is enabled by writing a specific value to FMATS. Note however that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined. Perform MAT switching in accordance with the description in section 21.6, Switching between User MAT and User Boot MAT. Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 21.4.4, Storable Areas for Procedure Program and Program Data.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(3)
User MAT Erasing in User Boot Mode
For erasing the user MAT in user boot mode, additional processing made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes. Figure 21.15 shows the procedure for erasing the user MAT in user boot mode.
Start erasing procedure program
Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5
1
MAT switchover
Set FMATS to value other than H'AA to select user MAT
User-boot-MAT selection state
Download
Set SCO to 1 and execute download
Set FKEY to H'A5
User-MAT selection state
Clear FKEY to 0
Set FEBS parameter
Programming JSR FTDAR setting + 16
FPFR = 0?
DPFR = 0?
No
Yes
Download error processing
Erasing
Initialization
Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32
FPFR = 0?
Yes No
No Clear FKEY and erasing error processing*
Required block erasing is completed?
Yes
No
Clear FKEY to 0
Yes Initialization error processing
Disable interrupts and bus master operation other than CPU
Set FMATS to H'AA to select user boot MAT
End erasing procedure program
MAT switchover
1
User-boot-MAT selection state
Note: * The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT.
Figure 21.15 Procedure for Erasing User MAT in User Boot Mode
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 21.15. MAT switching is enabled by writing a specific value to FMATS. Note however that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined. Perform MAT switching in accordance with the description in section 21.6, Switching between User MAT and User Boot MAT. Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 21.4.4, Storable Areas for Procedure Program and Program Data. 21.4.4 Storable Areas for Procedure Program and Program Data
In the descriptions in the previous section, the storable areas for the programming/erasing procedure programs and program data are assumed to be in the on-chip RAM. However, the procedure programs and program data can be stored in and executed from other areas, such as part of flash memory which is not to be programmed or erased. (1) Conditions that Apply to Programming/Erasing
1. The on-chip programming/erasing program is downloaded from the address in the on-chip RAM specified by FTDAR, therefore, this area is not available for use. 2. The on-chip programming/erasing program will use 128 bytes at the maximum as a stack. So, make sure that this area is allocated. 3. Download by setting the SCO bit to 1 will lead to switching of the MATs. Therefore, if this operation is used, it should be executed from the on-chip RAM. 4. The flash memory is accessible until the start of programming or erasing, that is, until the result of downloading has been determined. The required procedure programs, NMI handling vector, and NMI handling routine should be transferred to the on-chip RAM before programming/erasing of the flash memory starts. 5. Since flash memory is not accessible during programming/erasing processing, programs downloaded to the on-chip RAM are executed. The procedure programs that initiate programming/erasing processing, and execution areas for the NMI interrupt vector table and NMI interrupt handling program must be stored in on-chip RAM.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
6. After programming/erasing, access to the flash memory is prohibited until FKEY is cleared. In case the LSI mode is changed to generate a reset on completion of a programming/erasing operation, a reset state (RES = 0) of 100 s or more must be secured. Transitions to the reset state or hardware standby mode are prohibited during programming/erasing operations. However, when the reset signal is accidentally input to the chip, the reset must be released after a reset period of 100 s that is longer than normal. 7. Switching of the MATs by FMATS should be required when programming/erasing of the user MAT is operated in user boot mode. The program that switches the MATs should be executed from the on-chip RAM. (For details, see section 21.6, Switching between User MAT and User Boot MAT.) Make sure you know which MAT is currently selected when switching them. 8. When the program data storable area indicated by the programming parameter FMPDR is in flash memory, an error will occur even when the program data stored is normal. Therefore, the program data should be temporarily transferred to the on-chip RAM to set an address other than flash memory in FMPDR. In consideration of these conditions, the following tables show areas where program data can be stored and executed for different combinations of operating mode, user MAT bank configuration, and processing type. Table 21.7 Executable MAT
Initiated Mode Processing Programming Erasing Note: * User Program Mode Table 21.8 (1) Table 21.8 (2) Programming/Erasing is possible to the user MAT. User Boot Mode* Table 21.8 (3) Table 21.8 (4)
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Table 21.8 (1)
Usable Area for Programming in User Program Mode
Storable/Executable Area Selected MAT Embedded Program Storage MAT
Item Storage area for program data Selecting on-chip program to be downloaded Writing H'A5 to FKEY Writing 1 to SCO in FCCS (download) FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling routine Disabling interrupts Writing H'5A to FKEY Setting programming parameter
On-chip RAM
User MAT x*
User MAT

x x x x

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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Storable/Executable Area
Selected MAT Embedded Program Storage MAT
Item Programming Determination of programming result Programming error processing FKEY clearing Note: *
On-chip RAM
User MAT x x x x
User MAT
Transferring the data to the on-chip RAM in advance enables this area to be used.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Table 21.8 (2)
Usable Area for Erasure in User Program Mode
Storable/Executable Area Selected MAT Embedded Program Storage MAT
Item Selecting on-chip program to be downloaded Writing H'A5 to FKEY Writing 1 to SCO in FCCS (download) FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling routine Disabling interrupts Writing H'5A to FKEY Setting erasure parameter Erasure Determination of erasure result Erasing error processing FKEY clearing
On-chip RAM
User MAT
User MAT

x x x x x x x x

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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Table 21.8 (3)
Usable Area for Programming in User Boot Mode
Storable/Executable Area On-chip RAM User Boot MAT x*1 Selected MAT User Boot User MAT MAT Embedded Program Storage MAT
Item Storage area for program data Selecting on-chip program to be downloaded Writing H'A5 to FKEY Writing 1 to SCO in FCCS (download) FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling routine Disabling interrupts Switching MATs by FMATS Writing H'5A to FKEY

x x x x x

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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Storable/Executable Area On-chip RAM User Boot MAT x x x x*2 x x
Selected MAT User Boot User MAT MAT Embedded Program Storage MAT
Item Setting programming parameter Programming Determination of programming result Programming error processing FKEY clearing Switching MATs by FMATS
Notes: 1. Transferring the data to the on-chip RAM in advance enables this area to be used. 2. Switching FMATS by a program in the on-chip RAM enables this area to be used.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Table 21.8 (4)
Usable Area for Erasure in User Boot Mode
Storable/Executable Area On-chip RAM User Boot MAT Selected MAT User Boot User MAT MAT Embedded Program Storage MAT
Item Selecting on-chip program to be downloaded Writing H'A5 to FKEY Writing 1 to SCO in FCCS (download) FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling routine Disabling interrupts Switching MATs by FMATS Writing H'5A to FKEY Setting erasure parameter

x x x x x x

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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Storable/Executable Area
Selected MAT Embedded Program Storage MAT
Item Erasure Determination of erasure result Erasing error processing FKEY clearing Switching MATs by FMATS Note: *
User Boot |On-chip RAM MAT x x x* x x
User MAT
User Boot MAT
Switching FMATS by a program in the on-chip RAM enables this area to be used.
21.5
Protection
There are two kinds of flash memory programming/erasing protection: hardware and software protection. 21.5.1 Hardware Protection
Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization are possible. However, even though a programming/erasing program is initiated, the user MAT cannot be programmed/erased, and a programming/erasing error is reported with the FPFR parameter.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Table 21.9 Hardware Protection
Function to be Protected Item Description Download Programming/ Erasure
FWE pin protection *
When a low-level signal is input to the FWE pin, the FWE bit in FCCS is cleared and the programming/erasing protection state is entered. The programming/erasing interface registers are initialized in the reset state (including a reset by the WDT) and hardware standby mode, and the programming/erasing protection state is entered. The reset state will not be entered by a reset using the RES pin unless the RES pin is held low until oscillation has stabilized after the power is supplied. In the case of a reset during operation, hold the RES pin low for the RES pulse width that is specified by the AC characteristics. If a reset is input during programming or erasure, values in the flash memory are not guaranteed. In this case, execute erasure and then execute programming again.
Reset, standby protection
*
*
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.5.2
Software Protection
Software protection is set up by disabling download of on-chip programming/erasing programs or by means of a key code. Table 21.10 Software Protection
Function to be Protected Item Protection by SCO bit Description * Download Programming/ Erasure
The programming/erasing protection state is entered by clearing the SCO bit in FCCS to 0 to disable downloading of the programming/erasing programs. Downloading and programming/erasing are disabled unless the required key code is written in FKEY. Different key codes are used for downloading and programming/erasing.
Protection by FKEY
*
21.5.3
Error Protection
Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer entering runaway during programming/erasing of the flash memory or operations that are not following the stipulated procedures for programming/erasing. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the error-protection state is entered, and this aborts the programming or erasure. The FLER bit is set to 1 in the following conditions: * When an interrupt such as NMI occurs during programming/erasing. * When the flash memory is read during programming/erasing (including a vector read or an instruction fetch). * When a SLEEP instruction (including software-standby mode) is executed during programming/erasing.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
* When a bus master other than the CPU, such as the DTC or LPC, gets the bus during programming/erasing Error protection is cancelled only by a reset or a transition to hardware-standby mode. Note that the reset should be released after a reset period of 100 s which is longer than normal. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error-protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. The state transition diagram in figure 21.16 shows transitions to and from the error-protection state.
Program mode Erase mode
RES = 0 or STBY = 0
or =0 ES Y = 0 RB ST
Reset or hardware standby mode (Hardware protection)
Read disabled Programming/erasing disabled FLER = 0
Read disabled Programming/erasing enabled E FLER = 0 (S rro oft r wa oc re cu sta rre nd d by ) Error occurred
RES = 0 or STBY = 0
Programming/erasing interface registers are in the initial state.
Error-protection state
Read enabled Programming/erasing disabled FLER = 1
Software standby mode
Error-protection state (Software standby)
Read disabled Programming/erasing disabled FLER = 1
Software-standby mode canceled
Programming/erasing interface registers are in the initial state.
Figure 21.16 Transitions to Error-Protection State
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.6
Switching between User MAT and User Boot MAT
It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because both of these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode.) 1. MAT switching by FMATS should always be executed from the on-chip RAM. 2. To ensure that switching has finished and access is made to the newly switched MAT, execute four NOP instructions in the same on-chip RAM immediately after writing to FMATS (this prevents access to the flash memory during MAT switching). 3. If an interrupt has occurred during switching, there is no guarantee of which memory MAT is being accessed. Always mask the maskable interrupts before switching between MATs. In addition, configure the system so that NMI interrupts do not occur during MAT switching. 4. After the MATs have been switched, take care because the interrupt vector table will also have been switched. If interrupt handling is to be the same before and after MAT switching, transfer the interrupt handling routines to the on-chip RAM and set the WEINTE bit in FCCS to place the interruptvector table in the on-chip RAM. 5. Memory sizes of the user MAT and user boot MAT are different. Do not access a user boot MAT in a space of 8 kbytes or more. If access goes beyond the 8-kbyte space, the values read are undefined.

Procedure for switching to user boot MAT Procedure for switching to user MAT Procedure for switching to user boot MAT: 1. Disable interrupts (mask). 2. Write H'AA to FMATS. 3. Execute four NOP instructions before accessing the user boot MAT. Procedure for switching to user MAT: 1. Disable interrupts (mask). 2. Write a value other than H'AA to FMATS. 3. Execute four NOP instructions before accessing the user MAT.
Figure 21.17 Switching between User MAT and User Boot MAT
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21.7
Programmer Mode
Along with its on-board programming mode, this LSI also has a programmer mode as another mode for programming/erasing of programs and data. In programmer mode, a general PROM programmer that supports Renesas microcomputers with 1-Mbyte flash memory as a device type*1 can be used to freely write programs to the on-chip ROM. Programming/erasing is possible on the user MAT and user boot MAT*2. Figure 21.18 shows a memory map in programmer mode. A status-polling system is adopted for operation in automatic programming, automatic erasure, and status-read modes. In status-read mode, details of the internal signals are output after execution of automatic programming or automatic erasure. In programmer mode, a 12-MHz clock signal must be input. Notes: 1. In this LSI, set the programming voltage of the PROM programmer to 3.3 V. 2. For the PROM programmer and the version of its program, see the instruction manuals for socket adapter.
MCU mode H'000000 This LSI Programmer mode H'00000
On-chip ROM area H'0FFFFF H'FFFFF
Figure 21.18 Memory Map in Programmer Mode
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21.8
Serial Communication Interface Specifications for Boot Mode
The boot program initiated in boot mode performs transmission and reception with the host PC via the on-chip SCI. The serial communication interface specifications for the host and boot program are shown below. (1) Status
The boot program has three states. 1. Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot mode enables starting of the boot program and transition to the bit-rate-adjustment state. The boot program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the boot program enters the inquiry/selection state. 2. Inquiry/Selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected in this state. After selection of these settings, the boot program makes a transition to the programming/erasing state by the command for a transition to the programming/erasing state. The boot program transfers the libraries required for erasure to the on-chip RAM and erases the user MATs and user boot MATs before the transition to the programming/erasing state. 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum check and blank check are executed by sending commands from the host. The boot program states are shown in figure 21.19.
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Reset
Bit-rate-adjustment state
Inquiry/response wait Transition to programming/erasing state
Inquiry Inquiry and selection processing
Response Response processing
Processing for erasing user MAT and user boot MAT
Programming/erasing response wait Programming Programming processing Erasing Erasing processing Checking
Check processing
Figure 21.19 Boot Program States
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(2)
Bit-Rate-Adjustment State
The bit rate is adjusted by measuring the period of a low-level byte (H'00) transmitted from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry/selection state. The bit-rate-adjustment sequence is shown in figure 21.20.
Host H'00 (30 times maximum)
Boot Program
Measuring the 1-bit length
H'00 (Completion of adjustment) H'55 H'E6 (Boot response) (H'FF (error))
Figure 21.20 Bit-Rate-Adjustment Sequence (3) Communications Protocol
After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. 1. 1-byte commands and 1-byte responses These commands and responses are comprised of a single byte. They are the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. They are selection commands and responses to inquiries. The size of program data is not included under this heading because it is determined in another command. 3. Error response This response is an error response to the commands. It is two bytes of data, and consists of an error response and an error code.
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4. Programming of 128 bytes The size is not specified in the commands. The data size is indicated in the response to the programming unit inquiry. 5. Memory read response This response consists of r4 bytes of data.
1-byte command or 1-byte response n-byte command or n-byte response
Command or response
Data Data size Command or response Checksum
Error response Error code Error response
128-byte programming
Address Command
Data (n bytes) Checksum
Memory read response
Data size Response
Data Checksum
Figure 21.21 Communication Protocol Format * * * * * * * * * * Command (1 byte): Commands for inquiries, selection, programming, erasing, and checking Response (1 byte): Response to an inquiry Size (1 byte): The amount of transfer data excluding the command, size, and checksum Data (n bytes): Detailed data of a command or response Checksum (1 byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. Error response (1 byte): Error response to a command Error code (1 byte): Type of the error Address (4 bytes): Address for programming Data (n bytes): Data to be programmed (n is indicated in the response to the programming unit inquiry.) Data size (4 bytes): Four-byte response to a memory read
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(4)
Inquiry/Selection State
The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Inquiry and selection commands are listed in table 21.11. Table 21.11 Inquiry and Selection Commands
Command H'20 H'10 H'21 H'11 H'22 Command Name Supported Device Inquiry Device Selection Clock Mode Inquiry Clock Mode Selection Division Ratio Inquiry Description Inquiry regarding device code and product name Selection of device code Inquiry regarding number of clock modes and values of each mode Indication of the selected clock mode Inquiry regarding the number of types of division ratios, and the number and values of each ratio type
H'23 H'24 H'25 H'26 H'27 H'3F H'40 H'4F
Operating Clock Frequency Inquiry Inquiry regarding the maximum and minimum values of the main clock and peripheral clock User Boot MAT Information Inquiry Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT User MAT Information Inquiry Erased Block Information Inquiry Programming Unit Inquiry New Bit Rate Selection Inquiry regarding the number of user MATs and the start and last addresses of each MAT Inquiry regarding the number of blocks and the start and last addresses of each block Inquiry regarding the size of program data Selection of the new bit rate
Transition to Programming/Erasing Erasure of user MAT and user boot MAT, and State transition to programming/erasing state Boot Program Status Inquiry Inquiry into the processing status of the boot program
The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be transmitted from the host in that order. These commands are needed in all cases. When two or more selection commands are transmitted at the same time, the last command will be valid.
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All of these commands, except for boot program status inquiry (H'4F), will be valid until the boot program receives the programming/erasing state transition command (H'40). The host can choose the needed commands out of the above commands and make inquiries. The boot program status inquiry command (H'4F) remains valid even after the boot program has received the programming/erasing state transition command (H'40). (a) Supported Device Inquiry
The boot program will return the device codes of the supported devices and the product names in response to the supported device inquiry command.
Command H'20
* Command, H'20 (1 byte): Inquiry regarding supported devices
Response H'30 Number of characters *** SUM Size Number of devices Product name
Device code
* Response, H'30 (1 byte): Response to the supported device inquiry * Size (1 byte): The number of bytes to be transferred, excluding the command, size, and checksum, that is, the total amount of data consisting the number of devices, the number of characters, device codes, and product names * Number of devices (1 byte): The number of device types supported by the boot program in the microcomputer * Number of characters (1 byte): The number of characters in the device codes and boot program's name * Device code (4 bytes): ASCII code of the supported product name * Product name (n bytes): ASCII code of the boot program type name * SUM (1 byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00.
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(b)
Device Selection
The boot program will set the specified supported device in response to the device selection command. The program will return information on the selected device in response to the inquiry after this setting has been made.
Command H'10 Size Device code SUM
* Command, H'10 (1 byte): Device selection * Size (1 byte): The number of characters in the device code. Fixed at 2. * Device code (4 bytes): Device code (ASCII code) returned in response to the supported device inquiry * SUM (1 byte): Checksum
Response H'06
* Response, H'06 (1 byte): Response to the device selection command. The boot program will return ACK when the device code matches.
Error Response H'90 ERROR
* Error response, H'90 (1 byte): Error response to the device selection command ERROR (1 byte): Error code H'11: Checksum error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry
The boot program will return the supported clock modes in response to the clock mode inquiry command.
Command H'21
* Command, H'21 (1 byte): Inquiry regarding clock mode
Response H'31 Size Number of modes Mode *** SUM
* Response, H'31 (1 byte): Response to the clock mode inquiry * Size (1 byte): Amount of data that represents the number of modes and modes * Number of clock modes (1 byte): The number of supported clock modes. H'00 indicates no clock mode or the device allows the clock mode to be read. * Mode (1 byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.) * SUM (1 byte): Checksum
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(d)
Clock Mode Selection
The boot program will set the specified clock mode in response to the clock mode selection command. The program will return information on the selected clock mode in response to the inquiry after this setting has been made. The clock mode selection command should be sent after the device selection command.
Command H'11 Size Mode SUM
* * * *
Command, H'11 (1 byte): Selection of clock mode Size (1 byte): The number of characters that represents the modes. Fixed at 1. Mode (1 byte): A clock mode returned in response to the clock mode inquiry. SUM (1 byte): Checksum
H'06
Response
* Response, H'06 (1 byte): Response to the clock mode selection command. The boot program will return ACK when the clock mode matches.
Error Response H'91 ERROR
* Error response, H'91 (1 byte) : Error response to the clock mode selection command * ERROR (1 byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match Even if the number of clock modes is H'00 or H'01 by a clock mode inquiry, the clock mode must be selected using the respective value.
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(e)
Division Ratio Inquiry
The boot program will return the supported division ratios in response to the division ratio inquiry command.
Command H'22
* Command, H'22 (1 byte): Inquiry regarding division ratio
Response H'32 Number of division ratios *** SUM Size Division ratio Number of types ***
* Response, H'32 (1 byte): Response to the division ratio inquiry * Size (1 byte): The amount of data that represents the number of types, number of division ratios, and division ratios * Number of types (1 byte): The number of supported division ratio types (e.g. H'02 when there are two types: main operating frequency and peripheral module operating frequency) * Number of division ratios (1 byte): The number of supported division ratios for each operating frequency. The number of division ratios supported in the main module and peripheral modules. * Division ratio (1 byte) Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value will be H'FE[-2]) The number of division ratios returned is the same as the number of division ratios and as many groups of data are returned as there are types. * SUM (1 byte): Checksum
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(f)
Operating Clock Frequency Inquiry
The boot program will return the number of operating clock frequencies, and the maximum and minimum values in response to the operating clock frequency inquiry command.
Command H'23
* Command, H'23 (1 byte): Inquiry regarding operating clock frequencies
Response H'33 Size Number of operating clock frequencies
Minimum value of operating Maximum value of operating clock clock frequency frequency *** SUM
* Response, H'33 (1 byte): Response to operating clock frequency inquiry * Size (1 byte): The amount of data that represents the number of operating clock frequencies, and the minimum and maximum values of the operating clock frequencies * Number of operating clock frequencies (1 byte): The number of supported operating clock frequency types (e.g. H'02 when there are two types: main operating frequency and peripheral module operating frequency) * Minimum value of operating clock frequency (2 bytes): Minimum value among the divided clock frequencies. The minimum and maximum values of operating clock frequency represent the frequency values (MHz), valid to the hundredths place, and multiplied by 100. (e.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0) * Maximum value of operating clock frequency (2 bytes): Maximum value among the divided clock frequencies. There are as many pairs of minimum and maximum values as there are operating clock frequencies. * SUM (1 byte): Checksum
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(g)
User Boot MAT Information Inquiry
The boot program will return the number of user boot MATs and their addresses in response to the user boot MAT information inquiry command.
Command H'24
* Command, H'24 (1 byte): Inquiry regarding user boot MAT information
Response H'34 Size Number of areas Area last address
Area start address *** SUM
* Response, H'34 (1 byte): Response to user boot MAT information inquiry * Size (1 byte): The amount of data that represents the number of areas, area start address, and area last address * Number of areas (1 byte): The number of consecutive user boot MAT areas. H'01 when the user boot MAT areas are consecutive. * Area start address (4 bytes): Start address of the area * Area last address (4 bytes): Last address of the area. There are as many groups of data representing the start and last addresses as there are areas. * SUM (1 byte): Checksum (h) User MAT Information Inquiry
The boot program will return the number of user MATs and their addresses in response to the user MAT information inquiry command.
Command H'25
* Command, H'25 (1 byte): Inquiry regarding user MAT information
Response H'35 Size Number of areas Area last address
Area start address *** SUM
* Response, H'35 (1 byte): Response to the user MAT information inquiry * Size (1 byte): The amount of data that represents the number of areas, area start address, and area last address * Number of areas (1 byte): The number of consecutive user MAT areas. H'01 when the user MAT areas are consecutive.
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* Area start address (4 bytes): Start address of the area * Area last address (4 bytes): Last address of the area. There are as many groups of data representing the start and last addresses as there are areas. * SUM (1 byte): Checksum (i) Erased Block Information Inquiry
The boot program will return the number of erased blocks and their addresses in response to the erased block information inquiry command.
Command H'26
* Command, H'26 (1 byte): Inquiry regarding erased block information
Response H'36 Size Number of blocks Block last address
Block start address *** SUM
* Response, H'36 (1 byte): Response to the erased block information inquiry * Size (2 bytes): The amount of data that represents the number of blocks, block start address, and block last address. * Number of blocks (1 byte): The number of erased blocks of flash memory * Block start address (4 bytes): Start address of a block * Block last address (4 bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are blocks. * SUM (1 byte): Checksum (j) Programming Unit Inquiry
The boot program will return the programming unit used to program data in response to the programming unit inquiry command.
Command H'27
* Command, H'27 (1 byte): Inquiry regarding programming unit
Response H'37 Size Programming unit SUM
* Response, H'37 (1 byte): Response to programming unit inquiry * Size (1 byte): The number of characters that indicate the programming unit. Fixed at 2. * Programming unit (2 bytes): A unit for programming. This is the unit for reception of program data.
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* SUM (1 byte): Checksum (k) New Bit Rate Selection
The boot program will set a new bit rate in response to the new bit rate selection command, and return the new bit rate in response to the confirmation. This new bit rate selection command should be sent after sending the clock mode selection command.
Command H'3F Number of division ratios SUM Size Bit rate Input frequency
Division ratio 1 Division ratio 2
* Command, H'3F (1 byte): Selection of new bit rate * Size (1 byte): The amount of data that represents the bit rate, input frequency, number of division ratios, and division ratios * Bit rate (2 bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is H'00C0.) * Input frequency (2 bytes): Frequency of the clock input to the boot program. This is valid to the hundredths place and represents the frequency value (MHz) multiplied by 100. (e.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0) * Number of division ratios (1 byte): The number of supported division ratios. Normally the number is two: one for the main operating frequency and one for peripheral module operating frequency. * Division ratio 1 (1 byte): The division ratio for the main operating frequency Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value will be H'FE[-2]) * Division ratio 2 (1 byte): The division ratio for the peripheral module operating frequency Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value will be H'FE[-2]) * SUM (1 byte): Checksum
Response H'06
* Response, H'06 (1 byte): Response to selection of a new bit rate. The boot program will return ACK when the new bit rate can be set.
Error Response H'BF ERROR
* Error response, H'BF (1 byte): Error response to selection of a new bit rate
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* ERROR (1 byte): Error code H'11: Checksum error H'24: Bit rate selection error The rate is not available. H'25: Input frequency error The input frequency is not within the specified range. H'26: Division ratio error The division ratio does not match an available ratio. H'27: Operating frequency error The operating frequency is not within the specified range. (5) Receive Data Check
The methods for checking received data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of the minimum to maximum frequencies which are available with the clock modes of the specified device. When the value is out of this range, an input frequency error is generated. 2. Division ratio The received value of the division ratio is checked to ensure that it matches the division for the clock modes of the specified device. When the value is out of this range, a division ratio error is generated. 3. Operating frequency Operating frequency is calculated from the received value of the input frequency and the division ratio. The input frequency is the frequency input to the LSI, and the operating frequency is the frequency at which the LSI is actually operated. The formula is given below. Operating frequency = Input frequency / Division ratio The calculated operating frequency should be checked to ensure that it is within the range of the minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. 4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency () and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate selection error is generated. The error is calculated using the following formula:
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Error (%) = {[
x 106 (N + 1) x B x 64 x 2(2xn - 1)
] - 1} x 100
When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate.
Confirmation H'06
* Confirmation, H'06 (1 byte): Confirmation of a new bit rate
Response H'06
* Response, H'06 (1 byte): Response to confirmation of a new bit rate The sequence of new bit rate selection is shown in figure 21.22.
Host Setting a new bit rate Waiting for one-bit period at the specified bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate H'06 (ACK)
Boot program
Setting a new bit rate
Figure 21.22 Sequence of New Bit Rate Selection (6) Transition to Programming/Erasing State
The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order in response to the transition to the programming/erasing state command. On completion of this erasure, ACK will be returned and a transition made to the programming/erasing state. Before sending the programming selection command or program data, the host should select the LSI device with the device selection command, the clock mode with the clock mode selection command, and the new bit rate with the new bit rate selection command, and then send the transition to programming/erasing state command.
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Command
H'40
* Command, H'40 (1 byte): Transition to programming/erasing state
Response H'06
* Response, H'06 (1 byte): Response to transition to programming/erasing state. The boot program will return ACK when the user MAT and user boot MAT have been erased normally by the transferred erasing program.
Error Response H'C0 H'51
* Error response, H'C0 (1 byte): Error response to blank check of user boot MAT * Error code, H'51 (1 byte): Erasing error An error occurred and erasure was not completed. (7) Command Error
A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock mode selection command before a device selection command, or an inquiry command after the transition to programming/erasing state command, are such examples.
Error Response H'80 H'xx
* Error response, H'80 (1 byte): Command error * Command, H'xx (1 byte): Received command (8) Command Order
The order for commands in the inquiry/selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device selection (H'10) command. 3. A clock mode inquiry (H'21) should be made to inquire about the supported clock modes. 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the division ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit rate selection. 6. A new bit rate should be selected with the new bit rate selection (H'3F) command, according to the returned information on division ratios and operating frequencies.
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7. After selection of the device and clock mode, programming/erasing information of the user boot MAT and user MAT should be inquired using the user boot MAT information inquiry (H'24), user MAT information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27). 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state. (9) Programming/Erasing State
In the programming/erasing state, a programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/erasing commands are listed in table 21.12. Table 21.12 Programming/Erasing Commands
Command H'42 H'43 H'50 H'48 H'58 H'52 H'4A H'4B H'4C H'4D H'4F Command Name Description
User boot MAT programming selection Transfers the user boot MAT programming program User MAT programming selection 128-byte programming Erasing selection Block erasing Memory read User boot MAT sum check User MAT sum check User boot MAT blank check User MAT blank check Boot program status inquiry Transfers the user MAT programming program Programs 128 bytes of data Transfers the erasing program Erases a block of data Reads the contents of memory Checks the sum of the user boot MAT Checks the sum of the user MAT Checks whether the contents of the user boot MAT are blank Checks whether the contents of the user MAT are blank Inquires into the boot program's processing status
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Programming: Programming is executed by a programming-selection command and a 128-byte programming command. First, the host should send the programming-selection command, and select the programming method and programming MATs. There are two programming selection commands according to the area and method for programming. 1. User boot MAT programming selection 2. User MAT programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the program data according to the method specified by the selection command. When more than 128 bytes of data are to be programmed, 128-byte programming commands should be executed repeatedly. Sending from the host a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. In case of continuing programming with another method or programming of another MAT, the procedure must be repeated from the programming selection command. The sequence for the programming selection and 128-byte programming commands is shown in figure 21.23.
Host Programming selection (H'42, H'43)
Boot program
Transfer of the programming program
ACK 128-byte programming (address, data) Programming ACK 128-byte programming (H'FFFFFFFF) ACK
Repeat
Figure 21.23 Programming Sequence
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(a)
User Boot MAT Programming Selection
The boot program will transfer a programming program in response to the user boot MAT programming selection command. The data is programmed to the user boot MAT by the transferred programming program.
Command H'42
* Command, H'42 (1 byte): User boot MAT programming selection
Response H'06
* Response, H'06 (1 byte): Response to user boot MAT programming selection. When the programming program has been transferred, the boot program will return ACK.
Error Response H'C2 ERROR
* Error response, H'C2 (1 byte): Error response to user boot MAT programming selection * ERROR (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) User MAT Programming Selection: The boot program will transfer a programming program in response to the user MAT programming selection command. The data is programmed to the user MAT by the transferred programming program.
Command H'43
* Command, H'43 (1 byte): User MAT programming selection
Response H'06
* Response, H'06 (1 byte): Response to user MAT programming selection. When the programming program has been transferred, the boot program will return ACK.
Error Response H'C3 ERROR
* Error response, H'C3 (1 byte): Error response to user MAT programming selection * ERROR (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) 128-Byte Programming
The boot program will use the programming program transferred by the programming selection command for programming the user boot MAT or user MAT in response to the 128-byte programming command.
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Command
H'50 Data *** SUM
Address ***
* Command, H'50 (1 byte): 128-byte programming * Programming address (4 bytes): Start address for programming. Multiple of the size specified in response to the programming unit inquiry command. (e.g. H'00, H'01, H'00, H'00: H'010000) * Program data (128 bytes): Data to be programmed. The size is specified in response to the programming unit inquiry command. * SUM (1 byte): Checksum
Response H'06
* Response, H'06 (1 byte): Response to 128-byte programming. On completion of programming, the boot program will return ACK.
Error Response H'D0 ERROR
* Error response, H'D0 (1 byte): Error response to 128-byte programming * ERROR (1 byte): Error code H'11: Checksum Error H'2A: Address error H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the boundary of the programming unit. For example, when the programming unit is 128 bytes, the lower eight bits of the address should be H'00 or H'80. When the program data is less than 128 bytes, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of programming and wait for selection of programming or erasing.
Command H'50 Address SUM
* Command, H'50 (1 byte): 128-byte programming * Programming address (4 bytes): End code (H'FF, H'FF, H'FF, H'FF) * SUM (1 byte): Checksum
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Response
H'06
* Response, H'06 (one byte): Response to 128-byte programming. On completion of programming, the boot program will return ACK.
Error Response H'D0 ERROR
* Error response, H'D0 (1 byte): Error response to 128-byte programming * ERROR (1 byte): Error code H'11: Checksum error H'2A: Address error H'53: Programming error An error has occurred in programming and programming cannot be continued. (10) Erasure Erasure is performed with the erasure selection and block erasure commands. First, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasure command from the host with the block number H'FF will stop the erasure processing. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequence for the erasure selection command and block erasure command is shown in figure 21.24.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Host Preparation for erasure (H'48)
Boot program
Transfer of erasure program ACK Erasure (Erase-block number) ACK Erasure (H'FF) ACK
Repeat
Erasure
Figure 21.24 Erasure Sequence (a) Erasure Selection
The boot program will transfer the erasing program in response to the erasure selection command. User MAT data is erased by the transferred erasing program.
Command H'48
* Command, H'48 (1 byte): Erasure selection
Response H'06
* Response, H'06 (1 byte): Response to erasure selection. After the erasing program has been transferred, the boot program will return ACK.
Error Response H'C8 ERROR
* Error response, H'C8 (1 byte): Error response to erasure selection * ERROR (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) Block Erasure
The boot program will erase the contents of the specified block in response to the block erasure command.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Command
H'58
Size
Block number
SUM
* Command, H'58 (1 byte): Erasure * Size (1 byte): The number of characters that represents the erase-block number. Fixed at 1. * Block number (1 byte): Number of the block to be erased * SUM (1 byte): Checksum
Response H'06
* Response, H'06 (1 byte): Response to erasure On completion of erasure, the boot program will return ACK.
Error Response H'D8 ERROR
* Error response, H'D8 (1 byte): Response to erasure * ERROR (1 byte): Error code H'11: Checksum error H'29: Block number error Block number is incorrect. H'51: Erasing error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command.
Command H'58 Size Block number SUM
* Command, H'58 (1 byte): Erasure * Size (1 byte): The number of characters that represents the block number. Fixed at 1. * Block number (1 byte): H'FF Stop code for erasure * SUM (1 byte): Checksum
Response H'06
* Response, H'06 (1 byte): Response to end of erasure (ACK will be returned) When erasure is to be performed again after the block number H'FF has been sent, the procedure should be executed from the erasure selection command.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
(11) Memory Read The boot program will return the data in the specified address in response to the memory read command.
Command H'52 Size Area Read address SUM
Read size
* Command, H'52 (1 byte): Memory read * Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) * Area (one byte) H'00: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect. * Read address (4 bytes): Start address to be read from * Read size (4 bytes): Size of data to be read * SUM (1 byte): Checksum
Response H'52 Data SUM Read size ***
* * * *
Response: H'52 (1 byte): Response to memory read Read size (4 bytes): Size of data to be read Data (n bytes): Data of the read size from the read address SUM (1 byte): Checksum
H'D2 ERROR
Error Response
* Error response: H'D2 (1 byte): Error response to memory read * ERROR (1 byte): Error code H'11: Checksum error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. (12) User Boot MAT Sum Check The boot program will return the total amount of bytes of the user boot MAT contents in response to the user boot MAT sum check command.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Command
H'4A
* Command, H'4A (1 byte): Sum check for user boot MAT
Response H'5A Size Checksum of MAT SUM
* Response, H'5A (1 byte): Response to the checksum of user boot MAT * Size (1 byte): The number of characters that represents the checksum. Fixed at 4. * Checksum of MAT (4 bytes): Checksum of user boot MATs. The total amount of data is obtained in byte units. * SUM (1 byte): Checksum (for transmit data) (13) User MAT Sum Check The boot program will return the total amount of bytes of the user MAT contents in response to the user MAT sum check command.
Command H'4B
* Command, H'4B (1 byte): Checksum for user MAT
Response H'5B Size Checksum of MAT SUM
* Response, H'5B (1 byte): Response to the checksum of the user MAT * Size (1 byte): The number of characters that represents the checksum. Fixed at 4. * Checksum of MAT (4 bytes): Checksum of user MATs. The total amount of data is obtained in byte units. * SUM (1 byte): Checksum (for transmit data) (14) User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result in response to the user boot MAT blank check command.
Command H'4C
* Command, H'4C (1 byte): Blank check for user boot MATs
Response H'06
* Response, H'06 (1 byte): Response to blank check of user boot MATs. If all user boot MATs are blank (H'FF), the boot program will return ACK.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Error Response
H'CC
H'52
* Error response, H'CC (1 byte): Error response to blank check for user boot MATs * Error code, H'52 (1 byte): Erasure incomplete error (15) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result in response to the user MAT blank check command.
Command H'4D
* Command, H'4D (1 byte): Blank check for user MATs
Response H'06
* Response, H'06 (1 byte): Response to blank check for user MATs. If all user MATs are blank (H'FF), the boot program will return ACK.
Error Response H'CD H'52
* Error response, H'CD (1 byte): Error response to blank check for user MATs * Error code, H'52 (1 byte): Erasure incomplete error (16) Boot Program State Inquiry The boot program will return indications of its present state and error condition in response to the boot program state inquiry command. This inquiry can be made in either the inquiry/selection state or the programming/erasing state.
Command H'4F
* Command, H'4F (1 byte): Inquiry regarding boot program's state
Response H'5F Size Status ERROR SUM
* * * *
Response, H'5F (1 byte): Response to boot program state inquiry Size (1 byte): The number of characters. Fixed at 2. Status (1 byte): State of the standard boot program ERROR (1 byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. * SUM (1 byte): Checksum
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
Table 21.13 Status Code
Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F Description Device Selection Wait Clock Mode Selection Wait Bit Rate Selection Wait Programming/Erasing State Transition Wait (Bit rate selection is completed) Programming/Erasing State Programming/Erasing Selection Wait (Erasure is completed) Program Data Receive Wait (Programming is completed) Erase Block Specification Wait (Erasure is completed)
Table 21.14 Error Code
Code H'00 H'11 H'12 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Description No Error Checksum Error Program Size Error Device Code Mismatch Error Clock Mode Mismatch Error Bit Rate Selection Error Input Frequency Error Division Ratio Error Operating Frequency Error Block Number Error Address Error Data Length Error Erasing Error Erasure Incomplete Error Programming Error Selection Processing Error Command Error Bit-Rate-Adjustment Confirmation Error
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
21.9
Usage Notes
1. The initial state of a Renesas product at shipment is the erased state. For a product whose history of erasing is undefined, automatic erasure for checking the initial state (erased state) and compensating is recommended. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3. If the socket, socket adapter, or product index of the PROM programmer does not match the specifications, too much current flows and the product may be damaged. 4. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a PROM programmer that supports a programming voltage of 3.3 V for Renesas microcomputers with 1-Mbyte flash memory. Do not set the programmer to HN28F101 or a programming voltage of 5.0 V. Use only the specified socket adapter. If other adapters are used, the product may be damaged. 5. Do not remove the chip from the PROM programmer nor input a reset signal during programming/erasing. As a high voltage is applied to the flash memory during programming/erasing, doing so may damage flash memory permanently. If a reset is input accidentally, the reset must be released after a reset period of 100 s which is longer than normal. 6. After programming/erasing, access to the flash memory is prohibited until FKEY is cleared. In case the LSI mode is changed to generate a reset on completion of a programming/erasing operation, a reset state (RES = 0) of 100 s or more must be secured. Transitions to the reset state or hardware standby mode are prohibited during programming/erasing operations. However, when the reset signal is accidentally input to the chip, the reset must be released after a reset period of 100 s that is longer than normal. 7. At turning on or off the VCC power supply, fix the RES pin to low and set the flash memory to the hardware protection state. This power-on or power-off timing must also be satisfied at a power-off or power-on caused by a power failure and other factors. 8. Perform programming to a 128-byte programming-unit block only once in on-board programming or programmer mode. Perform programming in the state where the programming-unit block is fully erased. 9. When a chip is to be reprogrammed with the programmer after it has already been programmed or erased in on-board programming mode, automatic programming is recommended to be performed after automatic erasure. 10. To write data or programs to the flash memory, program data and programs must be allocated to addresses higher than that of the external interrupt vector table (in normal mode: H'0020, in advanced mode: H'000040), and H'FF must be written to the areas that are reserved for the system in the exception handling vector table.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
11. If data other than H'FF (4 bytes) is written to the key code area (in normal mode: H'001E to H'001F, in advance mode: H'00003C to H'00003F) of flash memory, reading cannot be performed in programmer mode. (In this case, data is read as H'00. Rewrite is possible after erasing the data.) For reading in programmer mode, make sure to write H'FF to the entire key code area. If data other than H'FF is to be written to the key code area in programmer mode, a verification error will occur unless a software countermeasure is taken for the PROM programmer and version of program. 12. The code size of the programming program that includes the initialization routine or the erasing program that includes the initialization routine is 2 kbytes or less. Accordingly, when the CPU clock frequency is 20 MHz, the download for each program takes approximately 200 s at the maximum. 13. While an instruction in the on-chip RAM is being executed, the DTC can write to the SCO bit in FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure that these registers are not accidentally written to, otherwise an on-chip program may be downloaded and damage the on-chip RAM or a MAT switchover may occur and the CPU get out of control. Do not use the DTC to write to flash memory related registers. 14. A programming/erasing program for flash memory used in the conventional H8S F-ZTAT microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of flash memory in this H8S F-ZTAT microcomputer. 15. Unlike the conventional H8S F-ZTAT microcomputer, no countermeasures are available for a runaway by the WDT during programming/erasing. Prepare countermeasures (e.g. use of periodic timer interrupts) for the WDT with taking the programming/erasing time into consideration as required.
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Section 21 Flash Memory (0.18-m F-ZTAT Version)
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Section 22 Boundary Scan (JTAG)
Section 22 Boundary Scan (JTAG)
The JTAG (Joint Test Action Group) is standardized as an international standard, IEEE Standard 1149.1, and is open to the public as IEEE Standard Test Access Port and Boundary-Scan Architecture. Although the name of the function is boundary scan and the name of the group who worked on standardization is the JTAG, the JTAG is commonly used as the name of a boundary scan architecture and a serial interface to access the devices having the architecture. This LSI has a boundary scan function (JTAG). Using this function along with other LSIs facilitates testing a printed-circuit board.
22.1
Features
* Five test pins (ETCK, ETDI, ETDO, ETMS, and ETRST) * TAP controller * Six instructions BYPASS mode EXTEST mode SAMPLE/PRELOAD mode CLAMP mode HIGHZ mode IDCODE mode (These instructions are test modes corresponding to IEEE 1149.1.)
HUDS000A_000020020300
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Section 22 Boundary Scan (JTAG)
ETCK
ETMS TAP controller ETRST Decoder
ETDI
SDIR
Shift register SDBPR SDBSR
SDIDR
ETDO Mux
[Legend] SDIR: Instruction register SDBPR: Bypass register SDBSR: Boundary scan register SDIDR: ID code register
Figure 22.1 JTAG Block Diagram
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Section 22 Boundary Scan (JTAG)
22.2
Input/Output Pins
Table 22.1 shows the JTAG pin configuration. Table 22.1 Pin Configuration
Pin Name Test clock Abbreviation ETCK I/O Input Function Test clock input Provides an independent clock supply to the JTAG. As the clock input to the ETCK pin is supplied directly to the JTAG, a clock waveform with a duty cycle close to 50% should be input. For details, see section 26, Electrical Characteristics. If there is no input, the ETCK pin is fixed to 1 by an internal pull-up. Test mode select ETMS Input Test mode select input Sampled on the rise of the ETCK pin. The ETMS pin controls the internal state of the TAP controller. If there is no input, the ETMS pin is fixed to 1 by an internal pull-up. Test data input ETDI Input Serial data input Performs serial input of instructions and data for JTAG registers. ETDI is sampled on the rise of the ETCK pin. If there is no input, the ETDI pin is fixed to 1 by an internal pull-up. Test data output ETDO Output Serial data output Performs serial output of instructions and data from JTAG registers. Transfer is performed in synchronization with the ETCK pin. If there is no output, the ETDO pin goes to the highimpedance state. Test reset ETRST Input Test reset input signal Initializes the JTAG asynchronously. If there is no input, the ETRST pin is fixed to 1 by an internal pull-up.
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Section 22 Boundary Scan (JTAG)
22.3
Register Descriptions
The JTAG has the following registers. * * * * Instruction register (SDIR) Bypass register (SDBPR) Boundary scan register (SDBSR) ID code register (SDIDR)
Instructions can be input to the instruction register (SDIR) by serial transfer from the test data input pin (ETDI). Data from SDIR can be output via the test data output pin (ETDO). The bypass register (SDBPR) is a 1-bit register to which the ETDI and ETDO pins are connected in BYPASS, CLAMP, or HIGHZ mode. The boundary scan register (SDBSR) is a 334-bit register to which the ETDI and ETDO pins are connected in SAMPLE/PRELOAD or EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a fixed code can be output via the ETDO pin in IDCODE mode. All registers cannot be accessed directly by the CPU. Table 22.2 shows the kinds of serial transfer possible with each JTAG register. Table 22.2 JTAG Register Serial Transfer
Register SDIR SDBPR SDBSR SDIDR Serial Input Possible Possible Possible Impossible Serial Output Possible Possible Possible Possible
22.3.1
Instruction Register (SDIR)
SDIR is a 32-bit read-only register. JTAG instructions can be transferred to SDIR by serial input from the ETDI pin. SDIR can be initialized when the ETRST pin is low or the TAP controller is in the Test-Logic-Reset state, but is not initialized by a reset or in standby mode. Only 4-bit instructions can be transferred to SDIR. If an instruction exceeding 4 bits is input, the last 4 bits of the serial data will be stored in SDIR.
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Section 22 Boundary Scan (JTAG)
Bit 31 30 29 28
Bit Name TS3 TS2 TS1 TS0
Initial Value 1 1 1 0
R/W R R R R
Description Test Set Bits 0000: EXTEST mode 0001: Setting prohibited 0010: CLAMP mode 0011: HIGHZ mode 0100: SAMPLE/PRELOAD mode 0101: Setting prohibited : : 1101: Setting prohibited 1110: IDCODE mode (Initial value) 1111: BYPASS mode
27 to 14
All 0
R
Reserved These bits are always read as 0 and cannot be modified.
13 12 11 10 9, 8

1 0 1 0 All 1
R R R R R
Reserved This bit is always read as 1 and cannot be modified. Reserved This bit is always read as 0 and cannot be modified. Reserved This bit is always read as 1 and cannot be modified. Reserved This bit is always read as 0 and cannot be modified. Reserved These bits are always read as 1 and cannot be modified.
7 to 1
All 0
R
Reserved These bits are always read as 0 and cannot be modified.
0
1
R
Reserved This bit is always read as 1 and cannot be modified.
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Section 22 Boundary Scan (JTAG)
22.3.2
Bypass Register (SDBPR)
SDBPR is a 1-bit shift register. In BYPASS, CLAMP, or HIGHZ mode, SDBPR is connected between the ETDI and ETDO pins. 22.3.3 Boundary Scan Register (SDBSR)
SDBSR is a shift register provided on the PAD for controlling the I/O terminals of this LSI. Using EXTEST mode or SAMPLE/PRELOAD mode, a boundary scan test conforming to the IEEE1149.1 standard can be performed. Table 22.3 shows the relationship between the terminals of this LSI and the boundary scan register. Table 22.3 Correspondence between Pins and Boundary Scan Register
Pin No. Pin Name Input/Output from ETDI 2 P43 Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Input 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 Bit No.
3
P44
4
P45
5
P46
6
P47
9
MD1
10
MD0
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Section 22 Boundary Scan (JTAG)
Pin No. 11
Pin Name NMI
Input/Output Input Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input
Bit No. 316 315 314 313 312 311 310 319 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282
14
P52
15
P51
16
P50
17
P97
18
P96
19
P95
20
P94
21
P93
22
P92
23
P91
24
P90
25
MD2
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Section 22 Boundary Scan (JTAG)
Pin No. 26
Pin Name FWE
Input/Output Input Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output
Bit No. 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245
32
PE0
33
PA7
34
PA6
35
PA5
37
PA4
38
PA3
39
PA2
40
PA1
41
PA0
43
PF7
44
PF6
45
PF5
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Section 22 Boundary Scan (JTAG)
Pin No. 46
Pin Name PF4
Input/Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output
Bit No. 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206
47
PF3
48
PF2
49
PF1
50
PF0
51
PG7
52
PG6
53
PG5
54
PG4
55
PG3
56
PG2
57
PG1
58
PG0
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Section 22 Boundary Scan (JTAG)
Pin No. 59
Pin Name PD7
Input/Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Input Input Input Input
Bit No. 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177
60
PD6
61
PD5
62
PD4
63
PD3
64
PD2
65
PD1
66
PD0
68
P70
69
P71
70
P72
71
P73
72
P74
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Section 22 Boundary Scan (JTAG)
Pin No. 73
Pin Name P75
Input/Output Input Input Input Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output
Bit No. 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144
74
P76
75
P77
78
P60
79
P61
80
P62
81
P63
82
P64
83
P65
84
P66
85
P67
87
PC7
88
PC6
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Section 22 Boundary Scan (JTAG)
Pin No. 9+
Pin Name PC5
Input/Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output
Bit No. 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
90
PC4
91
PC3
92
PC2
93
PC1
94
PC0
96
P27
97
P26
98
P25
99
P24
100
P23
101
P22
102
P21
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Section 22 Boundary Scan (JTAG)
Pin No. 103
Pin Name P20
Input/Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output
Bit No. 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
104
P17
105
P16
106
P15
107
P14
108
P13
109
P12
110
P11
112
P10
113
PB7
114
PB6
115
PB5
116
PB4
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Section 22 Boundary Scan (JTAG)
Pin No. 117
Pin Name PB3
Input/Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output
Bit No. 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
118
PB2
119
PB1
120
PB0
121
P30
122
P31
123
P32
124
P33
125
P34
126
P35
127
P36
128
P37
129
P80
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Section 22 Boundary Scan (JTAG)
Pin No. 130
Pin Name P81
Input/Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output Input Enable Output To ETDO
Bit No. 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
131
P82
132
P83
133
P84
134
P85
135
P86
136
P40
137
P41
138
P42
Note: The enable signals are active-high. When an enable signal is driven high, the corresponding pin is driven with the output value.
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Section 22 Boundary Scan (JTAG)
22.3.4
ID Code Register (SDIDR)
SDIDR is a 32-bit register. In IDCODE mode, SDIDR can output H'0036200F, which is a fixed code, from ETDO. However, no serial data can be written to SDIDR via ETDI.
31 28 0000 Version (4 bits) 27 0000 0011 0010 12 0010 11 0000 0000 1 111 0 1 Fixed Code (1 bit)
Part Number (16 bits)
Manufacture Identify (11 bits)
22.4
22.4.1
Operation
TAP Controller State Transitions
Figure 22.2 shows the internal states of the TAP controller. State transitions basically conform to the IEEE1149.1 standard.
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Section 22 Boundary Scan (JTAG)
1
Test-logic-reset 0 1 Select-DR-scan 0 1 Select-IR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 1 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0 1 1
0
Run-test/idle
0
0
Figure 22.2 TAP Controller State Transitions 22.4.2 JTAG Reset
The JTAG can be reset in two ways. * The JTAG is reset when the ETRST pin is held at 0. * When ETRST = 1, the JTAG can be reset by inputting at least five ETCK clock cycles while ETMS = 1.
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Section 22 Boundary Scan (JTAG)
22.5
Boundary Scan
The JTAG pins can be placed in the boundary scan mode stipulated by the IEEE1149.1 standard by setting a command in SDIR. 22.5.1 Supported Instructions
This LSI supports the three essential instructions defined in the IEEE1149.1 standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and optional instructions (CLAMP, HIGHZ, and IDCODE). (1) BYPASS
Instruction code: B'1111 The BYPASS instruction is an instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is being executed, the test circuit has no effect on the system circuits. (2) SAMPLE/PRELOAD
Instruction code: B'0100 The SAMPLE/PRELOAD instruction inputs values from this LSI internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is being executed, this LSI's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. This LSI system circuits are not affected by execution of this instruction. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching does not affect normal operation of this LSI. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin).
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Section 22 Boundary Scan (JTAG)
(3)
EXTEST
Instruction code: B'0000 The EXTEST instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned in when test data (N-1) is scanned out. Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). (4) CLAMP
Instruction code: B'0010 When the CLAMP instruction is enabled, the output pin outputs the value of the boundary scan register that has been previously set by the SAMPLE/PRELOAD instruction. While the CLAMP instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between the ETDI and ETDO pins. The related circuit operates in the same way when the BYPASS instruction is enabled. (5) HIGHZ
Instruction code: B'0011 When the HIGHZ instruction is enabled, all output pins enter a high-impedance state. While the HIGHZ instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between the ETDI and ETDO pins. The related circuit operates in the same way when the BYPASS instruction is enabled.
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Section 22 Boundary Scan (JTAG)
(6)
IDCODE
Instruction code: B'1110 When the IDCODE instruction is enabled, the value of the ID code register is output from the ETDO pin with LSB first when the TAP controller is in the Shift-DR state. While the IDCODE instruction is being executed, the test circuit does not affect the system circuit. When the TAP controller is in the Test-Logic-Reset state, the instruction register is initialized to the IDCODE instruction. 22.5.2 Notes
1. Boundary scan mode does not cover power-supply-related pins (VCC, VCL, VSS, AVCC, AVSS, and AVref). 2. Boundary scan mode covers clock-related pins (EXTAL, XTAL, X1, and X2). 3. Boundary scan mode does not cover reset- and standby-related pins (RES, STBY, and RESO). 4. Boundary scan mode does not cover JTAG-related pins (ETCK, ETDI, ETDO, ETMS, and ETRST). 5. Fix the MD2 pin low.
22.6
Usage Notes
1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not the JTAG is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For details, see section 26, Electrical Characteristics. To activate the JTAG after a reset, drive the ETRST pin to 1 and specify the ETCK, ETMS, and ETDI pins to any value. If the JTAG is not to be activated, drive the ETRST, ETCK, ETMS, and ETDI pins to 1 or the high-impedance state. These pins are internally pulled up and are noted in standby mode. 2. The following must be considered when the power-on reset signal is applied to the ETRST pin. The reset signal must be applied at power-on. To prevent the LSI system operation from being affected by the ETRST pin of the board tester, circuits must be separated. Alternatively, to prevent the ETRST pin of the board tester from being affected by the LSI system reset, circuits must be separated. Figure 22.3 shows a design example of the reset signal circuit wherein no reset signal interference occurs.
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Section 22 Boundary Scan (JTAG)
Board edge pin System reset Power-on reset circuit ETRST ETRST
This LSI RES
Figure 22.3 Reset Signal Circuit without Reset Signal Interference 3. The registers are not initialized in standby mode. If the ETRST pin is set to 0 in standby mode, IDCODE mode will be entered. 4. The frequency of the ETCK pin must be lower than that of the system clock. For details, see section 26, Electrical Characteristics. 5. Data input/output in serial data transfer starts from the LSB. Figure 22.4 and 22.5 shows examples of serial data input/output. 6. When data that exceeds the number of bits of the register connected between the ETDI and ETDO pins is serially transferred, the serial data that exceeds the number of register bits and output from the ETDO pin is the same as that input from the ETDI pin. 7. If the JTAG serial transfer sequence is disrupted, the ETRST pin must be reset. Transfer should then be retried, regardless of the transfer operation. 8. If a pin with a pull-up function is sampled while its pull-up function is enabled, 1 can be detected at the corresponding input scan register. In this case, the corresponding enable scan register should be cleared to 0. 9. If a pin with an open-drain function is sampled while its open-drain function is enabled and its corresponding output scan register is 1, 0 can be detected at the corresponding enable scan register.
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Section 22 Boundary Scan (JTAG)
SDIR serial data input/output SDIR is captured into the shift register in Capture-IR, and bits 0 to 31 of SDIR are output in that order from the ETDO pin in Shift-IR. Data input from the ETDI pin is written to SDIR in Update-IR. ETDI Bit 31 . . . . . . . . . . .
Shift register
ETDI Bit 31
Shift register
Bit 31 Bit 28
. . .
Bit 31 Bit 28 SDIR
SDIR
Bit 0 ETDO
Bit 0 ETDO
Capture-IR
Update-IR
Figure 22.4 Serial Data Input/Output (1)
SDIDR serial data input/output SDIDR is captured into the shift register in Capture-DR in IDCODE mode, and bits 0 to 31 of SDIDR are output in that order from the ETDO pin in Shift-DR. Data input from the ETDI pin is not written to any register in Update-DR. ETDI Bit 31 Bit 31
Shift register
. . . .
SDIDR
Bit 0
Bit 0
ETDO
Capture-DR
Figure 22.5 Serial Data Input/Output (2)
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Section 23 Clock Pulse Generator
Section 23 Clock Pulse Generator
This LSI incorporates a clock pulse generator which generates the system clock (), internal clock, bus master clock, and subclock (SUB). The clock pulse generator consists of an oscillator, duty correction circuit, system clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and subclock waveform forming circuit. Figure 23.1 shows a block diagram of the clock pulse generator.
EXTAL XTAL Oscillator
Duty correction circuit
System clock select circuit
Mediumspeed clock divider
/2 to /32
Bus master clock select circuit
EXCL (ExEXCL)
Subclock input circuit
Subclock waveform forming circuit
SUB
WDT_1 count clock
System clock to pin
Internal clock to on-chip peripheral modules
Bus master clock to CPU, DTC, and LPC
Figure 23.1 Block Diagram of Clock Pulse Generator In high-speed mode or medium-speed mode, the bus master clock is selected by software according to the settings of the SCK2 to SCK0 bits in the standby control register (SBYCR). For details on SBYCR, see section 24.1.1, Standby Control Register (SBYCR). The subclock input is controlled by software according to the EXCLE bit and the EXCLS bit in the port control register (PTCNT0) settings in the low power control register (LPWRCR). For details on LPWRCR, see section 24.1.2, Low-Power Control Register (LPWRCR). For details on PTCNT0, see section 8.17.1, Port Control Register 0 (PTCNT0).
CPG0500A_000020020300
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Section 23 Clock Pulse Generator
23.1
Oscillator
Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 23.1.1 Connecting Crystal Resonator
Figure 23.2 shows a typical method for connecting a crystal resonator. An appropriate damping resistance Rd, given in table 23.1 should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 23.3 shows an equivalent circuit of a crystal resonator. A crystal resonator having the characteristics given in table 23.2 should be used. The frequency of the crystal resonator should be the same as that of the system clock ().
CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF
Figure 23.2 Typical Connection to Crystal Resonator Table 23.1 Damping Resistor Values
Frequency (MHz) Rd () 4 500 8 200 10 0 12 0 16 0 20 0
CL L XTAL Rs EXTAL AT-cut parallel-resonance crystal resonator
C0
Figure 23.3 Equivalent Circuit of Crystal Resonator
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Section 23 Clock Pulse Generator
Table 23.2 Crystal Resonator Parameters
Frequency (MHz) RS (max) () C0 (max) (pF) 4 120 7 8 80 7 10 70 7 12 60 7 16 50 7 20 40 7
23.1.2
External Clock Input Method
Figure 23.4 shows a typical method of inputting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode. External clock input conditions are shown in table 23.3. The frequency of the external clock should be the same as that of the system clock ().
EXTAL XTAL
External clock input
Open
(a) Example of external clock input when XTAL pin is left open
EXTAL XTAL
External clock input
(b) Example of external clock input when an inverted clock is input to XTAL pin
Figure 23.4 Example of External Clock Input
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Section 23 Clock Pulse Generator
Table 23.3 External Clock Input Conditions
VCC = 3.0 to 3.6 V Item External clock input pulse width low level External clock input pulse width high level External clock rising time External clock falling time Symbol tEXL tEXH tEXr tEXf Min 20 20 0.4 80 Clock pulse width high level tCH 0.4 80 Max 5 5 0.6 0.6 Unit Test Conditions ns ns ns ns tcyc ns tcyc ns 5 MHz < 5 MHz 5 MHz < 5 MHz Figure 25.4 Figure 23.5
Clock pulse width low level tCL
tEXH
tEXL
EXTAL
VCC x 0.5
tEXr
tEXf
Figure 23.5 External Clock Input Timing The oscillator and duty correction circuit can adjust the waveform of the external clock input that is input from the EXTAL pin. When a specified clock signal is input to the EXTAL pin, internal clock signal output is determined after the external clock output stabilization delay time (tDEXT) has passed. As the clock signal output is not determined during the tDEXT cycle, a reset signal should be set to low to maintain the reset state. Table 23.4 shows the external clock output stabilization delay time. Figure 23.6 shows the timing of the external clock output stabilization delay time.
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Section 23 Clock Pulse Generator
Table 23.4 External Clock Output Stabilization Delay Time Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V
Item Symbol Min 500 Max Unit s Remarks Figure 23.6
External clock output stabilization delay tDEXT* time Note: * tDEXT includes a RES pulse width (tRESW).
VCC
3.0 V
STBY
VIH
EXTAL
(Internal and external)
RES tDEXT*
Note: The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW).
Figure 23.6 Timing of External Clock Output Stabilization Delay Time
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Section 23 Clock Pulse Generator
23.2
Duty Correction Circuit
The duty correction circuit generates the system clock () by correcting the duty of the clock output from the oscillator.
23.3
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (), and generates /2, /4, /8, /16, and /32 clocks.
23.4
Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply to the bus master from either the system clock () or medium-speed clock (/2, /4, /8, /16, or /32) by the SCK2 to SCK0 bits in SBYCR.
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Section 23 Clock Pulse Generator
23.5
Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL or ExEXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL or ExEXCL pin. Figure 23.7 shows the relationship of subclock input from the EXCL pin and the ExEXCL pin. When using a pin to input the subclock, specify input for the pin by clearing the DDR bit of the pin to 0. The EXCL pin is specified as an input pin by clearing the EXCLS bit in PTCNT0 to 0. The ExEXCL pin is specified as an input pin by setting the EXCLS bit in PTCNT0 to 1. The subclock input is enabled by setting the EXCLE bit in LPWRCR to 1.
EXCLS (PTCNT0) EXCLE (LPWRCR)
P96/EXCL Subclock P50/ExEXCL
Figure 23.7 Subclock Input from EXCL Pin and ExEXCL Pin Subclock input conditions are shown in table 23.5. When the subclock is not used, subclock input should not be enabled. Table 23.5 Subclock Input Conditions
VCC = 3.0 to 3.6 V Item Subclock input pulse width low level Subclock input pulse width high level Subclock input rising time Subclock input falling time Symbol tEXCLL tEXCLH tEXCLr tEXCLf Min Typ 15.26 15.26 Max 10 10 Unit s s ns ns Test Conditions Figure 23.8
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Section 23 Clock Pulse Generator
tEXCLH
tEXCLL
EXCL
VCC x 0.5
tEXCLr
tEXCLf
Figure 23.8 Subclock Input Timing
23.6
Subclock Waveform Forming Circuit
To remove noise from the subclock input at the EXCL (ExEXCL) pin, the subclock waveform forming circuit samples the subclock using a divided clock. The sampling frequency is set by the NESEL bit in LPWRCR. The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
23.7
Clock Select Circuit
The clock select circuit selects the system clock that is used in this LSI. A clock generated by the oscillator to which the XTAL and EXTAL pins are connected is selected as a system clock () when returning from high-speed mode, medium-speed mode, sleep mode, the reset state, or standby mode. In subactive mode, subsleep mode, or watch mode, a subclock input from the EXCL (ExEXCL) pin is selected as a system clock when the EXCLE bit in LPWRCR is 1. At this time, on-chip peripheral modules such as the CPU, TMR_0, TMR_1, WDT_0, WDT_1, I/O ports, and interrupt controller and their functions operate on the SUB clock. The count clock and sampling clock for each timer are divided SUB clocks.
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Section 23 Clock Pulse Generator
23.8
Handling of X1 and X2 Pins
The X1 and X2 pins should be open, as shown in figure 23.9.
X1 X2
Open Open
Figure 23.9 Handling of X1 and X2 Pins
23.9
23.9.1
Usage Notes
Notes on Resonator
Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user. Consult with the resonator manufacturer about the resonator circuit ratings that vary depending on the stray capacitances of the resonator and installation circuit. Make sure the voltage applied to the oscillation pins do not exceed the maximum rating. 23.9.2 Notes on Board Design
When using a crystal resonator, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator to prevent inductive interference with correct oscillation as shown in figure 23.10.
Signal A CL2 XTAL EXTAL CL1 Signal B This LSI
Prohibited
Figure 23.10 Note on Board Design of Oscillator Section
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Section 23 Clock Pulse Generator
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Section 24 Power-Down Modes
Section 24 Power-Down Modes
For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules. * Medium-speed mode System clock frequency for the CPU operation can be selected as /2, /4, /8, /16,or /32. * Subactive mode The CPU operates based on the subclock, and on-chip peripheral modules TMR_0, TMR_1, WDT_0, and WDT_1 continue operating. * Sleep mode The CPU stops but on-chip peripheral modules continue operating. * Subsleep mode The CPU stops but on-chip peripheral modules TMR_0, TMR_1, WDT_0, and WDT_1 continue operating. * Watch mode The CPU stops but on-chip peripheral module WDT_1 continue operating. * Software standby mode The clock pulse generator stops, and the CPU and on-chip peripheral modules stop operating. * Hardware standby mode The clock pulse generator stops, and the CPU and on-chip peripheral modules enter the reset state. * Module stop mode Independently of above operating modes, on-chip peripheral modules that are not used can be stopped individually.
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Section 24 Power-Down Modes
24.1
Register Descriptions
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, SYSCR2, MSTPCRH, and MSTPCRL the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). For details on the PSS bit in TSCR_1 (WDT_1), see TCSR_1 in section 14.3.2,Timer Control/Status Register (TCSR). * * * * * Standby control register (SBYCR) Low power control register (LPWRCR) Module stop control register H (MSTPCRH) Module stop control register L (MSTPCRL) Module stop control register A (MSTPCRA) Standby Control Register (SBYCR)
24.1.1
SBYCR controls power-down modes.
Bit 7 Bit Name Initial Value R/W SSBY 0 R/W Description Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode 1: Shifts to software standby mode, subactive mode, or watch mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode 1: Shifts to watch mode or high-speed mode Note that the SSBY bit is not changed even if a mode transition occurs by an interrupt.
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Section 24 Power-Down Modes
Bit 6 5 4
Bit Name Initial Value R/W STS2 STS1 STS0 0 0 0 R/W R/W R/W
Description Standby Timer Select 2 to 0 On canceling software standby mode, watch mode, or subactive mode, these bits select the wait time for clock stabilization from clock oscillation start. Select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency. Table 24.1 shows the relationship between the STS2 to STS0 values and wait time. With an external clock, an arbitrary wait time can be selected. For normal cases, the minimum value is recommended.
3 2 1 0
SCK2 SCK1 SCK0
0 0 0 0
R/W R/W R/W R/W
Reserved The initial value should not be changed. System Clock Select 2 to 0 These bits select a clock for the bus master in high-speed mode or medium-speed mode. When making a transition to subactive mode or watch mode, these bits must be cleared to B'000. 000: High-speed mode 001: Medium-speed clock: /2 010: Medium-speed clock: /4 011: Medium-speed clock: /8 100: Medium-speed clock: /16 101: Medium-speed clock: /32 11X: Setting prohibited
[Legend] X: Don't care
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Section 24 Power-Down Modes
Table 24.1 Operating Frequency and Wait Time
STS2 STS1 STS0 Wait Time 0 0 0 0 1 1 1 1 Note: 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states* 20 MHz 0.4 0.8 1.6 3.3 6.6 13.1 0.8 10 MHz 0.8 1.6 3.3 6.6 13.1 26.2 1.6 8 MHz 1.0 2.0 4.1 8.2 16.4 32.8 2.0 6 MHz 1.3 2.7 5.5 10.9 21.8 43.6 2.7 4 MHz 2.0 4.1 8.2 16.4 32.8 65.6 4.0 s Unit ms
Recommended specification * Setting prohibited.
24.1.2
Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit 7 Initial Bit Name Value DTON 0 R/W Description R/W Direct Transfer On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts directly to subactive mode, or shifts to sleep mode or software standby mode When the SLEEP instruction is executed in subactive mode: 0: Shifts to subsleep mode or watch mode 1: Shifts directly to high-speed mode, or shifts to subsleep mode
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Section 24 Power-Down Modes
Bit 6
Initial Bit Name Value LSON 0
R/W R/W
Description Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled. When the SLEEP instruction is executed in high-speed mode or medium-speed mode: 0: Shifts to sleep mode, software standby mode, or watch mode 1: Shifts to watch mode or subactive mode When the SLEEP instruction is executed in subactive mode: 0: Shifts directly to watch mode or high-speed mode 1: Shifts to subsleep mode or watch mode When watch mode is cancelled: 0: Shifts to high-speed mode 1: Shifts to subactive mode
5
NESEL
0
R/W
Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (SUB) input from the EXCL or ExEXCL pin is sampled using the clock () generated by the system clock pulse generator. Clear this bit to 0 when is 5 MHz or more. 0: Sampling using /32 clock 1: Sampling using /4 clock
4
EXCLE
0
R/W
Subclock Input Enable Enables or disables subclock input from the EXCL or ExEXCL pin. 0: Disables subclock input from the EXCL or ExEXCL pin 1: Enables subclock input from the EXCL or ExEXCL pin
3 to 0
All 0
R/W
Reserved The initial value should not be changed.
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Section 24 Power-Down Modes
24.1.3
Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA)
MSTPCR specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. * MSTPCRH
Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Data transfer controller (DTC) 16-bit free-running timer (FRT) 8-bit timers (TMR_0 and TMR_1) 8-bit PWM timer (PWM), 14-bit PWM timer (PWMX) Reserved The initial value should not be changed. A/D converter 8-bit timers (TMR_X and TMR_Y)
* MSTPCRL
Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Serial communication interface 1 (SCI_1) Serial communication interface 2 (SCI_2) I2C bus interface channel 0 (IIC_0) I2C bus interface channel 1 (IIC_1) KBU TPU LPC
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Section 24 Power-Down Modes
* MSTPCRA
Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTPA7 0 MSTPA6 0 MSTPA5 0 MSTPA4 0 MSTPA3 0 MSTPA2 0 MSTPA1 0 MSTPA0 0 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. 14-bit PWM timer (PWMX) 8-bit PWM timer (PWM)
MSTPCRH and MSTPCRA set operation or stop by a combination of bits as follows:
MSTPCRH: MSTP11 0 0 1 1 MSTPCRA: MSTPA1 0 1 0 1 Function 14-bit PWM timer (PWMX) operates. 14-bit PWM timer (PWMX) stops. 14-bit PWM timer (PWMX) stops. 14-bit PWM timer (PWMX) stops.
MSTPCRH: MSTP11 0 0 1 1
MSTPCRA: MSTPA0 0 1 0 1
Function 8-bit PWM timer (PWM) operates. 8-bit PWM timer (PWM) stops. 8-bit PWM timer (PWM) stops. 8-bit PWM timer (PWM) stops.
Note: The MSTP11 bit in MSTPCRH is the module stop bit of PWM and PWMX.
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Section 24 Power-Down Modes
MSTPCRB specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1.
24.2
Mode Transitions and LSI States
Figure 24.1 shows the possible mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode. The RES input causes a mode transition from a state other than hardware standby mode to the reset state. Table 24.2 shows the LSI internal states in each operating mode.
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Section 24 Power-Down Modes
Program halt state STBY pin = Low Reset state Hardware standby mode
STBY pin = High RES pin = Low
Program execution state
RES pin = High SLEEP instruction
SSBY = 0, LSON = 0 Sleep mode (main clock)
High-speed mode (main clock) SCK2 to SCK0 are 0 SCK2 to SCK0 are not 0
Any interrupt SLEEP instruction External interrupt*3 SLEEP instruction Interrupt*1 LSON bit = 0 SSBY = 1, PSS = 1, DTON = 0 Watch mode (subclock) SLEEP instruction Interrupt*1 LSON bit = 1 SLEEP instruction Interrupt*2 SSBY = 0, PSS = 1, LSON = 1 Subsleep mode (subclock) SSBY = 1, PSS = 0, LSON = 0 Software standby mode
Medium-speed mode (main clock)
SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to STS0), clock switching exception processing
SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 1 Clock switching exception processing
Subactive mode (subclock)
: Transition after exception processing
: Power-down mode
Notes: * When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * Always select high-speed mode before making a transition to watch mode or subactive mode. 1. NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE0 to WUE15, WDT_1, and KBU interrupts 2. NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE0 to WUE15, WDT_0, WDT_1, TMR_0, TMR_1, and KBU interrupts 3. NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE0 to WUE15, and KBU interrupts
Figure 24.1 Mode Transition Diagram
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Section 24 Power-Down Modes
Table 24.2 LSI Internal States in Each Operating Mode
Function
System clock pulse generator Subclock input
HighSpeed
Functioning Functioning Functioning
MediumSpeed Sleep
Functioning Functioning Functioning in mediumspeed mode Functioning Functioning Functioning Halted
Module Stop
Functioning Functioning Functioning
Watch
Halted
Subactive
Halted
Subsleep
Halted
Software Standby
Halted
Hardware Standby
Halted
Functioning Halted
Functioning Subclock operation
Functioning Halted
Halted
Halted
CPU
Instruction execution Registers
Halted
Halted
Retained
Retained
Retained
Retained
Undefined
External NMI interrupts IRQ0 to IRQ15 KIN0 to KIN15 WUE0 to WUE15 On-chip DTC peripheral modules
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Halted
Functioning
Functioning in mediumspeed mode/ Functioning Functioning
Functioning
Function- Halted ing/Halted (retained) (retained)
Halted (retained)
Halted (retained)
Halted (retained)
Halted (reset)
WDT_1
Functioning
Functioning
Functioning
Subclock operation Halted (retained)
Subclock operation
Subclock operation
Halted (retained)
Halted (reset)
WDT_0 TMR_0, TMR_1 FRT TPU TMR_X, TMR_Y IIC_0 IIC_1 LPC KBU Functioning in mediumspeed mode/ Functioning Functioning/Halted (retained)
Halted (retained)
Halted (retained)
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Section 24 Power-Down Modes
HighSpeed
Functioning
Function
On-chip PWM peripheral PWMX modules SCI_1 SCI_2 A/D converter RAM
MediumSpeed Sleep
Functioning Functioning
Module Stop
Watch
Subactive
Halted (retained) Halted (reset)
Subsleep
Halted (retained) Halted (reset)
Software Hardware Standby Standby
Halted (retained) Halted (reset) Halted (reset)
Function- Halted ing/Halted (retained) (reset) Halted (reset)
Functioning Functioning
Functioning Functioning
Functioning (DTC) Functioning
Functioning Functioning
Retained
Functioning Functioning
Retained
Retained
Retained
I/O
Retained
Functioning
Retained
High impedance
Note: Halted (retained) means that the internal register values are retained and the internal state is operation suspended. Halted (reset) means that the internal register values and the internal state are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained).
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Section 24 Power-Down Modes
24.3
Medium-Speed Mode
The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the operating clock can be selected from /2, /4, /8, /16, or /32. On-chip peripheral modules other than the bus masters and KBU operate on the system clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in four states, and internal I/O registers in eight states. By clearing all of bits SCK2 to SCK0 to 0 in medium-speed mode, a transition is made to highspeed mode at the end of the current bus cycle. When the SLEEP instruction is executed with the SSBY bit in SBYCR cleared to 0 and the LSON bit in LPWRCR cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, medium-speed mode is cancelled and a transition is made to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode.
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Section 24 Power-Down Modes
Figure 24.2 shows an example of medium-speed mode timing.
Medium-speed mode
, peripheral module clock
Bus master clock
Internal address bus
SBYCR
SBYCR
Internal write signal
Figure 24.2 Medium-Speed Mode Timing
24.4
Sleep Mode
The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the on-chip peripheral modules do not. The contents of the CPU's internal registers are retained. Sleep mode is cleared by any interrupt, the RES pin input, or the STBY pin input. When an interrupt occurs, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the interrupt is disabled, or interrupts other than NMI have been masked by the CPU. When the RES pin is driven low and sleep mode is cleared, a transition is made to the reset state. After the specified reset input time has elapsed, driving the RES pin high causes the CPU to start reset exception handling. When the STBY pin is driven low, a transition is made to hardware standby mode.
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Section 24 Power-Down Modes
24.5
Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop. However, the contents of the CPU registers, on-chip RAM data, I/O ports, and the states of on-chip peripheral modules other than the SCI, PWM, PWMX, and A/D converter are retained as long as the prescribed voltage is supplied. Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15, KIN0 to KIN15, or WUE0 to WUE15), KBU interrupt, RES pin input, or STBY pin input. When an external interrupt request signal is input, system clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ15 interrupt, set the corresponding enable bit to 1. When clearing software standby mode with a KIN0 to KIN15 or WUE0 to WUE15 interrupt, enable the input. In these cases, ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ15 is generated. In the case of an IRQ0 to IRQ15 interrupt, software standby mode is not cleared if the corresponding enable bit is cleared to 0 or if the interrupt has been masked by the CPU. In the case of a KIN0 to KIN15 or WUE0 to WUE15 interrupt, software standby mode is not cleared if the input is disabled or if the interrupt has been masked by the CPU. When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. When the STBY pin is driven low, software standby mode is cleared and a transition is made to hardware standby mode.
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Section 24 Power-Down Modes
Figure 24.3 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge of the NMI pin.
Oscillator
NMI
NMIEG
SSBY
NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction
Oscillation stabilization time tOSC2
NMI exception handling
Figure 24.3 Software Standby Mode Application Example
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Section 24 Power-Down Modes
24.6
Hardware Standby Mode
The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2, MD1, and MD0) while this LSI is in hardware standby mode. Hardware standby mode is cleared by the STBY pin input or the RES pin input. When the STBY pin is driven high while the RES pin is low, the clock pulse generator starts oscillation. Ensure that the RES pin is held low until system clock oscillation stabilizes. When the RES pin is subsequently driven high after the clock oscillation stabilization time has elapsed, reset exception handling starts. Figure 24.4 shows an example of hardware standby mode timing.
Oscillator
RES
STBY
Oscillation stabilization time
Reset exception handling
Figure 24.4 Hardware Standby Mode Timing
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Section 24 Power-Down Modes
24.7
Watch Mode
The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and on-chip peripheral modules other than WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Watch mode is cleared by an interrupt (WOVI1, NMI, IRQ0 to IRQ15, KIN0 to KIN15, or WUE0 to WUE15), KBU interrupt, RES pin input, or STBY pin input. When an interrupt occurs, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR cleared to 0, or a transition is made to subactive mode when the LSON bit is set to 1. When a transition is made to high-speed mode, a stable clock is supplied to the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in SBYCR has elapsed. In the case of an IRQ0 to IRQ15 interrupt, watch mode is not cleared if the corresponding enable bit has been cleared to 0 or the interrupt has been masked by the CPU. In the case of a KIN0 to KIN15 or WUE0 to WUE15 interrupt, watch mode is not cleared if the input is disabled or the interrupt has been masked by the CPU. In the case of an interrupt from an on-chip peripheral module, watch mode is not cleared if the interrupt enable register has been set to disable the reception of that interrupt or the interrupt has been masked by the CPU. When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. When the STBY pin is driven low, a transition is made to hardware standby mode.
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Section 24 Power-Down Modes
24.8
Subsleep Mode
The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. In subsleep mode, the CPU is stopped. On-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. The contents of the CPU registers, several on-chip peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Subsleep mode is cleared by an interrupt (interrupts by on-chip peripheral modules, NMI, IRQ0 to IRQ15, KIN0 to KIN15, or WUE0 to WUE15), RES pin input, or STBY pin input. When an interrupt occurs, subsleep mode is cleared and interrupt exception handling starts. In the case of an IRQ0 to IRQ15 interrupt, subsleep mode is not cleared if the corresponding enable bit has been cleared to 0 or the interrupt has been masked by the CPU. In the case of a KIN0 to KIN15 or WUE0 to WUE15 interrupt, subsleep mode is not cleared if the input is disabled or the interrupt has been masked by the CPU. In the case of an interrupt from an on-chip peripheral module, subsleep mode is not cleared if the interrupt enable register has been set to disable the reception of that interrupt or the interrupt has been masked by the CPU. When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. When the STBY pin is driven low, a transition is made to hardware standby mode.
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Section 24 Power-Down Modes
24.9
Subactive Mode
The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR both set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode with the LSON bit in LPWRCR set to 1, a direct transition is made to subactive mode. Similarly, if an interrupt occurs in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU operates at a low speed based on the subclock and sequentially executes programs. On-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped. When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SBYCR must all be cleared to 0. Subactive mode is cleared by the SLEEP instruction, RES pin input, or STBY pin input. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, subactive mode is cleared and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, a direct transition is made to high-speed mode. For details on direct transitions, see section 24.11, Direct Transitions. When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. When the STBY pin is driven low, a transition is made to hardware standby mode.
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Section 24 Power-Down Modes
24.10
Module Stop Mode
Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cleared and module operation resumes at the end of the bus cycle. In module stop mode, the internal states of on-chip peripheral modules other than the SCI, PWM, PWMX, and A/D converter are retained. After the reset state is cancelled, all on-chip peripheral modules other than the DTC are in module stop mode. While an on-chip peripheral module is in module stop mode, its registers cannot be read from or written to.
24.11
Direct Transitions
The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a direct transition is made from high-speed mode to subactive mode and vice versa, there is no interruption of program execution. A direct transition is enabled by executing the SLEEP instruction after setting the DTON bit in LPWRCR to 1. After a transition, direct transition exception handling starts. When the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR both set to 1, and the PSS bit in TSCR (WDT_1) set to 1, the CPU makes a direct transition to subactive mode. When the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, the DTON bit in LPWRCR set to 1, and the PSS bit in TSCR (WDT_1) set to 1, after the time set in the STS2 to STS0 bits in SBYCR has elapsed, the CPU makes a direct transition to high-speed mode.
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Section 24 Power-Down Modes
24.12
Usage Notes
24.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, while a high level is output or the pull-up MOS is on, the current consumption is not reduced by the amount of current to support the high level output. 24.12.2 Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during oscillation stabilization. 24.12.3 DTC Module Stop Mode If the DTC module stop mode specification and DTC bus request occur simultaneously, the bus is released to the DTC and the MSTP bit cannot be set to 1. After completing the DTC bus cycle, set the MSTP bit to 1 again.
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Section 24 Power-Down Modes
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Section 25 List of Registers
Section 25 List of Registers
The list of registers gives information on the on-chip I/O register addresses, how the register bits are configured, the register states in each operating mode, the register selection condition, and the register address of each module. The information is given as shown below. 1. * * * * * Register addresses (address order) Registers are listed from the lower allocation addresses. For the addresses of 16 bits, the MSB is described. Registers are classified by functional modules. The access size is indicated. H8S/2140B Group compatible register addresses or extended register addresses are selected depending on the RELOCATE bit in system control register 3 (SYSCR3). When the extended register addresses are selected, the some register addresses of ICC_1, TMR_Y, PWMX_0 and PORT are changed. Therefore, the selection with other module registers that share the same addresses with these registers is not necessary.
2. * * *
Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. The bit number in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * Each line covers eight bits, and 16-bit register is shown as 2 lines, respectively. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, see the section on that on-chip peripheral module. 4. Register selection conditions * Register selection conditions are described in the same order as the register addresses. * Register selection conditions with the RELOCATE bit in the system control register 3 (SYSCR3) cleared to 0 are indicated. For details, see section 3.2.2, System Control Register (SYSCR), section 3.2.3, Serial Timer Control Register (STCR), section 23.1.3, Module Stop Control Register H, L, A (MSTPCRH, MSTPCRL, MSTPCRA), or register descriptions for each module.
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Section 25 List of Registers
5. Register addresses (classification by type of module) * The register addresses are described by modules * The register addresses are described in channel order when the module has multiple channels.
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Section 25 List of Registers
25.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Number
Register Name
Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer Status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 LPC channel 4 address register H LPC channel 4 address register L Input data register 4 Output data register 4 Status register 4 Host interface control register 4 SERIRQ control register 2 RAM buffer address register Erase block register LMC status register 1 LMC status register 2 LMC control register 1 LMC control register 2
Abbreviation of Bits
TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 LADR4H LADR4L IDR4 ODR4 STR4 HICR4 SIRQCR2 RBUFAR EBLKR LMCST1 LMCST2 LMCCR1 LMCCR2 8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address
H'FD40 H'FD41 H'FD42 H'FD44 H'FD45 H'FD46 H'FD48 H'FD4A H'FDD4 H'FDD5 H'FDD6 H'FDD7 H'FDD8 H'FDD9 H'FDDA H'FDE0 H'FDE1 H'FDE2 H'FDE3 H'FDE4 H'FDE5 H'FDE6 H'FDE8 H'FDE9 H'FDEA H'FDEB
Module
TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC
Data Width
8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Access States
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
On-chip RAM protect control register MPCR Host base address register 1H Host base address register 1L Host base address register 2H Host base address register 2L HBAR1H HBAR1L HBAR2H HBAR2L
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Section 25 List of Registers
Number
Register Name
On-chip RAM host base address register H On-chip RAM host base address register L Address space set register On-chip RAM address space set register Slave address register 1 Slave address register 2 Flash memory write protect register H
Abbreviation of Bits
RAMBARH RAMBARL ASSR RAMASSR SAR1 SAR2 FWPRH 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address Module
H'FDEC H'FDED H'FDEE H'FDEF H'FDF0 H'FDF1 H'FDF2 H'FDF3 H'FDF4 H'FDF5 H'FDF6 H'FDF7 H'FDF8 H'FDF9 H'FDFA H'FDFB H'FDFC H'FDFD H'FE00 H'FE01 H'FE02 H'FE03 H'FE04 H'FE05 LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC PORT PORT PORT PORT PORT PORT
Data Width
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Access States
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Flash memory write protect register M FWPRM Flash memory write protect register L On-chip RAM address initial value register Flash memory read protect register H Flash memory read protect register M Flash memory read protect register L User command data register Flash memory programming address register H Flash memory programming address register L Manufacture ID code register Device ID code register Port 6 noise canceller enable register Port 6 noise canceller mode control register Port 6 noise cancel cycle setting register Port C noise canceller enable register Port C noise canceller mode control register Port C noise cancel cycle setting register FWPRL RAMAR FRPRH FRPRM FRPRL UCMDTR FLWARH FLWARL LMCMIDCR LMCDIDCR P6NCE P6NCMC P6NCCS PCNCE PCNCMC PCNCCS
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Section 25 List of Registers
Number
Register Name
Abbreviation of Bits
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address Module
H'FE06 H'FE07 H'FE08 H'FE10 H'FE11 H'FE12 H'FE14 H'FE16 H'FE19 H'FE1C H'FE1D H'FE20 H'FE20 H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE31 PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC
Data Width
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Access States
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Port G noise canceller enable register PGNCE Port G noise canceller mode control register Port G noise cancel cycle setting register Port control register 0 Port control register 1 Port control register 2 Port 9 pull-up MOS control register Port G Nch-OD control register Port F Nch-OD control register Port C Nch-OD control register Port D Nch-OD control register Bidirectional data register 0 MW Bidirectional data register 0 SW Bidirectional data register 1 Bidirectional data register 2 Bidirectional data register 3 Bidirectional data register 4 Bidirectional data register 5 Bidirectional data register 6 Bidirectional data register 7 Bidirectional data register 8 Bidirectional data register 9 Bidirectional data register 10 Bidirectional data register 11 Bidirectional data register 12 Bidirectional data register 13 Bidirectional data register 14 Bidirectional data register 15 Input data register 3 Output data register 3 PGNCMC PGNCCS PTCNT0 PTCNT1 PTCNT2 P9PCR PGNOCR PFNOCR PCNOCR PDNOCR TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3
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Section 25 List of Registers
Number
Register Name
Status register 3 LPC channel address register H LPC channel address register L SERIRQ control register 0 SERIRQ control register 1 Input data register 1 Output data register 1 Status register 1 Input data register 2 Output data register 2 Status register 2 Host interface select register Host interface control register 0 Host interface control register 1 Host interface control register 2 Host interface control register 3
Abbreviation of Bits
STR3 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address Module
H'FE32 H'FE34 H'FE35 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A H'FE3C H'FE3D H'FE3E H'FE3F H'FE40 H'FE41 H'FE42 H'FE43 H'FE44 H'FE45 H'FE46 H'FE47 (read) H'FE47 (write) H'FE48 H'FE49 LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC INT INT PORT PORT PORT PORT PORT
Data Width
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Access States
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Wake-up event interrupt mask register WUEMRB B Wake-up event interrupt mask register WUEMR Port G output data register Port G input data register Port G data direction register Port E pull-up MOS control register Port F output data register Port E input data register PGODR PGPIN PGDDR PEPCR PFODR PEPIN
H'FE4A PORT (read) (writing prohibited) H'FE4B (read) H'FE4B (write) PORT PORT
Port F input data register Port F data direction register
PFPIN PFDDR
8 8
8 8
2 2
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Section 25 List of Registers
Number
Register Name
Port C output data register Port D output data register Port C input data register Port C data direction register Port D input data register Port D data direction register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register _2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer Status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 System control register 3 Module stop control register A
Abbreviation of Bits
PCODR PDODR PCPIN PCDDR PDPIN PDDDR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 SYSCR3 MSTPCRA 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8
Address
H'FE4C H'FE4D H'FE4E (read) H'FE4E (write) H'FE4F (read) H'FE4F (write) H'FE50 H'FE51 H'FE52 H'FE53 H'FE54 H'FE55 H'FE56 H'FE58 H'FE5A H'FE5C H'FE5E H'FE70 H'FE71 H'FE72 H'FE74 H'FE75 H'FE76 H'FE78 H'FE7A H'FE7D H'FE7E
Module
PORT PORT PORT PORT PORT PORT TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 SYSTEM SYSTEM
Data Width
8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8
Access States
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 887 of 986 REJ09B0098-0300
Section 25 List of Registers
Number
Register Name
Keyboard matrix interrupt mask register Pull-up MOS control register Keyboard matrix interrupt mask register A Interrupt control register D PWMX (D/A) control register PWMX (D/A) data register AH PWMX (D/A) data register AL PWMX (D/A) data register BH PWMX (D/A) counter H PWMX (D/A) data register BL PWMX (D/A) counter L Flash code control status register
Abbreviation of Bits
KMIMR KMPCR KMIMRA ICRD DACR DADRAH DADRAL DADRBH DACNTH DADRBL DACNTL FCCS 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address
Data Access Module Width States
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
H'FE81 INT (RELOCATE = 1) H'FE82 PORT (RELOCATE = 1) H'FE83 INT (RELOCATE = 1) H'FE87 INT
H'FEA0 PWMX (RELOCATE = 1) H'FEA0 PWMX (RELOCATE = 1) H'FEA1 PWMX (RELOCATE = 1) H'FEA6 PWMX (RELOCATE = 1) H'FEA6 PWMX (RELOCATE = 1) H'FEA7 PWMX (RELOCATE = 1) H'FEA7 PWMX (RELOCATE = 1) H'FEA8 H'FEA9 H'FEAA H'FEAC H'FEAD H'FEAE H'FEB0 H'FEB1 H'FEC0 H'FEC1 H'FEC2 ROM ROM ROM ROM ROM ROM TPU TPU KBU_0 KBU_0 KBU_1
Flash program code select register FPCS Flash erase code select register Flash key code register Flash MAT select register FECS FKEY FMATS
Flash transfer destination address FTDAR register Timer start register Timer synchro register Keyboard control register 1_0 Keyboard buffer transmit data register_0 Keyboard control register 1_1 TSTR TSYR KBCR1_0 KBTR_0 KBCR1_1
Rev. 3.00 Jul. 14, 2005 Page 888 of 986 REJ09B0098-0300
Section 25 List of Registers
Number
Register Name
Keyboard buffer transmit data register_1 Keyboard control register 1_2 Keyboard buffer transmit data register_2 Timer XY control register Timer control register_x Timer control/status register_Y Time constant register A_Y Time constant register B_Y Timer counter_Y Timer input select register I2C bus data register_1 Second slave address register_1 I2C bus mode register_1 Slave address register_1 I2C bus control register_1 I2C bus status register_1
Abbreviation of Bits
KBTR_1 KBCR1_2 KBTR_2 TCR_XY TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y TISR ICDR_1 SARX_1 ICMR_1 SAR_1 ICCR_1 ICSR_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address
H'FEC3 H'FEC4 H'FEC5 H'FEC6
Data Access Module Width States
KBU_1 KBU_2 KBU_2 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
TMR_XY 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
H'FEC8 TMR_Y (RELOCATE = 1) H'FEC9 TMR_Y (RELOCATE = 1) H'FECA TMR_Y (RELOCATE = 1) H'FECB TMR_Y (RELOCATE = 1) H'FECC TMR_Y (RELOCATE = 1) H'FECD TMR_Y (RELOCATE = 1) H'FECE IIC_1 (RELOCATE = 1) H'FECE IIC_1 (RELOCATE = 1) H'FECF IIC_1 (RELOCATE = 1) H'FECF (RELOCATE = 1) H'FED0 (RELOCATE = 1) H'FED1 (RELOCATE = 1) H'FED4 H'FED5 H'FED8 H'FED9 H'FEDA IIC_1 IIC_1 IIC_1 IIC_0 IIC_1 KBU_0 KBU_0 KBU_0
I2C bus extended control register_0 ICXR_0 I2C bus extended control register_1 ICXR_1 Keyboard control register H_0 Keyboard control register L_0 Keyboard data buffer register_0 KBCRH_0 KBCRL_0 KBBR_0
Rev. 3.00 Jul. 14, 2005 Page 889 of 986 REJ09B0098-0300
Section 25 List of Registers
Number
Register Name
Keyboard control register 2_0 Keyboard control register H_1 Keyboard control register L_1 Keyboard data buffer register_1 Keyboard control register 2_1 Keyboard control register H_2 Keyboard control register L_2 Keyboard data buffer register_2 Keyboard control register 2_1 Keyboard comparator control register DDC switch register Interrupt control register A Interrupt control register B Interrupt control register C IRQ status register IRQ sense control register H IRQ sense control register L DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC vector register Address break control register Break address register A Break address register a Break address register b IRQ enable register 16 IRQ status register 16 IRQ sense control register 16 H
Abbreviation of Bits
KBCR2_0 KBCRH_1 KBCRL_1 KBBR_1 KBCR2_1 KBCRH_2 KBCRL_2 KBBR_2 KBCR2_2 KBCOMP DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address
H'FEDB H'FEDC H'FEDD H'FEDE H'FEDF H'FEE0 H'FEE1 H'FEE2 H'FEE3 H'FEE4 H'FEE6 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEF8 H'FEF9 H'FEFA
Module
KBU_0 KBU_1 KBU_1 KBU_1 KBU_1 KBU_2 KBU_2 KBU_2 KBU_2 IrDA IIC_0, IIC_1 INT INT INT INT INT INT DTC DTC DTC DTC DTC DTC INT INT INT INT INT INT INT
Data Access Width States
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 890 of 986 REJ09B0098-0300
Section 25 List of Registers
Number
Register Name
IRQ sense control register 16 L IRQ sense port select register 16 IRQ sense port select register Peripheral clock select register System control register 2 Standby control register Low power control register Module stop control register H Module stop control register L Serial mode register_1 I2C bus control register _1 Bit rate register_1 I2C bus status register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 I2C bus data register_1 Second slave address register_1 I2C bus mode register_1 Slave address register_1 Timer interrupt enable register Timer control/status register Free-running counter Output control register A
Abbreviation of Bits
ISCR16L ISSR16 ISSR PCSR SYSCR2 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 TIER TCSR FRC OCRA 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16
Address
H'FEFB H'FEFC H'FEFD H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88
Module
INT INT INT PWM, PWMX PORT
Data Access Width States
8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SCI_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16
H'FF88 IIC_1 (RELOCATE = 0) H'FF89 SCI_1
H'FF89 IIC_1 (RELOCATE = 0) H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E SCI_1 SCI_1 SCI_1 SCI_1 SCI_1
H'FF8E IIC_1 (RELOCATE = 0) H'FF8E IIC_1 (RELOCATE = 0) H'FF8F IIC_1 (RELOCATE = 0) H'FF8F IIC_1 (RELOCATE = 0) H'FF90 H'FF91 H'FF92 H'FF94 FRT FRT FRT FRT
Rev. 3.00 Jul. 14, 2005 Page 891 of 986 REJ09B0098-0300
Section 25 List of Registers
Number
Register Name
Output control register B Timer control register Timer output compare control register Input capture register A Output control register AR Input capture register B Output control register AF Input capture register C Output compare register DM Input capture register D Serial mode register_2 PWMX (D/A) control register PWMX (D/A) data register AH PWMX (D/A) data register AL Bit rate register_2 Serial control register _2 Transmit data register _2 Serial status register_2 Receive data register _2 Smart card mode register_2 PWMX (D/A) counter H PWMX (D/A) data register BH PWMX (D/A) counter L PWMX (D/A) data register BL Timer control/status register_0
Abbreviation of Bits
OCRB TCR TOCR ICRA OCRAR ICRB OCRAF ICRC OCRDM ICRD SMR_2 DACR DADRAH DADRAL BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DACNTH DADRBH DACNTL DADRBL TCSR_0 16 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address
H'FF94 H'FF96 H'FF97 H'FF98 H'FF98 H'FF9A H'FF9A H'FF9C H'FF9C H'FF9E H'FFA0
Data Access Module Width States
FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT SCI_2 16 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
H'FFA0 PWMX (RELOCATE = 0) H'FFA0 PWMX (RELOCATE = 0) H'FFA1 PWMX (RELOCATE = 0) H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FFA6 (RELOCATE = 0) H'FFA6 (RELOCATE = 0) H'FFA7 (RELOCATE = 0) H'FFA7 (RELOCATE = 0) H'FFA8 (write) SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 PWMX PWMX PWMX PWMX WDT_0
Rev. 3.00 Jul. 14, 2005 Page 892 of 986 REJ09B0098-0300
Section 25 List of Registers
Number
Register Name
Timer control/status register_0 Timer counter_0 Timer counter_0 Port A output data register Port A input data register Port A data direction register
Abbreviation of Bits
TCSR_0 TCNT_0 TCNT_0 PAODR PAPIN PADDR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address
H'FFA8 (read) H'FFA8 (write) H'FFA9 (read) H'FFAA H'FFAB H'FFAB H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD H'FFBD H'FFBE H'FFBE H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3
Module
WDT_0 WDT_0 WDT_0 PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT INT
Data Access Width States
8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Port 1 pull-up MOS control register P1PCR Port 2 pull-up MOS control register P2PCR Port 3 pull-up MOS control register P3PCR Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Port 3 data direction register Port 4 data direction register Port 3 data register Port 4 data register Port 5 data direction register Port 6 data direction register Port 5 data register Port 6 data register Port B output data register Port 8 data direction register Port B input data register Port 7 input data register Port B data direction register Port 8 data register Port 9 data direction register Port 9 data register Interrupt enable register Serial timer control register P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR P8DDR PBPIN P7PIN PBDDR P8DR P9DDR P9DR IER STCR
SYSTEM 8
Rev. 3.00 Jul. 14, 2005 Page 893 of 986 REJ09B0098-0300
Section 25 List of Registers
Number
Register Name
System control register Mode control register Bus control register Wait state control register Timer control register _0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Timer counter_0 Timer counter_1 PWM output enable register B PWM data polarity register B PWM register select PWM data register 15 to 8 I2C bus control register_0 I2C bus status register_0 I2C bus data register_0 Second slave address register_0 I2C bus mode register_0 Slave address register_0 A/D data register AH A/D data register AL A/D data register BH A/D data register BL
Abbreviation of Bits
SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB PWDPRB PWSL PWDR 15 to 8 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address
H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 H'FFD4 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDE H'FFDE H'FFDF H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE3
Module
Data Access Width States
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
SYSTEM 8 SYSTEM 8 BSC BSC TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 PWM PWM PWM PWM IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 8 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8
A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter
Rev. 3.00 Jul. 14, 2005 Page 894 of 986 REJ09B0098-0300
Section 25 List of Registers
Number
Register Name
A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Timer control/status register Timer control/status register Timer counter_1 Timer counter_1 Timer control register_X Timer control register_x Keyboard matrix interrupt mask register Timer control/status register_X Timer control/status register_Y Pull-up MOS control register Input capture register R Time constant register A_Y Input capture register F Time constant register B_Y Keyboard matrix interrupt mask register A Timer counter_X
Abbreviation of Bits
ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCSR_1 TCNT_1 TCNT_1 TCR_X TCR_Y KMIMR TCSR_X TCSR_Y KMPCR TICRR TCORA_Y TICRF TCORB_Y KMIMRA TCNT_X 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address
H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA (write) H'FFEA (read) H'FFEA (write) H'FFEB (read) H'FFF0
Module
Data Access Width States
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter A/D 8 Converter WDT_1 WDT_1 WDT_1 WDT_1 TMR_X 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8
H'FFF0 TMR_Y (RELOCATE = 0) H'FFF1 INT (RELOCATE = 0) H'FFF1 TMR_X
H'FFF1 TMR_Y (RELOCATE = 0) H'FFF2 PORT (RELOCATE = 0) H'FFF2 TMR_X
H'FFF2 TMR_Y (RELOCATE = 0) H'FFF3 TMR_X
H'FFF3 TMR_Y (RELOCATE = 0) H'FFF3 INT (RELOCATE = 0) H'FFF4 TMR_X
Rev. 3.00 Jul. 14, 2005 Page 895 of 986 REJ09B0098-0300
Section 25 List of Registers
Number
Register Name
Timer counter_Y Time constant register C Timer input select register Time constant register A_X Time constant register B_X Timer connection register I Timer connection register S
Abbreviation of Bits
TCNT_Y TCORC TISR TCORA_X TCORB_X TCONRI TCONRS 8 8 8 8 8 8 8
Address
Module
Data Access Width States
8 8 8 8 8 8 8 2 2 2 2 2 2 2
H'FFF4 TMR_Y (RELOCATE = 0) H'FFF5 TMR_X
H'FFF5 TMR_Y (RELOCATE = 0) H'FFF6 H'FFF7 H'FFFC H'FFFE TMR_X TMR_X TMR_X TMR_X, TMR_Y
Rev. 3.00 Jul. 14, 2005 Page 896 of 986 REJ09B0098-0300
Section 25 List of Registers
25.2
Register Bits
Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines.
Register Abbreviation TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 Bit 7 IOB3 TTGE TCFD bit15 bit7 TGRA_1 bit15 bit7 TGRB_1 bit15 bit7 LADR4H LADR4L IDR4 ODR4 STR4 HICR4 SIRQCR2 RBUFAR EBLKR LMCST1 LMCST2 LMCCR1 LMCCR2 MPCR HBAR1H bit15 bit7 bit7 bit7 DBU47 IEDIR3 RBA15 bit7 FLPI Bit 6 CCLR1 IOB2 bit14 bit6 bit14 bit6 bit14 bit6 bit14 bit6 bit6 bit6 DBU46 LPC4E IEDIR4 RBA14 bit6 FLEI Bit 5 CCLR0 IOB1 TCIEU TCFU bit13 bit5 bit13 bit5 bit13 bit5 bit13 bit5 bit5 bit5 DBU45 IBFIE4 IRQ11E4 RBA13 bit5 BUFINII Bit 4 CKEG1 IOB0 TCIEV TCFV bit12 bit4 bit12 bit4 bit12 bit4 bit12 bit4 bit4 bit4 DBU44 IRQ10E4 RBA12 bit4 USERI WRITEE USERIE HB1A28 Bit 3 CKEG0 MD3 IOA3 bit11 bit3 bit11 bit3 bit11 bit3 bit11 bit3 bit3 bit3 C/D4 IRQ9E4 RBA11 bit3 FLPERR Bit 2 TPSC2 MD2 IOA2 bit10 bit2 bit10 bit2 bit10 bit2 bit10 bit2 bit2 bit2 DBU42 IRQ6E4 RBA10 bit2 FLEERR Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB bit9 bit1 bit9 bit1 bit9 bit1 bit9 bit1 bit1 bit1 IBF4 SMIE4 RBA9 bit1 RAMWE HB1A25 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA bit8 bit0 bit8 bit0 bit8 bit0 bit8 bit0 bit0 bit0 OBF4 RBA8 bit0 RAMRE HB1A24 LPC Module TPU_1
PROTECT LMCBUSY ERASEE LMCE FLPIE HB1A31 LPCME FLEIE HB1A30 FWME BUFINIIE HB1A29
BUFTRAN FLASHE HDINIE
WAITSEL HB1A27 HB1A26
Rev. 3.00 Jul. 14, 2005 Page 897 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation HBAR1L HBAR2H HBAR2L RAMBARH RAMBARL ASSR RAMASSR SAR1 SAR2 FWPRH FWPRM FWPRL RAMAR FRPRH FRPRM FRPRL UCMDTR FLWARH FLWARL LMCMIDCR LMCDIDCR P6NCE P6NCMC P6NCCS PCNCE PCNCMC PCNCCS PGNCE PGNCMC PGNCCS PTCNT0 Bit 7 HB1A23 HB2A31 HB2A23 MRA31 MRA23 AS13 SA1R23 SA2R23 WPB23 WPB15 WPB7 RMR7 RPB23 RPB15 RPB7 bit7 FWA14 bit7 bit7 P67NCE Bit 6 HB1A22 HB2A30 HB2A22 MRA30 MRA22 AS12 SA1R22 SA2R22 WPB22 WPB14 WPB6 RMR6 RPB22 RPB14 RPB6 bit6 FWA13 bit6 bit6 P66NCE Bit 5 HB1A21 HB2A29 HB2A21 MRA29 MRA21 AS11 SA1R21 SA2R21 WPB21 WPB13 WPB5 RMR5 RPB21 RPB13 RPB5 bit5 FWA12 bit5 bit5 P65NCE Bit 4 HB1A20 HB2A28 HB2A20 MRA28 MRA20 AS10 RAMAS4 SA1R20 SA2R20 WPB20 WPB12 WPB4 RMR4 RPB20 RPB12 RPB4 bit4 FWA19 FWA11 bit4 bit4 P64NCE Bit 3 HB1A19 HB2A27 HB2A19 MRA27 MRA19 AS23 RAMAS3 SA1R19 SA2R19 WPB19 WPB11 WPB3 RMR3 RPB19 RPB11 RPB3 bit3 FWA18 FWA10 bit3 bit3 P63NCE Bit 2 HB1A18 HB2A26 HB2A18 MRA26 MRA18 AS22 RAMAS2 SA1R18 SA2R18 WPB18 WPB10 WPB2 RMR2 RPB18 RPB10 RPB2 bit2 FWA17 FWA9 bit2 bit2 P62NCE Bit 1 HB1A17 HB2A25 HB2A17 MRA25 MRA17 AS21 RAMAS1 SA1R17 SA2R17 WPB17 WPB9 WPB1 RMR1 RPB17 RPB9 RPB1 bit1 FWA16 FWA8 bit1 bit1 P61NCE Bit 0 HB1A16 HB2A24 HB2A16 MRA24 MRA16 AS20 RAMAS0 SA1R16 SA2R16 WPB16 WPB8 WPB0 RMR0 RPB16 RPB8 RPB0 bit0 FWA15 FWA7 bit0 bit0 P60NCE PORT Module LPC
P67NCMC P66NCMC P65NCMC P64NCMC P63NCMC P62NCMC P61NCMC P60NCMC PC7NCE PC6NCE PC5NCE PC4NCE PC3NCE P6NCCK2 P6NCCK1 P6NCCK0 PC2NCE PC1NCE PC0NCE
PC7NCMC PC6NCMC PC5NCMC PC4NCMC PC3NCMC PC2NCMC PC1NCMC PC0NCMC PG7NCE PG6NCE PG5NCE PG4NCE PG3NCE PCNCCK2 PCNCCK1 PCNCCK0 PG2NCE PG1NCE PG0NCE
PG7NCMC PG6NCMC PG5NCMC PG4NCMC PG3NCMC PG2NCMC PG1NCMC PG0NCMC TMCI0S TMCI1S TMIXS TMIYS TMOXS PGNCCK2 PGNCCK1 PGNCCK0 PWMAS PWMBS EXCLS
Rev. 3.00 Jul. 14, 2005 Page 898 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation PTCNT1 PTCNT2 P9PCR PGNOCR PFNOCR PCNOCR PDNOCR TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3* STR3*
2
Bit 7 SCL0AS LPCS
Bit 6 SCL1AS
Bit 5 SCL0BS P95PCR
Bit 4 SCL1BS P94PCR
Bit 3 SDA0AS P93PCR
Bit 2 SDA1AS P92PCR
Bit 1 SDA0BS P91PCR
Bit 0 SDA1BS LDRQS P90PCR
Module PORT
PG7NOCR PG6NOCR PG5NOCR PG4NOCR PG3NOCR PG2NOCR PG1NOCR PG0NOCR PF7NOCR PF6NOCR PF5NOCR PF4NOCR PF3NOCR PF2NOCR PF1NOCR PF0NOCR PC7NOCR PC6NOCR PC5NOCR PC4NOCR PC3NOCR PC2NOCR PC1NOCR PC0NOCR PD7NOCR PD6NOCR PD5NOCR PD4NOCR PD3NOCR PD2NOCR PD1NOCR PD0NOCR bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 IBF3B DBU37 bit15 bit7 Q/C bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 OBF3B DBU36 bi14 bit6 SELREQ bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 MWMF DBU35 bit13 bit5 IEDIR2 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 SWMF DBU34 bit12 bit4 SMIE3B bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 C/D3 C/D3 bit11 bit3 SMIE3A bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 DBU32 DBU32 bit10 SMIE2 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 IBF3 IBF3 bit9 bit1 IRQ12E1 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 OBF3 OBF3 bit8 TWRE IRQ1E1 LPC
3
LADR3H LADR3L SIRQCR0
Rev. 3.00 Jul. 14, 2005 Page 899 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation SIRQCR1 IDR1 ODR1 STR1 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMRB WUEMR PGODR PGPIN PGDDR PEPCR PFODR PEPIN PFPIN PFDDR PCODR PDODR PCPIN PCDDR PDPIN PDDDR TCR_0 TMDR_0 TIORH_0 Bit 7 IRQ11E3 bit7 bit7 DBU17 bit7 bit7 DBU27 SELSTR3 LPC3E LPCBSY GA20 LFRAME WUEMR7 Bit 6 IRQ10E3 bit6 bit6 DBU16 bit6 bit6 DBU26 Bit 5 IRQ9E3 bit5 bit5 DBU15 bit5 bit5 DBU25 Bit 4 IRQ6E3 bit4 bit4 DBU14 bit4 bit4 DBU24 Bit 3 IRQ11E2 bit3 bit3 C/D1 bit3 bit3 C/D2 SELIRQ6 SDWNE SDWNB IBFIE3 LPCPD WUEMR3 Bit 2 IRQ10E2 bit2 bit2 DBU12 bit2 bit2 DBU22 SELSMI PMEE PMEB IBFIE2 PME WUEMR2 Bit 1 IRQ9E2 bit1 bit1 IBF1 bit1 bit1 IBF2 Bit 0 IRQ6E2 bit0 bit0 OBF1 bit0 bit0 OBF2 Module LPC
SELIRQ11 SELIRQ10 SELIRQ9 LPC2E CLKREQ LRST CLKRUN WUEMR6 LPC1E IRQBSY SDWN SERIRQ WUEMR5 FGA20E LRSTB ABRT LRESET WUEMR4
SELIRQ12 SELIRQ1 LSMIE LSMIB IBFIE1 LSMI WUEMR1 LSCIE LSCIB ERRIE LSCI WUEMR0 WUEMR8 PG0ODR PG0PIN PG0DDR PE0PCR PF0ODR PE0PIN PF0PIN PF0DDR PC0ODR PD0ODR PC0PIN PC0DDR PD0PIN PD0DDR TPSC0 MD0 IOA0 TPU_0 PORT INT
WUEMR15 WUEMR14 WUEMR13 WUEMR12 WUEMR11 WUEMR10 WUEMR9 PG7ODR PG7PIN PG7DDR PF7ODR PF7PIN PF7DDR PC7ODR PD7ODR PC7PIN PC7DDR PD7PIN PD7DDR CCLR2 IOB3 PG6ODR PG6PIN PG6DDR PF6ODR PF6PIN PF6DDR PC6ODR PD6ODR PC6PIN PC6DDR PD6PIN PD6DDR CCLR1 IOB2 PG5ODR PG5PIN PG5DDR PF5ODR PF5PIN PF5DDR PC5ODR PD5ODR PC5PIN PC5DDR PD5PIN PD5DDR CCLR0 BFB IOB1 PG4ODR PG4PIN PG4DDR PE4PCR PF4ODR PE4PIN PF4PIN PF4DDR PC4ODR PD4ODR PC4PIN PC4DDR PD4PIN PD4DDR CKEG1 BFA IOB0 PG3ODR PG3PIN PG3DDR PE3PCR PF3ODR PE3PIN PF3PIN PF3DDR PC3ODR PD3ODR PC3PIN PC3DDR PD3PIN PD3DDR CKEG0 MD3 IOA3 PG2ODR PG2PIN PG2DDR PE2PCR PF2ODR PE2PIN PF2PIN PF2DDR PC2ODR PD2ODR PC2PIN PC2DDR PD2PIN PD2DDR TPSC2 MD2 IOA2 PG1ODR PG1PIN PG1DDR PE1PCR PF1ODR PE1PIN PF1PIN PF1DDR PC1ODR PD1ODR PC1PIN PC1DDR PD1PIN PD1DDR TPSC1 MD1 IOA1
Rev. 3.00 Jul. 14, 2005 Page 900 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation TIORL_0 TIER_0 TSR_0 TCNT_0 Bit 7 IOD3 TTGE bit15 bit7 TGRA_0 bit15 bit7 TGRB_0 bit15 bit7 TGRC_0 bit15 bit7 TGRD_0 bit15 bit7 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 IOB3 TTGE TCFD bit15 bit7 TGRA_2 bit15 bit7 TGRB_2 bit15 bit7 SYSCR3 MSTPCRA KMIMR KMPCR KMIMRA ICRD MSTPA7 KMIMR7 KM7PCR KMIMR15 ICRD7 Bit 6 IOD2 bit14 bit6 bit14 bit6 bit14 bit6 bit14 bit6 bit14 bit6 CCLR1 IOB2 bit14 bit6 bit14 bit6 bit14 bit6 EIVS MSTPA6 KMIMR6 KM6PCR KMIMR14 ICRD6 Bit 5 IOD1 bit13 bit5 bit13 bit5 bit13 bit5 bit13 bit5 bit13 bit5 CCLR0 IOB1 TCIEU TCFU bit13 bit5 bit13 bit5 bit13 bit5 Bit 4 IOD0 TCIEV TCFV bit12 bit4 bit12 bit4 bit12 bit4 bit12 bit4 bit12 bit4 CKEG1 IOB0 TCIEV TCFV bit12 bit4 bit12 bit4 bit12 bit4 Bit 3 IOC3 TGIED TGFD bit11 bit3 bit11 bit3 bit11 bit3 bit11 bit3 bit11 bit3 CKEG0 MD3 IOA3 bit11 bit3 bit11 bit3 bit11 bit3 MSTPA3 KMIMR3 KM3PCR KMIMR11 ICRD3 Bit 2 IOC2 TGIEC TGFC bit10 bit2 bit10 bit2 bit10 bit2 bit10 bit2 bit10 bit2 TPSC2 MD2 IOA2 bit10 bit2 bit10 bit2 bit10 bit2 MSTPA2 KMIMR2 KM2PCR KMIMR10 ICRD2 Bit 1 IOC1 TGIEB TGFB bit9 bit1 bit9 bit1 bit9 bit1 bit9 bit1 bit9 bit1 TPSC1 MD1 IOA1 TGIEB TGFB bit9 bit1 bit9 bit1 bit9 bit1 MSTPA1 KMIMR1 KM1PCR KMIMR9 ICRD1 Bit 0 IOC0 TGIEA TGFA bit8 bit0 bit8 bit0 bit8 bit0 bit8 bit0 bit8 bit0 TPSC0 MD0 IOA0 TGIEA TGFA bit8 bit0 bit8 bit0 bit8 bit0 MSTPA0 KMIMR0 KM0PCR KMIMR8 ICRD0 INT PORT INT SYSTEM TPU_2 Module TPU_0
RELOCATE MSTPA5 KMIMR5 KM5PCR KMIMR13 ICRD5 MSTPA4 KMIMR4 KM4PCR KMIMR12 ICRD4
Rev. 3.00 Jul. 14, 2005 Page 901 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation DACR DADRA Bit 7 TEST DA13 DA5 DADRB DA13 DA5 DACNT DACNT7 DACNT8 FCCS FPCS FECS FKEY FMATS FTDAR TSTR TSYR KBCR1_0 KBTR_0 KBCR1_1 KBTR_1 KBCR1_2 KBTR_2 TCRXY TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y TISR ICDR_1 SARX_1 ICMR_1 FWE K7 MS7 TDER KBTS KBT7 KBTS KBT7 KBTS KBT7 OSX CMIEB CMFB bit7 bit7 bit7 ICDR7 SVAX6 MLS Bit 6 PWME DA12 DA4 DA12 DA4 DACNT6 DACNT9 K6 MS6 TDA6 PS KBT6 PS KBT6 PS KBT6 OEY CMIEA CMFA bit6 bit6 bit6 ICDR6 SVAX5 WAIT Bit 5 DA11 DA3 DA11 DA3 DACNT5 DACNT10 K5 MS5 TDA5 KCIE KBT5 KCIE KBT5 KCIE KBT5 CKSX OVIE OVF bit5 bit5 bit5 ICDR5 SVAX4 CKS2 Bit 4 DA10 DA2 DA10 DA2 DACNT4 DACNT11 FLER K4 MS4 TDA4 KTIE KBT4 KTIE KBT4 KTIE KBT4 CKSY CCLR1 ICIE bit4 bit4 bit4 ICDR4 SVAX3 CKS1 Bit 3 OEB DA9 DA1 DA9 DA1 DACNT3 DACNT12 K3 MS3 TDA3 KBT3 KBT3 KBT3 CCLR0 OS3 bit3 bit3 bit3 ICDR3 SVAX2 CKS0 Bit 2 OEA DA8 DA0 DA8 DA0 DACNT2 DACNT13 K2 MS2 TDA2 CST2 SYNC2 KCIF KBT2 KCIF KBT2 KCIF KBT2 CKS2 OS2 bit2 bit2 bit2 ICDR2 SVAX1 BC2 Bit 1 OS DA7 CFS DA7 CFS DACNT1 K1 MS1 TDA1 CST1 SYNC1 KBTE KBT1 KBTE KBT1 KBTE KBT1 CKS1 OS1 bit1 bit1 bit1 ICDR1 SVAX0 BC1 Bit 0 CKS DA6 DA6 REGS DACNT0 REGS SCO PPVS EPVB K0 MS0 TDA0 CST0 SYNC0 KTER KBT0 KTER KBT0 KTER KBT0 CKS0 OS0 bit0 bit0 bit0 IS ICDR0 FSX BC0 IIC_1 TMR_XY TMR_Y KBU TPU ROM Module PWMX
Rev. 3.00 Jul. 14, 2005 Page 902 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation SAR_1 ICCR_1 ICSR_1 ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCR2_0 KBCRH_1 KBCRL_1 KBBR_1 KBCR2_1 KBCRH_2 KBCRL_2 KBBR_2 KBCR2_2 KBCOMP DDCSWR Bit 7 SVA6 ICE ESTP STOPIM STOPIM KBIOE KBE KB7 KBIOE KBE KB7 KBIOE KBE KB7 IrE Bit 6 SVA5 IEIC STOP HNDS HNDS KCLKI KCLKO KB6 KCLKI KCLKO KB6 KCLKI KCLKO KB6 IrCKS2 Bit 5 SVA4 MST IRTR ICDRF ICDRF KDI KDO KB5 KDI KDO KB5 KDI KDO KB5 IrCKS1 Bit 4 SVA3 TRS AASX ICDRE ICDRE KBFSEL KB4 KBFSEL KB4 KBFSEL KB4 IrCKS0 Bit 3 SVA2 ACKE AL ALIE ALIE KBIE RXCR3 KB3 TXCR3 KBIE RXCR3 KB3 TXCR3 KBIE RXCR3 KB3 TXCR3 IrTxINV CLR3 Bit 2 SVA1 BBSY AAS ALSL ALSL KBF RXCR2 KB2 TXCR2 KBF RXCR2 KB2 TXCR2 KBF RXCR2 KB2 TXCR2 IrRxINV CLR2 Bit 1 SVA0 IRIC ADZ FNC1 FNC1 PER RXCR1 KB1 TXCR1 PER RXCR1 KB1 TXCR1 PER RXCR1 KB1 TXCR1 CLR1 Bit 0 FS SCP ACKB FNC0 FNC0 KBS RXCR0 KB0 TXCR0 KBS RXCR0 KB0 TXCR0 KBS RXCR0 KB0 TXCR0 CLR0 IrDA IIC_0, IIC_1 ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ICRA7 ICR7 ICR7 IRQ7F IRQ7SCB IRQ3SCB DTCEA7 DTCEB7 DTCEC7 DTCED7 DTCEE7 SWDTE ICRA6 ICRB6 ICRC6 IRQ6F IRQ7SCA IRQ3SCA DTCEA6 DTCEB6 DTCEC6 DTCED6 DTCEE6 DTVEC6 ICRA5 ICRB5 ICRC5 IRQ5F IRQ6SCB IRQ2SCB DTCEA5 DTCEB5 DTCEC5 DTCED5 DTCEE5 DTVEC5 ICRA4 ICRB4 ICRC4 IRQ4F IRQ6SCA IRQ2SCA DTCEA4 DTCEB4 DTCEC4 DTCED4 DTCEE4 DTVEC4 ICRA3 ICRB3 ICRC3 IRQ3F IRQ5SCB IRQ1SCB DTCEA3 DTCEB3 DTCEC3 DTCED3 DTCEE3 DTVEC3 ICRA2 ICRB2 ICRC2 IRQ2F IRQ5SCA IRQ1SCA DTCEA2 DTCEB2 DTCEC2 DTCED2 DTCEE2 DTVEC2 ICRA1 ICRB1 ICRC1 IRQ1F IRQ4SCB IRQ0SCB DTCEA1 DTCEB1 DTCEC1 DTCED1 DTCEE1 DTVEC1 ICRA0 ICRB0 ICRC0 IRQ0F IRQ4SCA IRQ0SCA DTCEA0 DTCEB0 DTCEC0 DTCED0 DTCEE0 DTVEC0 DTC INT KBU_2 KBU_1 IIC_0 IIC_1 KBU_0 Module IIC_1
Rev. 3.00 Jul. 14, 2005 Page 903 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L ISSR16 ISSR PCSR Bit 7 CMF A23 A15 A7 IRQ15E IRQ15F Bit 6 A22 A14 A6 IRQ14E IRQ14F Bit 5 A21 A13 A5 IRQ13E IRQ13F Bit 4 A20 A12 A4 IRQ12E IRQ12F Bit 3 A19 A11 A3 IRQ11E IRQ11F Bit 2 A18 A10 A2 IRQ10E IRQ10F Bit 1 A17 A9 A1 IRQ9E IRQ9F Bit 0 BIE A16 A8 IRQ8E IRQ8F Module INT
IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB ISS15 ISS7 ISS14 ISS13 ISS5 PWCKXB ISS12 ISS4 PWCKXA ISS11 ISS3 MSTP11 MSTP3 STOP (BCP1) IRQ9SCA ISS10 ISS2 PWCKB IRQ8SCB ISS9 ISS1 PWCKA IRQ8SCA ISS8 ISS0 PWCKXC PWM, PWMX
SYSCR2 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1*
1
KWUL1 SSBY DTON MSTP15 MSTP7 C/A (GM)
KWUL0 STS2 LSON MSTP14 MSTP6
P6PUE STS1 NESEL MSTP13 MSTP5
STS0 EXCLE MSTP12 MSTP4 O/E (O/E)
SCK2 MSTP10 MSTP2 MP (BCP0) bit2 TEIE bit2 TEND (TEND) bit2 SINV OCIBE OCFB bit10 bit2 bit10 bit2
SCK1 MSTP9 MSTP1 CKS1 (CKS1) bit1 CKE1 bit1 MPB (MPB) bit1 OVIE OVF bit9 bit1 bit9 bit1
SCK0 MSTP8 MSTP0 CKS0 (CKS0) bit0 CKE0 bit0 MPBT (MPBT) bit0 SMIF CCLRA bit8 bit0 bit8 bit0
PORT SYSTEM
CHR (BLK) PE (PE)
SCI_1
BRR_1 SCR_1 TDR_1 SSR_1*
1
bit7 TIE bit7 TDRE (TDRE)
bit6 RIE bit6 RDRF (RDRF) bit6 ICIBE ICFB bit14 bit6 bit14 bit6
bit5 TE bit5 ORER (ORER) bit5 ICICE ICFC bit13 bit5 bit13 bit5
bit4 RE bit4
bit3 MPIE bit3
FER (ERS) PER (PER) bit4 ICIDE ICFD bit12 bit4 bit12 bit4 bit3 SDIR OCIAE OCFA bit11 bit3 bit11 bit3
RDR_1 SCMR_1 TIER TCSR FRC
bit7 ICIAE ICFA bit15 bit7
FRT
OCRA/ OCRB
bit15 bit7
Rev. 3.00 Jul. 14, 2005 Page 904 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation TCR TOCR ICRA/ OCRAR ICRB/ OCRAF ICRC/ OCRDM ICRD Bit 7 IEDGA ICRDMS bit15 bit7 bit15 bit7 bit15 bit7 bit15 bit7 SMR_2*
1
Bit 6 IEDGB OCRAMS bit14 bit6 bit14 bit6 bit14 bit6 bit14 bit6
Bit 5 IEDGC ICRS bit13 bit5 bit13 bit5 bit13 bit5 bit13 bit5
Bit 4 IEDGD OCRS bit12 bit4 bit12 bit4 bit12 bit4 bit12 bit4 O/E (O/E)
Bit 3 BUFEA OEA bit11 bit3 bit11 bit3 bit11 bit3 bit11 bit3 STOP (BCP1)
Bit 2 BUFEB OEB bit10 bit2 bit10 bit2 bit10 bit2 bit10 bit2 MP (BCP0) bit2 TEIE bit2 TEND (TEND) bit2 SINV CKS2 bit2 PA2ODR PA2PIN PA2DDR P12PCR P22PCR P32PCR P12DDR P22DDR P12DR P22DR P32DDR
Bit 1 CKS1 OLVLA bit9 bit1 bit9 bit1 bit9 bit1 bit9 bit1 CKS1 (CKS1) bit1 CKE1 bit1 MPB (MPB) bit1 CKS1 bit1 PA1ODR PA1PIN PA1DDR P11PCR P21PCR P31PCR P11DDR P21DDR P11DR P21DR P31DDR
Bit 0 CKS0 OLVLB bit8 bit0 bit8 bit0 bit8 bit0 bit8 bit0 CKS0 (CKS0) bit0 CKE0 bit0 MPBT (MPBT) bit0 SMIF CKS0 bit0 PA0ODR PA0PIN PA0DDR P10PCR P20PCR P30PCR P10DDR P20DDR P10DR P20DR P30DDR
Module FRT
C/A (GM)
CHR (BLK) PE (PE)
SCI_2
BRR_2 SCR_2 TDR_2 SSR_2*
1
bit7 TIE bit7 TDRE (TDRE)
bit6 RIE bit6 RDRF (RDRF) bit6 WT/IT bit6 PA6ODR PA6PIN PA6DDR P16PCR P26PCR P36PCR P16DDR P26DDR P16DR P26DR P36DDR
bit5 TE bit5 ORER (ORER) bit5 TME bit5 PA5ODR PA5PIN PA5DDR P15PCR P25PCR P35PCR P15DDR P25DDR P15DR P25DR P35DDR
bit4 RE bit4
bit3 MPIE bit3
SCI_2
FER (ERS) PER (PER) bit4 bit4 PA4ODR PA4PIN PA4DDR P14PCR P24PCR P34PCR P14DDR P24DDR P14DR P24DR P34DDR bit3 SDIR RST/NMI bit3 PA3ODR PA3PIN PA3DDR P13PCR P23PCR P33PCR P13DDR P23DDR P13DR P23DR P33DDR
RDR_2 SCMR_2 TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR
bit7 OVF bit7 PA7ODR PA7PIN PA7DDR P17PCR P27PCR P37PCR P17DDR P27DDR P17DR P27DR P37DDR
WDT_0
PORT
Rev. 3.00 Jul. 14, 2005 Page 905 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 Bit 7 P47DDR P37DR P47DR P67DDR P67DR PB7ODR PB7PIN P77PIN PB7DDR P97DDR P97DR IRQ7E IICS EXPE CMIEB CMIEB CMFB CMFB bit7 bit7 bit7 bit7 bit7 bit7 Bit 6 P46DDR P36DR P46DR P66DDR P66DR PB6ODR PB6PIN P86DDR P76PIN PB6DDR P86DR P96DDR P96DR IRQ6E IICX1 ICIS0 CMIEA CMIEA CMFA CMFA bit6 bit6 bit6 bit6 bit6 bit6 Bit 5 P45DDR P35DR P45DR P65DDR P65DR PB5ODR PB5PIN P85DDR P75PIN PB5DDR P85DR P95DDR P95DR IRQ5E IICX0 INTM1 BRSTRM ABW OVIE OVIE OVF OVF bit5 bit5 bit5 bit5 bit5 bit5 Bit 4 P44DDR P34DR P44DR P64DDR P64DR PB4ODR PB4PIN P84DDR P74PIN PB4DDR P84DR P94DDR P94DR IRQ4E IICE INTM0 BRSTS1 AST CCLR1 CCLR1 ADTE bit4 bit4 bit4 bit4 bit4 bit4 Bit 3 P43DDR P33DR P43DR P63DDR P63DR PB3ODR PB3PIN P83DDR P73PIN PB3DDR P83DR P93DDR P93DR IRQ3E FLSHE XRST BRSTS0 WMS1 CCLR0 CCLR0 OS3 OS3 bit3 bit3 bit3 bit3 bit3 bit3 Bit 2 P42DDR P32DR P42DR P52DDR P62DDR P52DR P62DR PB2ODR PB2PIN P82DDR P72PIN PB2DDR P82DR P92DDR P92DR IRQ2E NMIEG MDS2 WMS0 CKS2 CKS2 OS2 OS2 bit2 bit2 bit2 bit2 bit2 bit2 Bit 1 P41DDR P31DR P41DR P51DDR P61DDR P51DR P61DR PB1ODR PB1PIN P81DDR P71PIN PB1DDR P81DR P91DDR P91DR IRQ1E ICKS1 KINWUE MDS1 IOS1 WC1 CKS1 CKS1 OS1 OS1 bit1 bit1 bit1 bit1 bit1 bit1 Bit 0 P40DDR P30DR P40DR P50DDR P60DDR P50DR P60DR PB0ODR PB0PIN P80DDR P70PIN PB0DDR P80DR P90DDR P90DR IRQ0E ICKS0 RAME MDS0 IOS0 WC0 CKS0 CKS0 OS0 OS0 bit0 bit0 bit0 bit0 bit0 bit0 TMR_0, TMR_1 BSC INT SYSTEM Module PORT
Rev. 3.00 Jul. 14, 2005 Page 906 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation PWOERB PWDPRB PWSL Bit 7 OE15 OS15 PWCKE Bit 6 OE14 OS14 PWCKS bit6 IEIC STOP ICDR6 SVAX5 WAIT SVA5 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/IT bit6 CMIEA CMFA bit6 bit6 bit6 bit6 bit6 bit6 Bit 5 OE13 OS13 bit5 MST IRTR ICDR5 SVAX4 CKS2 SVA4 AD7 AD7 AD7 AD7 ADST TME bit5 OVIE OVF bit5 bit5 bit5 bit5 bit5 bit5 Bit 4 OE12 OS12 bit4 TRS AASX ICDR4 SVAX3 CKS1 SVA3 AD6 AD6 AD6 AD6 SCAN PSS bit4 CCLR1 ICF bit4 bit4 bit4 bit4 bit4 bit4 ICST Bit 3 OE11 OS11 RS3 bit3 ACKE AL ICDR3 SVAX2 CKS0 SVA2 AD5 AD5 AD5 AD5 CKS RST/NMI bit3 CCLR0 OS3 bit3 bit3 bit3 bit3 bit3 bit3 Bit 2 OE10 OS10 RS2 bit2 BBSY AAS ICDR2 SVAX1 BC2 SVA1 AD4 AD4 AD4 AD4 CH2 CKS2 bit2 CKS2 OS2 bit2 bit2 bit2 bit2 bit2 bit2 Bit 1 OE9 OS9 RS1 bit1 IRIC ADZ ICDR1 SVAX0 BC1 SVA0 AD3 AD3 AD3 AD3 CH1 CKS1 bit1 CKS1 OS1 bit1 bit1 bit1 bit1 bit1 bit1 Bit 0 OE8 OS8 RS0 bit0 SCP ACKB ICDR0 FSX BC0 FS AD2 AD2 AD2 AD2 CH0 CKS0 bit0 CKS0 OS0 bit0 bit0 bit0 bit0 bit0 bit0 TMR_X WDT_1 A/D Converter A/D Converter IIC_0 Module PWM
PWDR 15 to 8 bit7 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 TCR_X TCSR_X TICRR TICRF TCNT_X TCORC TCORA_X TCORB_X TCONRI ICE ESTP ICDR7 SVAX6 MLS SVA6 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGS1 OVF bit7 CMIEB CMFB bit7 bit7 bit7 bit7 bit7 bit7
Rev. 3.00 Jul. 14, 2005 Page 907 of 986 REJ09B0098-0300
Section 25 List of Registers
Register Abbreviation TCONRS Bit 7 TMRX/Y Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TMR_X, TMR_Y
Notes: 1. In normal mode and Smart Card interface mode, bit names differ in part. ( ) : Bit name in Smart Card interface mode. 2. When TWRE = 1 or SELSTR = 3. 3. When TWRE = 1 and SELSTR = 3.
Rev. 3.00 Jul. 14, 2005 Page 908 of 986 REJ09B0098-0300
Section 25 List of Registers
25.3
Register States in Each Operating Mode
HighSpeed/
Register Abbreviation TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 LADR4H LADR4L IDR4 ODR4 STR4 HICR4 SIRQCR2 RBUFAR EBLKR LMCST1 LMCST2 LMCCR1 LMCCR2 MPCR HBAR1H HBAR1L HBAR2H HBAR2L RAMBARH RAMBARL Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MediumSpeed Watch Sleep
SubActive
SubSleep
Module Stop
Software Standby
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized LPC Module TPU_1
Rev. 3.00 Jul. 14, 2005 Page 909 of 986 REJ09B0098-0300
Section 25 List of Registers
HighSpeed/ Register Abbreviation ASSR RAMASSR SAR1 SAR2 FWPRH FWPRM FWPRL RAMAR FRPRH FRPRM FRPRL UCMDTR FLWARH FLWARL LMCMIDCR LMCDIDCR P6NCE P6NCMC P6NCCS PCNCE PCNCMC PCNCCS PGNCE PGNCMC PGNCCS PTCNT0 PTCNT1 PTCNT2 P9PCR PGNOCR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PORT Module LPC
Rev. 3.00 Jul. 14, 2005 Page 910 of 986 REJ09B0098-0300
Section 25 List of Registers
HighSpeed/ Register Abbreviation PFNOCR PCNOCR PDNOCR TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module LPC
Rev. 3.00 Jul. 14, 2005 Page 911 of 986 REJ09B0098-0300
Section 25 List of Registers
HighSpeed/ Register Abbreviation IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMRB WUEMR PGODR PGPIN PGDDR PEPCR PFODR PEPIN PFPIN PCODR PDODR PCPIN PFDDR PCDDR PDPIN PDDDR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_0 PORT PORT INT Module LPC
Rev. 3.00 Jul. 14, 2005 Page 912 of 986 REJ09B0098-0300
Section 25 List of Registers
HighSpeed/ Register Abbreviation TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 SYSCR3 MSTPCRA KMIMR KMPCR KMIMRA ICRD DACR DADRA DADRB DACNT FCCS FPCS FECS FKEY FMATS FTDAR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Initialized Initialized Initialized Initialized SubSleep Active SubSleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized ROM PWMX PWMX INT PORT INT SYSTEM TPU_2 Module TPU_0
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 3.00 Jul. 14, 2005 Page 913 of 986 REJ09B0098-0300
Section 25 List of Registers
HighSpeed/ Register Abbreviation TSTR TSYR KBCR1_0 KBTR_0 KBCR1_1 KBTR_1 KBCR1_2 KBTR_2 TCRXY TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y TISR ICDR_1 SARX_1 ICMR_1 SAR_1 ICCR_1 ICSR_1 ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCR2_0 KBCRH_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized KBU_1 IIC_0 IIC_1 KBU_0 IIC_1 TMR_XY TMR_Y KBU Module TPU
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Section 25 List of Registers
HighSpeed/ Register Abbreviation KBCRL_1 KBBR_1 KBCR2_1 KBCRH_2 KBCRL_2 KBBR_2 KBCR2_2 KBCOMP DDCSWR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Sleep SubActive SubSleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized IrDA IIC_0, IIC_1 ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized INT DTC INT KBU_2 Module KBU_1
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Section 25 List of Registers
HighSpeed/ Register Abbreviation ISSR16 ISSR PCSR Reset Initialized Initialized Initialized MediumSpeed Watch Initialized Initialized Initialized SubSleep Active SubSleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized PWM, PWMX SYSCR2 SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 TIER TCSR FRC OCRA/ OCRB TCR TOCR ICRA/ OCRAR ICRB/ OCRAF ICRC/ OCRDM ICRD Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized FRT SCI_1 PORT SYSTEM Module INT
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
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Section 25 List of Registers
HighSpeed/ Register Abbreviation SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Initialized Initialized Initialized SubSleep Active SubSleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PORT WDT_0 Module SCI_2
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
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Section 25 List of Registers
HighSpeed/ Register Abbreviation P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Initialized Initialized SubSleep Active SubSleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_0* A TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 PWOERB PWDPRB PWSL PWDR 15 to 8 ICCR_0 ICSR_0 ICDR_0 SARX_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized IIC_0 PWM TMR_1 TMR_1 BSC INT SYSTEM Module PORT
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
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Section 25 List of Registers
HighSpeed/ Register Abbreviation ICMR_0 SAR_0 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 TCR_X TCSR_X TICRR TICRF TCNT_X TCORC TCORA_X TCORB_X TCONRI TCONRS Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized MediumSpeed Watch Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SubSleep Active SubSleep Module Stop Software Standby Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TMR_X, TMR_Y TMR_X WDT_1 A/D Converter Module IIC_0
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
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Section 25 List of Registers
25.4
Register Selection Condition
Register Abbreviation TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 LADR4H LADR4L IDR4 ODR4 STR4 HICR4 SIRQCR2 RBUFAR EBLKR LMCST1 LMCST2 LMCCR1 LMCCR2 MPCR HBAR1H HBAR1L HBAR2H HBAR2L RAMBARH RAMBARL ASSR RAMASSR MSTP0 = 0 LPC Register selection condition MSTP1 = 0 Module TPU_1
Lower Address H'FD40 H'FD41 H'FD42 H'FD44 H'FD45 H'FD46 H'FD48 H'FD4A H'FDD4 H'FDD5 H'FDD6 H'FDD7 H'FDD8 H'FDD9 H'FDDA H'FDE0 H'FDE1 H'FDE2 H'FDE3 H'FDE4 H'FDE5 H'FDE6 H'FDE8 H'FDE9 H'FDEA H'FDEB H'FDEC H'FDED H'FDEE H'FDEF
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Section 25 List of Registers
Lower Address H'FDF0 H'FDF1 H'FDF2 H'FDF3 H'FDF4 H'FDF5 H'FDF6 H'FDF7 H'FDF8 H'FDF9 H'FDFA H'FDFB H'FDFC H'FDFD H'FE00 H'FE01 H'FE02 H'FE03 H'FE04 H'FE05 H'FE06 H'FE07 H'FE08 H'FE10 H'FE11 H'FE12 H'FE14 H'FE16 H'FE19 H'FE1C H'FE1D
Register Abbreviation SAR1 SAR2 FWPRH FWPRM FWPRL RAMAR FRPRH FRPRM FRPRL UCMDTR FLWARH FLWARL LMCMIDCR LMCDIDCR P6NCE P6NCMC P6NCCS PCNCE PCNCMC PCNCCS PGNCE PGNCMC PGNCCS PTCNT0 PTCNT1 PTCNT2 P9PCR PGNOCR PFNOCR PCNOCR PDNOCR
Register selection condition MSTP0 = 0
Module LPC
No condition
PORT
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Section 25 List of Registers
Lower Address H'FE20
Register Abbreviation TWR0MW TWR0SW
Register selection condition MSTP0 = 0
Module LPC
H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE31 H'FE32 H'FE34 H'FE35 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A H'FE3C H'FE3D H'FE3E H'FE3F H'FE40
TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 IDR2 ODR2 STR2 HISEL HICR0
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Section 25 List of Registers
Lower Address H'FE41 H'FE42 H'FE43 H'FE44 H'FE45 H'FE46 H'FE47
Register Abbreviation HICR1 HICR2 HICR3 WUEMRB WUEMR PGODR PGPIN (read) PGDDR (write)
Register selection condition MSTP0 = 0
Module LPC
No condition
INT
No condition
PORT
H'FE48 H'FE49 H'FE4A H'FE4B H'FE4C H'FE4D H'FE4E
PEPCR PFODR PEPIN (read) (write prohibited) PFPIN (read) PCODR PDODR PCPIN (read) PCDDR (write)
H'FE4F
PDPIN (read) PDDDR (write)
H'FE50 H'FE51 H'FE52 H'FE53 H'FE54 H'FE55 H'FE56 H'FE58 H'FE5A H'FE5C H'FE5E
TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0
MSTP1 = 0
TPU_0
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Section 25 List of Registers
Lower Address H'FE70 H'FE71 H'FE72 H'FE74 H'FE75 H'FE76 H'FE78 H'FE7A H'FE7D H'FE7E H'FE81 H'FE82 H'FE83 H'FE87 H'FEA0
Register Abbreviation TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 SYSCR3 MSTPCRA KMIMR (RELOCATE = 1) KMPCR (RELOCATE = 1) KMIMRA (RELOCATE = 1) ICRD DACR (RELOCATE = 1) DADRAH (RELOCATE = 1)
Register selection condition MSTP1 = 0
Module TPU_2
No condition
SYSTEM
MSTP2 = 0
INT PORT INT
No condition MSTP11 = 0 MSTPA1 = 0 REGS in PWMX DACNT/DADRB = 1 REGS in DACNT/DADRB = 0
H'FEA1 H'FEA6
DADRAL (RELOCATE = 1) DADRBH (RELOCATE = 1) DACNTH (RELOCATE = 1)
REGS in DACNT/DADRB = 1 REGS in DACNT/DADRB = 0 REGS in DACNT/DADRB = 1 FLSHE = 1 ROM
H'FEA7
DADRBL (RELOCATE = 1) DACNTL (RELOCATE = 1)
H'FEA8 H'FEA9 H'FEAA H'FEAC H'FEAD H'FEAE H'FEB0 H'FEB1
FCCS FPCS FECS FKEY FMATS FTDAR TSTR TSYR
MSTP1 = 0
TPU
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Section 25 List of Registers
Lower Address H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE
Register Abbreviation KBCR1_0 KBTR_0 KBCR1_1 KBTR_1 KBCR1_2 KBTR_2 TCRXY TCR_Y (RELOCATE = 1) TCSR_Y (RELOCATE = 1) TCORA_Y (RELOCATE = 1) TCORB_Y (RELOCATE = 1) TCNT_Y (RELOCATE = 1) TISR (RELOCATE = 1) ICDR_1 (RELOCATE = 1) SARX_1 (RELOCATE = 1)
Register selection condition MSTP2 = 0
Module KBU
MSTP8 = 0
TMR_XY TMR_Y
MSTP3 = 0
ICE in ICCR_1 = 1 ICE in ICCR_1 = 0 ICE in ICCR_1 = 1 ICE in ICCR_1 = 0
IIC_1
H'FECF
ICMR_1 (RELOCATE = 1) SAR_1 (RELOCATE = 1)
H'FED0 H'FED1 H'FED4 H'FED5 H'FED8 H'FED9 H'FEDA H'FEDB H'FEDC H'FEDD H'FEDE H'FEDF H'FEE0
ICCR_1 (RELOCATE = 1) ICSR_1 (RELOCATE = 1) ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCR2_0 KBCRH_1 KBCRL_1 KBBR_1 KBCR2_1 KBCRH_2 MSTP4 = 0 MSTP3 = 0 MSTP2 = 0 IIC_0 IIC_1 KBU
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Section 25 List of Registers
Lower Address H'FEE1 H'FEE2 H'FEE3 H'FEE4 H'FEE6 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEEE H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEF8 H'FEF9 H'FEFA H'FEFB H'FEFC H'FEFD H'FF82 H'FF83 H'FF84 H'FF85
Register Abbreviation KBCRL_2 KBBR_2 KBCR2_2 KBCOMP DDCSWR ICRA ICRB ICRC ISR ISCRH ISCRL DTCERA DTCERB DTCERC DTCERD DTCERE DTVECR ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L ISSR16 ISSR PCSR SYSCR2 SBYCR LPWRCR
Register selection condition MSTP2 = 0
Module KBU
No condition MSTP4 = 0, IICE in STCR = 1 No condition
IrDA IIC_0, IIC_1 INT
No condition
DTC
No condition
INT
No condition FLSHE in STCR = 0
PWM, PWMX SYSTEM
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Section 25 List of Registers
Lower Address H'FF86 H'FF87 H'FF88
Register Abbreviation MSTPCRH MSTPCRL SMR_1 (RELOCATE = 1) SMR_1 (RELOCATE = 0) ICCR_1 (RELOCATE = 0)
Register selection condition FLSHE in STCR = 0
Module SYSTEM
MSTP6 = 0 MSTP6 = 0, IICE in STCR = 0 MSTP3 = 0, IICE in STCR = 1 MSTP6 = 0 MSTP6 = 0, IICE in STCR = 0 MSTP3 = 0, IICE in STCR = 1 MSTP6 = 0
SCI_1
IIC_1 SCI_1
H'FF89
BRR_1 (RELOCATE = 1) BRR_1 (RELOCATE = 0) ICSR_1 (RELOCATE = 0)
IIC_1 SCI_1
H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E
SCR_1 TDR1 SSR_1 RDR_1
SCMR_1 (RELOCATE = 1) MSTP6 = 0 SCMR_1 (RELOCATE = 0) MSTP6 = 0, IICE in STCR = 0 ICDR_1 (RELOCATE = 0) SARX_1 (RELOCATE = 0) MSTP3 = 0, IICE in STCR = 1 ICE in ICCR1 = 1 ICE in ICCR1 = 0 ICE in ICCR1 = 1 ICE in ICCR1 = 0 MSTP13 = 0 FRT IIC_1
H'FF8F
ICMR_1 (RELOCATE = 0) SAR_1 (RELOCATE = 0)
H'FF90 H'FF91 H'FF92 H'FF94
TIER TCSR FRC OCRA OCRB
MSTP13 = 0
OCRS in TOCR = 0 OCRS in TOCR = 1
H'FF96 H'FF97 H'FF98
TCR TOCR ICRA OCRAR ICRS in TOCR = 0 ICRS in TOCR = 1 ICRS in TOCR = 0 ICRS in TOCR = 1 MSTP13 = 0 ICRS in TOCR = 0 ICRS in TOCR = 1 FRT
H'FF9A
ICRB OCRAF
H'FF9C
ICRC OCRDM
H'FF9E
ICRD
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Section 25 List of Registers
Lower Address H'FFA0
Register Abbreviation SMR_2 (RELOCATE = 1) SMR_2 (RELOCATE = 0)
Register selection condition MSTP5 = 0 MSTP5 = 0, IICE in STCR = 0
Module SCI_2
DADRAH (RELOCATE = 0) MSTP11 = 0, MSTPA1 = 0, IICE in STCR = 1 DACR (RELOCATE = 0) H'FFA1 BRR_2 (RELOCATE = 1) BRR_2 (RELOCATE = 0) MSTP5 = 0
REGS in PWMX DACNT/DADRB = 0 REGS in DACNT/DADRB = 1 SCI_2
MSTP5 = 0, IICE in STCR = 0 REGS in PWMX DACNT/DADRB = 0 SCI_2
DADRAL (RELOCATE = 0) MSTP11 = 0, MSTPA1 = 0, IICE in STCR = 1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 (RELOCATE = 1) MSTP5 = 0
SCMR_2 (RELOCATE = 0) MSTP5 = 0, IICE in STCR = 0 DADRBH (RELOCATE = 0) MSTP11 = 0, MSTPA1 = 0, IICE in STCR = 1 DACNTH (RELOCATE = 0) H'FFA7 DADRBL (RELOCATE = 0) DACNTL (RELOCATE = 0) H'FFA8 TCSR_0 TCNT_0 (write) H'FFA9 H'FFAA H'FFAB TCNT_0 (read) PAODR PAPIN (read) PADDR (write) H'FFAC H'FFAD H'FFAE P1PCR P2PCR P3PCR No condition PORT No condition REGS in PWMX DACNT/DADRB = 0 REGS in DACNT/DADRB = 1 REGS in DACNT/DADRB = 0 REGS in DACNT/DADRB = 1 WDT_0
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Section 25 List of Registers
Lower Address H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD
Register Abbreviation P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR P8DDR (write) PBPIN (read)
Register selection condition No condition
Module PORT
H'FFBE
P7PIN (read) PBDDR (write)
H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD
P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 MSTP12 = 0 TMR_0, TMR_1 No condition BSC No condition No condition INT SYSTEM
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Section 25 List of Registers
Lower Address H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 H'FFD4 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDE
Register Abbreviation TCORB TCORB_1 TCNT_0 TCNT_1 PWOERB PWDPRB PWSL PWDR 15 to 8 ICCR_0 (RELOCATE = 0) ICSR_0 (RELOCATE = 0) ICDR_0 (RELOCATE = 0) SARX_0 (RELOCATE = 0)
Register selection condition MSTP12 = 0
Module TMR_0, TMR_1
No condition
PWM
MSTP11 = 0 MSTPA0 = 0 MSTP4 = 0, IICE in STCR = 1 IIC_0
MSTP4 = 0, IICE in STCR = 1 MSTP4 = 0, IICE in STCR = 1 MSTP9 = 0
ICE in ICCR0 = 1 ICE in ICCR0 = 0 ICE in ICCR0 = 1 ICE in ICCR0 = 0 A/D Converter
H'FFDF
ICMR_0 (RELOCATE = 0) SAR_0 (RELOCATE = 0)
H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA
ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 (write)
No condition
WDT_1
H'FFEB H'FFF0
TCNT_1 (read) TCR_X (RELOCATE = 1) TCR_X (RELOCATE = 0) TCR_Y (RELOCATE = 0) MSTP8 = 0 MSTP8 = 0, KINWUE in STCR = 0 TMRX/Y in TCONRS =0 TMRX/Y in TCONRS TMR_Y =1 TMR_X
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Section 25 List of Registers
Lower Address H'FFF1
Register Abbreviation KMIMR (RELOCATE = 0) TCSR_X (RELOCATE = 1) TCSR_X (RELOCATE = 0) TCSR_Y (RELOCATE = 0)
Register selection condition MSTP2 = 0, KINWUE in STCR = 1 MSTP8 = 0 MSTP8 = 0, TMRX/Y in TCONRS KINWUE in SYSCR = 0 = 0
Module
TMRX/Y in TCONRS INT =1 TMR_X
TMRX/Y in TCONRS TMR_Y =1 MSTP2 = 0, KINWUE in SYSCR = 1 MSTP8 = 0 MSTP8 = 0, TMRX/Y in TCONRS KINWUE in SYSCR = 0 = 0 TMRX/Y in TCONRS TMR_Y =1 INT TMR_X TMRX/Y in TCONRS =0 TMRX/Y in TCONRS TMR_Y =1 MSTP8 = 0 MSTP8 = 0, KINWUE in SYSCR = 0 TMRX/Y in TCONRS =0 TMRX/Y in TCONRS TMR_Y =1 MSTP8 = 0 MSTP8 = 0, KINWUE in SYSCR = 0 TMRX/Y in TCONRS =0 TMRX/Y in TCONRS TMR_Y =1 TMR_X TMRX/Y in TCONRS =0 TMR_X TMRX/Y in TCONRS =1 TMR_X TMR_X PORT TMR_X
H'FFF2
KMPCR (RELOCATE = 0) TICRR (RELOCATE = 1) TICRR (RELOCATE = 0) TCORA_Y (RELOCATE = 0)
H'FFF3
KMIMRA (RELOCATE = 0) MSTP2 = 0, KINWUE in SYSCR = 1 TICRF (RELOCATE = 1) TICRF (RELOCATE = 0) TCORB_Y (RELOCATE = 0) MSTP8 = 0 MSTP8 = 0, KINWUE in SYSCR = 0
H'FFF4
TCNT_X (RELOCATE = 1) TCNT_X (RELOCATE = 0) TCNT_Y (RELOCATE = 0)
H'FFF5
TCORC (RELOCATE = 1) TCORC (RELOCATE = 0) TISR (RELOCATE = 0)
H'FFF6
TCORA_X (RELOCATE = 1) MSTP8 = 0 TCORA_X (RELOCATE = 0) MSTP8 = 0, KINWUE in SYSCR = 0
H'FFF7
TCORB_X (RELOCATE = 1) MSTP8 = 0 TCORB_X (RELOCATE = 0) MSTP8 = 0, KINWUE in SYSCR = 0
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Section 25 List of Registers
Lower Address H'FFFC
Register Abbreviation TCONRI (RELOCATE = 1) TCONRI (RELOCATE = 0)
Register selection condition MSTP8 = 0 MSTP8 = 0, KINWUE in SYSCR = 0
Module TMR_Y
H'FFFE
TCONRS (RELOCATE = 1) MSTP8 = 0 TCONRS (RELOCATE = 0) MSTP8 = 0, KINWUE in SYSCR = 0
TMR_X, TMR_Y
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Section 25 List of Registers
25.5
Module INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT BSC BSC DTC
Register Addresses (Classification by Type of Module)
Register name WUEMRB WUEMR KMIMR KMIMR KMIMRA KMIMRA ICRD ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L ISSR16 ISSR IER BCR WSCR DTCERA Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE44 H'FE45 H'FE81 (RELOCATE = 1) H'FFF1 (RELOCATE = 0) H'FE83 (RELOCATE = 1) H'FFF3 (RELOCATE = 0) H'FE87 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEF8 H'FEF9 H'FEFA H'FEFB H'FEFC H'FEFD H'FFC2 H'FFC6 H'FFC7 H'FEEE Data Initial value width H'FF H'FF H'BF H'BF H'FF H'FF H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'D3 H'F3 H'00 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
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Section 25 List of Registers
Module DTC DTC DTC DTC DTC PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT
Register name DTCERB DTCERC DTCERD DTCERE DTVECR P1PCR P1DDR P1DR P2PCR P2DDR P2DR P3PCR P3DDR P3DR P4DDR P4DR P5DR P5DDR P6NCE P6NCMC P6NCCS KMPCR KMPCR SYSCR2 P6DR P6DDR P7PIN P8DDR P8DR P9PCR
Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEEF H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FFAC H'FFB0 H'FFB2 H'FFAD H'FFB1 H'FFB3 H'FFAE H'FFB4 H'FFB6 H'FFB5 H'FFB7 H'FFBA H'FFB8 H'FE00 H'FE01 H'FE02 H'FE82 (RELOCATE = 1) H'FFF2 (RELOCATE = 0) H'FF83 H'FFBB H'FFB9 H'FFBE H'FFBD H'FFBF H'FE14
Data Initial value width H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'F8 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'80 H'80 H'00 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 934 of 986 REJ09B0098-0300
Section 25 List of Registers
Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT
Register name P9DDR P9DR PAODR PAPIN PADDR PBODR PBPIN PBDDR PCNCE PCNCMC PCNCCS PCNOCR PCODR PCPIN PCDDR PDNOCR PDODR PDPIN PDDDR PEPCR PEPIN PFNOCR PFDDR PFODR PFPIN PGNCE PGNCMC PGNCCS PGNOCR PGODR
Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFC0 H'FFC1 H'FFAA H'FFAB H'FFAB H'FFBC H'FFBD H'FFBE H'FE03 H'FE04 H'FE05 H'FE1C H'FE4C H'FE4E (Read) H'FE4E (Write) H'FE1D H'FE4D H'FE4F (Read) H'FE4F (Write) H'FE48
Data Initial value width H'00 H'00/H'40 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
H'FE4A (Read) (Writing prohibited) H'FE19 H'FE4B (Write) H'FE49 H'FE4B (Read) H'FE06 H'FE07 H'FE08 H'FE16 H'FE46 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00
Rev. 3.00 Jul. 14, 2005 Page 935 of 986 REJ09B0098-0300
Section 25 List of Registers
Module PORT PORT PORT PORT PORT PWM PWM PWM PWM PWM PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX
Register name PGPIN PGDDR PTCNT0 PTCNT1 PTCNT2 PWOERB PWDPRB PWSL PWDR 15 to 8 PCSR DACR DACR DADRAH DADRAH DADRAL DADRAL DACNTH DACNTH DADRBH DADRBH DACNTL DACNTL
Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE47 (Read) H'FE47 (Write) H'FE10 H'FE11 H'FE12 H'FFD2 H'FFD4 H'FFD6 H'FFD7 H'FF82 H'FEA0 (RELOCATE = 1) H'FFA0 (RELOCATE = 0) H'FEA0 (RELOCATE = 1) H'FFA0 (RELOCATE = 0) H'FEA1 (RELOCATE = 1) H'FFA1 (RELOCATE = 0) H'FEA6 (RELOCATE = 1) H'FFA6 (RELOCATE = 0) H'FEA6 (RELOCATE = 1) H'FFA6 (RELOCATE = 0) H'FEA7 (RELOCATE = 1) H'FFA7 (RELOCATE = 0)
Data Initial value width H'00 H'00 H'00 H'00 H'00 H'00 H'20 H'00 H'00 H'30 H'FF H'00 H'FF H'FF H'FF H'FF H'00 H'FF H'FF H'03 H'03 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 936 of 986 REJ09B0098-0300
Section 25 List of Registers
Module PWMX PWMX PWMX FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT FRT TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_1 TPU_1
Register name DADRBL DADRBL PCSR TIER TCSR FRC OCRA OCRB TCR TOCR ICRA OCRAR ICRB OCRAF ICRC OCRDM ICRD TCR_0 TMDR0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1
Number of bits Address 8 8 8 8 8 16 16 16 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8 H'FEA7 (RELOCATE = 1) H'FFA7 (RELOCATE = 0) H'FF82 H'FF90 H'FF91 H'FF92 H'FF94 H'FF94 H'FF96 H'FF97 H'FF98 H'FF98 H'FF9A H'FF9A H'FF9C H'FF9C H'FF9E H'FE50 H'FE51 H'FE52 H'FE53 H'FE54 H'FE55 H'FE56 H'FE58 H'FE5A H'FE5C H'FE5E H'FD40 H'FD41
Data Initial value width H'FF H'FF H'00 H'01 H'00 H'0000 H'FFFF H'FFFF H'00 H'00 H'0000 H'FFFF H'0000 H'FFFF H'0000 H'0000 H'0000 H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 8 8 8 8 8 16 16 16 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 937 of 986 REJ09B0098-0300
Section 25 List of Registers
Module TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU TPU TMR_0 TMR_0 TMR_0 TMR_0 TMR_0 TMR_1 TMR_1 TMR_1 TMR_1 TMR_1 TMR_X TMR_X TMR_X TMR_X TMR_X
Register name TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TSTR TSYR TCR_0 TCSR_0 TCORA_0 TCORB_0 TCNT_0 TCR_1 TCSR_1 TCORA_1 TCORB_1 TCNT_1 TCR_X TCSR_X TICRR TICRF TCNT_X
Number of bits Address 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FD42 H'FD44 H'FD45 H'FD46 H'FD48 H'FD4A H'FE70 H'FE71 H'FE72 H'FE74 H'FE75 H'FE76 H'FE78 H'FE7A H'FEB0 H'FEB1 H'FFC8 H'FFCA H'FFCC H'FFCE H'FFD0 H'FFC9 H'FFCB H'FFCD H'FFCF H'FFD1 H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4
Data Initial value width H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'00 H'00 H'00 H'00 H'FF H'FF H'00 H'00 H'FF H'FF H'FF H'00 H'00 H'00 H'00 H'00 H'00 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 16 16 16 8 16 16 16 16 8 8 8 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 938 of 986 REJ09B0098-0300
Section 25 List of Registers
Module TMR_X TMR_X TMR_X TMR_X TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_X, TMR_Y TMR_XY WDT_0 WDT_0 WDT_0 WDT_0
Register name TCORC TCORA_X TCORB_X TCONRI TCR_Y TCR_Y TCSR_Y TCSR_Y TCORA_Y TCORA_Y TCORB_Y TCORB_Y TCNT_Y TCNT_Y TISR TISRF TCONRS TCRXY TCSR_0 TCSR_0 TCNT_0 TCNT_0
Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFF5 H'FFF6 H'FFF7 H'FFFC H'FEC8 (RELOCATE = 1) H'FFF0 (RELOCATE = 0) H'FEC9 (RELOCATE = 1) H'FFF1 (RELOCATE = 0) H'FECA (RELOCATE = 1) H'FFF2 (RELOCATE = 0) H'FECB (RELOCATE = 1) H'FFF3 (RELOCATE = 0) H'FECC (RELOCATE = 1) H'FFF4 (RELOCATE = 0) H'FECD (RELOCATE = 1) H'FFF5 (RELOCATE = 0) H'FFFE H'FEC6 H'FFA8 (Write) H'FFA8 (Read) H'FFA8 (Write) H'FFA9 (Read)
Data Initial value width H'FF H'FF H'FF H'00 H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'00 H'00 H'FE H'FE H'00 H'00 H'00 H'00 H'00 H'00 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 16 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 939 of 986 REJ09B0098-0300
Section 25 List of Registers
Module WDT_1 WDT_1 WDT_1 WDT_1 IrDA SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_1 IIC_1 IIC_1
Register name TCSR_1 TCSR_1 TCNT_1 TCNT_1 KBCOMP SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ICXR_0 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 ICDR_1 SARX_1 ICMR_1
Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFEA (Write) H'FFEA (Read) H'FFEA (Write) H'FFEB (Read) H'FEE4 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FED4 H'FFD8 H'FFD9 H'FFDE H'FFDE H'FFDF H'FFDF H'FECE (RELOCATE = 1) H'FECE (RELOCATE = 1) H'FECF (RELOCATE = 1)
Data Initial value width H'00 H'00 H'00 H'00 H'00 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'01 H'00 H'01 H'00 H'00 H'01 H'00 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 940 of 986 REJ09B0098-0300
Section 25 List of Registers
Module IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1
Register name SAR_1 ICCR_1 ICSR_1 ICXR_1 ICCR_1 ICSR_1 ICDR_1 SARX_1 ICMR_1 SAR_1
Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FECF (RELOCATE = 1) H'FED0 (RELOCATE = 1) H'FED1 (RELOCATE = 1) H'FED5 H'FF88 (RELOCATE = 0) H'FF89 (RELOCATE = 0) H'FF8E (RELOCATE = 0) H'FF8E (RELOCATE = 0) H'FF8F (RELOCATE = 0) H'FF8F (RELOCATE = 0) H'FEE6 H'FEC0 H'FEC1 H'FED8 H'FED9 H'FEDA H'FEDB H'FEC2 H'FEC3 H'FEDC H'FEDD H'FEDE H'FEDF H'FEC4 H'FEC5
Data Initial value width H'00 H'01 H'00 H'00 H'01 H'00 H'01 H'00 H'00 H'0F H'00 H'FF H'70 H'70 H'00 H'F0 H'00 H'FF H'70 H'70 H'00 H'F0 H'00 H'FF 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
IIC_0, IIC_1 DDCSWR KBU_0 KBU_0 KBU_0 KBU_0 KBU_0 KBU_0 KBU_1 KBU_1 KBU_1 KBU_1 KBU_1 KBU_1 KBU_2 KBU_2 KBCR1_0 KBTR_0 KBCRH_0 KBCRL_0 KBBR_0 KBCR2_0 KBCR1_1 KBTR_1 KBCRH_1 KBCRL_1 KBBR_1 KBCR2_1 KBCR1_2 KBTR_2
Rev. 3.00 Jul. 14, 2005 Page 941 of 986 REJ09B0098-0300
Section 25 List of Registers
Module KBU_2 KBU_2 KBU_2 KBU_2 LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC
Register name KBCRH_2 KBCRL_2 KBBR_2 KBCR2_2 RBUFAR EBLKR LMCST1 LMCST2 LMCCR1 LMCCR2 MPCR HBAR1H HBAR1L HBAR2H HBAR2L RAMBARH RAMBARL ASSR RAMASSR SAR1 SAR2 FWPRH FWPRM FWPRL RAMAR FRPRH FRPRM FRPRL UCMDTR FLWARH FLWARL
Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEE0 H'FEE1 H'FEE2 H'FEE3 H'FDE0 H'FDE1 H'FDE2 H'FDE3 H'FDE4 H'FDE5 H'FDE6 H'FDE8 H'FDE9 H'FDEA H'FDEB H'FDEC H'FDED H'FDEE H'FDEF H'FDF0 H'FDF1 H'FDF2 H'FDF3 H'FDF4 H'FDF5 H'FDF6 H'FDF7 H'FDF8 H'FDF9 H'FDFA H'FDFB
Data Initial value width H'70 H'70 H'00 H'F0 H'EF H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'D0 H'FF H'FF H'FF H'00 H'00 H'00 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 942 of 986 REJ09B0098-0300
Section 25 List of Registers
Module LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC
Register name LMCMIDCR LMCDIDCR TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 IDR2 ODR2
Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FDFC H'FDFD H'FE20 H'FE20 H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE31 H'FE32 H'FE34 H'FE35 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A H'FE3C H'FE3D
Data Initial value width H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 943 of 986 REJ09B0098-0300
Section 25 List of Registers
Module LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter ROM
Register name STR2 HISEL HICR0 HICR1 HICR2 HICR3 LADR4H LADR4L IDR4 ODR4 STR4 HICR4 SIRQCR2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR FCCS
Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE3E H'FE3F H'FE40 H'FE41 H'FE42 H'FE43 H'FDD4 H'FDD5 H'FDD6 H'FDD7 H'FDD8 H'FDD9 H'FDDA H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FEA8
Data Initial value width H'00 H'03 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 944 of 986 REJ09B0098-0300
Section 25 List of Registers
Module ROM ROM ROM ROM ROM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM
Register name FPCS FECS FKEY FMATS FTDAR MSTPCRA SBYCR LPWRCR MSTPCRH MSTPCRL SYSCR3 STCR SYSCR MDCR SYSCR2
Number of bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEA9 H'FEAA H'FEAC H'FEAD H'FEAE H'FE7E H'FF84 H'FF85 H'FF86 H'FF87 H'FE7D H'FFC3 H'FFC4 H'FFC5 H'FF83
Data Initial value width H'00 H'00 H'00 H'00 H'00 H'01 H'00 H'3F H'FF H'00 H'00 H'09 H'00 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address states 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 Jul. 14, 2005 Page 945 of 986 REJ09B0098-0300
Section 25 List of Registers
Rev. 3.00 Jul. 14, 2005 Page 946 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
Section 26 Electrical Characteristics
26.1 Absolute Maximum Ratings
Table 26.1 lists the absolute maximum ratings. Table 26.1 Absolute Maximum Ratings
Item Power supply voltage* Symbol VCC Value -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.3 -0.3 to AVCC +0.3 -20 to +75 -20 to +75 -55 to +125 C Unit V
Input voltage (except port 7, A, G, P97, Vin P86, P52, and P42) Input voltage (port A, G, P97, P86, P52, Vin and P42) Input voltage (port 7) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Operating temperature (when flash memory is programmed or erased) Storage temperature Caution: Note: * Vin AVref AVCC VAN Topr Topr Tstg
Permanent damage to this LSI may result if absolute maximum ratings are exceeded. Make sure the applied power supply does not exceed 4.3V. Voltage applied to the VCC pin. The VCL pin should not be applied a voltage.
Rev. 3.00 Jul. 14, 2005 Page 947 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
26.2
DC Characteristics
Table 26.2 lists the DC characteristics. Table 26.3 lists the permissible output currents. Table 26.4 lists the bus drive characteristics. Table 26.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC*1 = 3.0 V to 3.6 V, AVref*1 = 3.0 V to AVCC, VSS = AVSS*1 = 0 V
Item Schmitt trigger input voltage P67 to P60(KWUL = 00)* , (1) 3 IRQ7 to IRQ0* , IRQ15 to IRQ8, KIN7 to KIN0, KIN15 to KIN8, WUE15 to WUE0, ExIRQ7 to ExIRQ0, and ExIRQ15 to ExIRQ8 P67 to P60(KWUL = 01)
2
Symbol Min. VT VT
-
Typ. Max. VCC x 0.7
Unit V
Test Conditions
VCC x 0.2
-
+
V T - VT
+
VCC x 0.05
Schmitt trigger input voltage (changin g levels)
VT VT
-
VCC x 0.3
-

VCC x 0.7 VCC x 0.8 VCC x 0.9 VCC + 0.3
+
V T - VT P67 to P60(KWUL = 10) VT VT
- +
+
VCC x 0.05 VCC x 0.4
V T - VT P67 to P60(KWUL = 11) VT VT RES, STBY, NMI, MD2, MD1, MD0, FWE, and ETRST EXTAL Port 7 Port A, G, P97, P86, P52, and P42 Input pins other than (1) and (2) above
- +
+
-
VCC x 0.03 VCC x 0.45
V T - VT Input high voltage (2) VIH
+
-
0.05 VCC x 0.9
VCC x 0.7 VCC x 0.7 VCC x 0.7 VCC x 0.7

VCC + 0.3 AVCC + 0.3 5.5 VCC + 0.3
Rev. 3.00 Jul. 14, 2005 Page 948 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
Item Input low RES, STBY, MD2, MD1, MD0, FWE, and ETRST voltage (3)
Symbol Min. VIL -0.3 -0.3 VOH VCC- 0.5 VCC- 1.0 0.5 VOL
Typ. Max. VCC x 0.1 VCC x 0.2 0.4 1.0
Unit
Test Conditions
NMI, EXTAL, and input pins other than (1) and (3) above Output high voltage All output pins (except for port A, G, P97, P86, P52, and P42) Port A, G, P97, P86, P52, and 4 P42* All output pins *
5
IOH = -200 A IOH = -1 mA IOH = -200 A IOL = 1.6 mA IOL = 5 mA
Output low voltage
Ports 1, 2, 3, C, and D
Rev. 3.00 Jul. 14, 2005 Page 949 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
Table 26.2 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC*1 = 3.0 V to 3.6 V, AVref*1 = 3.0 V to AVCC, VSS = AVSS*1 = 0 V
Item Input leakage current RES STBY, NMI, MD2, MD1, MD0, and FWE Port 7 Ports 1 to 6 Three-state leakage current (off Ports 8, 9, and A to G state) Input pull-up MOS current ITSI Symbol Min. Typ. Max. Unit Test Conditions Iin 10.0 A 1.0 1.0 1.0 Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to VCC - 0.5 V
Ports 1 to 3 and P95 to -IP P90 Port 6 (P6PUE=0), B to F Port 6 (P6PUE=1)
5 30 3
30
150 300 100 15 10 45 mA pF
Vin = 0 V
Input capacitance
P41, P40, PB7 to PB3, Cin and PC7 Other than above
Vin = 0 V f = 1MHz Ta = 25C VCC = 3.0 V to 3.6 V f = 20 MHz, all modules operating, high-speed mode VCC = 3.0 V to 3.6 V f = 20 MHz
Current 6 consumption*
Normal operation
ICC
Sleep mode
7

22
35
Standby mode*
10 1
40 80 2
A
Ta 50 C 50 C < Ta
Analog power supply current
During A/D conversion AIcc A/D conversion standby

mA A mA A V ms/V AVref = 3.0 V to AVCC AVCC = 3.0 V to 3.6 V
0.01 5 1 2
Reference power supply current
During A/D conversion AIref A/D conversion standby
0.01 5 0 0.8 20
VCC start voltage VCC rising edge
VCCSTART SVCC
Rev. 3.00 Jul. 14, 2005 Page 950 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used. Even if the A/D converter is not used, apply a value in the range from 3.0 V to 3.6 V to the AVCC and AVref pins by connection to the power supply (VCC). The relationship between these two pins should be AVref AVCC. 2. Includes peripheral module inputs multiplexed on the pin. 3. IRQ2 includes the ADTRG input multiplexed on the pin. 4. Ports A, G, P97, P86, P52, P42, and peripheral module outputs multiplexed on the pin are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0, SCL1, SDA0, SDA1, ExSCLA, ExSCLB, ExSDAA, and ExSDAB (ICE bit in ICCR is 1). Ports A, G, P97, P86/SCK1, P52, and P42/SCK2 (ICE bit in ICCR is 0) high levels are driven by NMOS. An external pull-up resistor is necessary to provide high-level output from these pins when they are used as an output. 5. Indicates values when ICCS = 0, ICE = 0, and KBIOE = 0. Low level output when the bus drive function is selected is rated separately. 6. Current consumption values are for VIH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state.
Table 26.2 DC Characteristics (3) Using LPC Function Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V
Item Input high voltage Input low voltage P37 to P30 P83 to P80, PB1, PB0 P37 to P30 P83 to P80, PB1, PB0 Symbol Min. VIH VIL VOH VOL VCC x 0.5 VCC x 0.9 Max. VCC x 0.3 VCC x0.1 Unit V V V V IOH = -0.5 mA IOL = 1.5 mA Test Conditions
Output high voltage P37, P33 to P30, P82 to P80. PB1, PB0 Output low voltage P37, P33 to P30, P82 to P80. PB1, PB0
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Section 26 Electrical Characteristics
Table 26.3 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, VSS = 0V
Item Permissible output low current (per pin) SCL0, SDA0, SCL1, SDA1, ExSCLA, ExSDAA, ExSCLB, ExSDAB, PS2AC to PS2CC, PS2AD to PS2CD, and PA7 to PA4 (bus drive function selected) Ports 1, 2, 3, C, and D Other output pins Permissible output low current (total) Total of ports 1, 2, 3, C, and D IOL Total of all output pins, including the above -IOH -IOH Symbol Min. IOL Typ. Max. 10 Unit mA

5 2 40 60 2 30
Permissible output All output pins high current (per pin) Permissible output high current (total) Total of all output pins
Notes: 1. To protect LSI reliability, do not exceed the output current values in table 26.3. 2. When driving a Darlington transistor or LED, always insert a current-limiting resistor in the output line, as show in figures 26.1 and 26.2.
Rev. 3.00 Jul. 14, 2005 Page 952 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
Table 26.4 Bus Drive Characteristics Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V Applicable Pins: SCL0, SDA0, SCL1, SDA1, ExSCLA, ExSDAA, ExSCLB, and ExSDAB (bus drive function selected)
Item Schmitt trigger input voltage Symbol VT VT
- +
Min.
VCC x 0.3
Typ. Max.
VCC x 0.7
Unit V
Test Conditions
-
VT - VT Input high voltage Input low voltage Output low voltage VIH VIL VOL Cin ITSI
+
VCC x 0.05 VCC x 0.7
5.5
VCC x 0.3
- 0.5
0.5 0.4 10 1.0 pF A
IOL = 8 mA IOL = 3 mA Vin = 0 V, f = 1 MHz, Ta = 25C Vin = 0.5 to VCC - 0.5 V
Input capacitance Three-state leakage current (off state)
Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V Applicable Pins: PS2AC to PS2CC, PS2AD to PS2CD, and PA7 to PA4 (bus drive function selected)
Item Output low voltage Symbol VOL Min. Typ. Max. 0.8 0.5 0.4 Unit V Test Conditions IOL = 16mA IOL = 8 mA IOL = 3 mA
Rev. 3.00 Jul. 14, 2005 Page 953 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
This LSI
2 k
Port
Darlington transistor
Figure 26.1 Darlington Transistor Drive Circuit (Example)
This LSI
600 Ports 1 to 3 LED
Figure 26.2 LED Drive Circuit (Example)
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Section 26 Electrical Characteristics
26.3
AC Characteristics
Figure 26.3 shows the test conditions for the AC characteristics.
3V C = 30pF : All ports RL = 2.4 k RH = 12 k I/O timing test levels * Low level : 0.8 V * High level : 1.5 V
RL LSI output pin C RH
Figure 26.3 Output Load Circuit
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Section 26 Electrical Characteristics
26.3.1
Clock Timing
Table 26.5 shows the clock timing. The clock timing specified here covers clock output () and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 23, Clock Pulse Generator. Table 26.5 Clock Timing Condition A: Condition B: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 4 MHz to 10 MHz VCC = 3.0 V to 3.6 V, VSS = 0 V, = 4 MHz to 20 MHz
Condition A Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Reset oscillation stabilization (crystal) Symbol Min. tcyc tCH tCL tCr tCf tOSC1 100 30 30 20 8 Max. 250 20 20 Condition B Min. 50 20 20 10 8 Max. 250 5 5 ms Figure 26.5 Figure 26.6 Unit ns Reference Figure 26.4
Software standby tOSC2 oscillation stabilization time (crystal) External clock output stabilization delay time tDEXT
500
500
s
Figure 26.5
tcyc tCH tCf
tCL
tCr
Figure 26.4 System Clock Timing
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Section 26 Electrical Characteristics
EXTAL tDEXT VCC tDEXT
STBY
tOSC1 RES
tOSC1
Figure 26.5 Oscillation Stabilization Timing
NMI IRQi ( i = 0 to 15 ) KINi ( i = 0 to 15 ) WUEi ( i = 0 to 15 ) PS2AC to PS2CC tOSC2
Figure 26.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)
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Section 26 Electrical Characteristics
26.3.2
Control Signal Timing
Table 26.6 shows the control signal timing. Only external interrupts NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE0 to WUE15, and KBCA to KBCC can be operated based on the subclock (SUB = 32.768 kHz). Table 26.6 Control Signal Timing Conditions:
Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time (IRQ15 to IRQ0, KIN15 to KIN0, WUE15 to WUE0) IRQ hold time (IRQ15 to IRQ0, KIN15 to KIN0, WUE15 to WUE0) IRQ pulse width (IRQ15 to IRQ0, KIN15 to KIN0, WUE15 to WUE0) (exiting software standby mode)
VCC = 3.0 V to 3.6 V, VSS = 0 V, = 32.768 kHz, 4 MHz to 20 MHz
Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS Min. 200 20 150 10 200 150 Max. Unit ns tcyc ns Figure 26.8 Test Conditions Figure 26.7
tIRQH
10
tIRQW
200
tRESS RES tRESW tRESS
Figure 26.7 Reset Input Timing
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Section 26 Electrical Characteristics
tNMIS
NMI tNMIW
tNMIH
IRQi (i = 0 to 15)
tIRQW tIRQS
tIRQH
IRQ Edge input
tIRQS
IRQ Level input
KINi (i = 0 to 15) WUEi (i = 0 to 15)
tIRQS
tIRQH
tIRQW
Figure 26.8 Interrupt Input Timing 26.3.3 Timing of On-Chip Peripheral Modules
Tables 26.7 to 26.9 show the on-chip peripheral module timing. The on-chip peripheral modules that can be operated by the subclock ( = 32.768 kHz) are I/O ports, external interrupts (NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE0 to WUE15, and KBCA to KBCC), watchdog timer, and 8-bit timer (channels 0 and 1) only.
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Section 26 Electrical Characteristics
Table 26.7 Timing of On-Chip Peripheral Modules Conditions:
Item I/O ports Output data delay time Input data setup time Input data hold time FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges PWM, PWMX Timer output delay time SCI Input clock cycle Asynchronous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time WDT RESO output delay time RESO output pulse width tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS tRESD tRESOW
VCC = 3.0 V to 3.6 V, VSS = 0 V, SUB = 32.768 kHz*, = 4 MHz to 20 MHz
Symbol tPWD tPRS tPRH tFTOD tFTIS tFTCS tFTCWH tFTCWL tTOCD tTICS tTCKS tTCKWH tTCKWL tTMOD tTMRS tTMCS tTMCWH tTMCWL tPWOD tScyc Min. 30 30 30 30 1.5 2.5 30 30 1.5 2.5 30 30 1.5 2.5 4 6 0.4 50 50 30 132 Max. 50 50 50 50 50 0.6 1.5 1.5 50 100 ns ns tcyc Figure 26.20 Figure 26.21 ns Figure 26.19 tScyc tcyc ns tcyc Figure 26.17 Figure 26.18 tcyc ns Figure 26.14 Figure 26.16 Figure 26.15 tcyc Figure 26.13 ns Figure 26.12 tcyc Figure 26.11 ns Figure 26.10 Unit ns Test Conditions Figure 26.9
Note:
*
Applied only for the peripheral modules that are available during subclock operation.
Rev. 3.00 Jul. 14, 2005 Page 960 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
T1
T2
tPRS Ports 1 to 9 and A to G (read)
tPRH
tPWD Ports 1 to 6, 8, 9, A to D, F, and G (write)
Figure 26.9 I/O Port Input/Output Timing
tFTOD FTOA, FTOB
tFTIS FTIA, FTIB, FTIC, FTID
Figure 26.10 FRT Input/Output Timing
tFTCS FTCI tFTCWL tFTCWH
Figure 26.11 FRT Clock Input Timing
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Section 26 Electrical Characteristics
tTOCD Output compare outputs tTICS Input capture inputs Note:* TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, and TIOCD0
Figure 26.12 TPU Input/Output Timing
tTCKS TCLKS to TCLKD tTCKWL tTCKWH tTCKS
Figure 26.13 TPU Clock Input Timing
tTMOD TMO_0, TMO_1 TMO_X, TMO_Y
Figure 26.14 8-Bit Timer Output Timing
tTMCS TMI_0, TMI_1 TMI_X, TMI_Y tTMCWL tTMCWH tTMCS
Figure 26.15 8-Bit Timer Clock Input Timing
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Section 26 Electrical Characteristics
tTMRS TMI_0, TMI_1 TMI_X, TMI_Y
Figure 26.16 8-Bit Timer Reset Input Timing
tPWOD PW15 to PW8, PWX1 to PWX0
Figure 26.17 PWM, PWMX Output Timing
tSCKW tSCKr tSCKf
SCK1 to SCK2
tScyc
Figure 26.18 SCK Clock Input Timing
SCK1 to SCK2 tTXD TxD1 to TxD2 (transmit data) tRXS RxD1 to RxD2 (receive data) tRXH
Figure 26.19 SCI Input/Output Timing (Clock Synchronous Mode)
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Section 26 Electrical Characteristics
tTRGS ADTRG
Figure 26.20 A/D Converter External Trigger Input Timing
tRESD RESO
tRESD
tRESOW
Figure 26.21 WDT Output Timing (RESO) Table 26.8 KBU Bus Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 4 MHz to 20 MHz
Standard Value Item KCLK, KD output fall time KCLK, KD input data hold time Symbol Min. tKBF tKBIH tKBOD Cb 20 + 0.1 Cb 150 150 Test Typ. Max. Unit Conditions Remarks 450 400 pF ns Figure 26.22
KCLK, KD input data setup time tKBIS KCLK, KD output delay time KCLK, KD capacitive load Note: *
When KCLK and KD are output, an external pull-up register must be connected, as shown in figure 26.22.
Rev. 3.00 Jul. 14, 2005 Page 964 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
receive tKBIS KCLK/KD* tKBIH
transmit (a) tKBOD KCLK/KD*
transmit (b) KCLK/KD* tKBF Note: shown in this figure is divided by 1/N when the operating mode is medium-speed mode. KCLK : PS2AC to PS2CC KD : PS2AD to PS2CD
Figure 26.22 Keyboard Buffer Control Unit Timing
Rev. 3.00 Jul. 14, 2005 Page 965 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
Table 26.9 I2C Bus Timing Conditions:
Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA output fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Note: *
VCC = 3.0 V to 3.6 V, VSS = 0 V, = 4 MHz to 20 MHz
Test Conditions Symbol tSCL tSCLH tSCLL tSr tSf tOf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min. 12 3 5 20 + 0.1 Cb 5 3 3 3 0.5 0 Typ. Max. 7.5* 300 250 1 400 ns pF tcyc ns Unit tcyc Figure 26.23
17.5 tcyc can be set according to the clock selected for use by the I2C module.
Rev. 3.00 Jul. 14, 2005 Page 966 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
SDA0 SDA1
VIH VIL tBUF tSTAH
tSCLH
tSTAS
tSP
tSTOS
SCL0 SCL1 P* S* tSf tSCLL tSCL tSr tSDAH Sr* tSDAS P*
Note: * S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Retransmission start condition
Figure 26.23 I2C Bus Interface Input/Output Timing Table 26.10 LPC Timing Conditions:
Item Input clock cycle Input clock pulse width (H) Input clock pulse width (L) Transmit signal delay time Transmit signal floating delay time Receive signal setup time Receive signal hold time
VCC = 3.0 V to 3.6V, VSS = 0 V, = 4 MHz to 20 MHz
Symbol tLcyc tLCKH tLCKL tTXD tOFF tRXS tRXH Min. 30 11 11 2 7 0 Typ. Max. 11 28 Unit ns Test Conditions Figure 26.24
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Section 26 Electrical Characteristics
tLCKH
tLcyc
LCLK
tLCKL LCLK tTXD LAD3 to LAD0, SERIRQ, CLKRUN (transmit signal) tRXS LAD3 to LAD0, SERIRQ, CLKRUN, LFRAME (receive signal) tOFF LAD3 to LAD0, SERIRQ, CLKRUN (transmit signal) tRXH
Figure 26.24 LPC Interface Timing
Test voltage: 0.4Vcc
50 pF
Figure 26.25 Test Conditions for Tester
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Section 26 Electrical Characteristics
Table 26.11 JTAG Timing Conditions:
Item ETCK clock cycle time ETCK clock high pulse width ETCK clock low pulse width ETCK clock rise time ETCK clock fall time ETRST pulse width Reset hold transition pulse width ETMS setup time ETMS hold time ETDI setup time ETDI hold time ETDO data delay time Note: * When tcyc tTCKcyc
VCC = 3.0 V to 3.6 V, VSS = 0 V, = 4 MHz to 20 MHz
Symbol tTCKcyc tTCKH tTCKL tTCKr tTCKf tTRSTW tRSTHW tTMSS tTMSH tTDIS tTDIH tTDOD Min. 50* 20 20 20 3 20 20 20 20 Max. 250* 5 5 20 ns Figure 26.28 tcyc Figure 26.27 Unit ns Test Conditions Figure 26.26
tTCKcyc
tTCKH
tTCKf
ETCK
tTCKL tTCKr
Figure 26.26 JTAG ETCK Timing
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Section 26 Electrical Characteristics
ETCK RES
tRSTHW
ETRST
tTRSTW
Figure 26.27 Reset Hold Timing
ETCK
tTMSS tTMSH
ETMS
tTDIS tTDIH
ETDI
tTDOD
ETDO (Six instructions defined in IEEE1149.1) ETDO (Other instructions)
tTDOD
Figure 26.28 JTAG Input/Output Timing
Rev. 3.00 Jul. 14, 2005 Page 970 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
26.3.4
A/D Conversion Characteristics
Table 26.12 lists the A/D conversion characteristics. Table 26.12 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC VSS = AVSS = 0 V, = 4 MHz to 16 MHz VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 4 MHz to 20 MHz
Condition A Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min. Typ. 10 8.38* 20 5
1
Condition B:
Condition B Min. Typ. 10 13.4* 20 5
2
Max.
Max.
Unit Bits s pF k
7.0 7.5 7.5 0.5 8.0
7.0 7.5 7.5 0.5 8.0
LSB
Notes: 1. Value when using the maximum operating frequency in single mode of 134 states. 2. Value when using the maximum operating frequency in single mode of 266 states.
Rev. 3.00 Jul. 14, 2005 Page 971 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
26.4
Flash Memory Characteristics
Table 26.13 lists the flash memory characteristics. Table 26.13 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Avref = 3.0 V to AVCC, VSS = AVSS = 0 V Ta = 0C to +75C (operating temperature range for programming/erasing)
Symbol Min.
124
Item Programming time* * * Erase time* * *
124
Typ. 3 80 500 1000 20 20 40
3
Max. 30 800 5000 10000 60 60 120
Unit ms/128 bytes ms/4-kbyte block ms/32-kbyte block ms/64-kbyte block s/1 Mbyte s/1 Mbytes s/1 Mbytes Times Years
Test Conditions
tP tE

Programming time 124 (total)* * * Erase time (total)* * *
124
tP tE tPE NWEC tDRP
100* 10
Ta = 25C Ta = 25C Ta = 25C
Programming and Erase 124 time (total)* * * Reprogramming count Data retention time*
4
Notes: 1. Programming and erase time depends on the data. 2. Programming and erase time do not include data transfer time. 3 This value indicates the minimum number of which the flash memory are reprogrammed with all characteristics guaranteed. (The guaranteed value ranges from 1 to the minimum number.) 4. This value indicates the characteristics while the flash memory is reprogrammed within the specified range (including the minimum number).
Rev. 3.00 Jul. 14, 2005 Page 972 of 986 REJ09B0098-0300
Section 26 Electrical Characteristics
26.5
Usage Notes
It is necessary to connect a bypass capacitor between the VCC pin and VSS pin, and a capacitor between the VCL pin and VSS pin for stable internal step-down power. An example of connection is shown in figure 26.29.
Vcc power supply External capacitor for internal step-down power stabilization One 0.1 F / 0.47 F or two in parallel VSS VSS
Bypass capacitor
VCC
VCL
10 F
0.01 F
It is recommended that a bypass capacitor be connected to the VCC pin. (The values are reference values.) When connecting, place a bypass capacitor near the pin.
Do not connect Vcc power supply to the VCL pin. Always connect a capacitor for internal step-down power stabilization. Use one or two ceramic multilayer capacitor(s) (0.1 F / 0.47 F: connect in parallel when using two) and place it (them) near the pin.
Figure 26.29 Connection of VCL Capacitor
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Section 26 Electrical Characteristics
Rev. 3.00 Jul. 14, 2005 Page 974 of 986 REJ09B0098-0300
Appendix
Appendix
A. I/O Port States in Each Pin State
I/O Port States in Each Pin State
MCU Operating Mode 2, 3 2, 3 2, 3 2, 3 2, 3 Hardware Software Standby Standby Mode Mode T T T T T keep keep keep keep keep Watch Mode keep keep keep keep ExEXCL input /keep Port 51, 52 Port 6 Port 7, E Port 8 Port 97 Port 96 , EXCL Port 95 to 90 2, 3 Port A to D, F, G 2, 3 T T T T keep keep keep keep keep keep keep keep I/O port I/O port I/O port I/O port 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 T T T T T T T T T T T T keep keep T keep keep [DDR = 1]H [DDR = 0]T keep keep T keep keep EXCL input/ keep keep keep T keep keep [DDR = 1] Clock output [DDR = 0]T Sleep Mode keep keep keep keep keep SubSleep Mode keep keep keep keep ExEXCL input/ keep keep keep T keep keep EXCL input/ keep SubActive Mode I/O port I/O port I/O port I/O port Program Execution State I/O port I/O port I/O port I/O port
Table A.1
Port Name Pin Name Port 1 Port 2 Port 3 Port 4 Port 50 ExEXCL
Reset T T T T T
ExEXCL ExEXCL input/ I/O port I/O port I/O port input/ I/O port I/O port I/O port
Input port Input port I/O port I/O port EXCL input/ I/O port I/O port Clock output/ EXCL input/
Input port input port
[Legend] H: High level L: Low level T: High impedance keep: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, the input pull-up MOS remains on). Output ports maintain their previous state. Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port function determined by DDR and DR. DDR: Data direction register
Rev. 3.00 Jul. 14, 2005 Page 975 of 986 REJ09B0098-0300
Appendix
B.
Product Lineup
Type Code R4F2114R Mark Code F2114RVTE20 Package (Code) PTQP0144LC-A (TFP-144) F-ZTAT version
Product Type H8S/2114R
Rev. 3.00 Jul. 14, 2005 Page 976 of 986 REJ09B0098-0300
Appendix
C.
Package Dimensions
For package dimensions, dimensions described in Renesas Semiconductor Packages Data Book have priority.
JEITA Package Code P-TQFP144-16x16-0.40 RENESAS Code PTQP0144LC-A Previous Code TFP-144/TFP-144V MASS[Typ.] 0.6g
HD
*1
D
108 109
73 72
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
b1
Reference Symbol
Dimension in Millimeters Min Nom 16 16 1.00 17.8 17.8 18.0 18.0 18.2 18.2 1.20 0.05 0.13 0.10 0.18 0.16 0.12 0.17 0.15 0 0.4 0.07 0.08 1.0 1.0 0.4 0.5 1.0 0.6 8 0.22 0.15 0.23 Max
*2
c1
c
D E
ZE
A2
144 1 ZD Index mark 36
37
Terminal cross section
HD HE A A1 bp
F
b1 c
A
A2
c1
c
e
*3
e x y ZD ZE L L1
y
bp
x
M
A1
L L1
Detail F
Figure C.1 Package Dimensions (TFP-144)
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Appendix
Rev. 3.00 Jul. 14, 2005 Page 978 of 986 REJ09B0098-0300
Index
Numerics
14-bit PWM timer (PWMX)................... 259 16-bit count mode................................... 402 16-bit free-running timer (FRT) ............. 277 16-bit timer pulse unit............................. 305 8-bit PWM timer (PWM)........................ 247 8-bit timer (TMR) ................................... 377 Bit rate..................................................... 445 Block data transfer instructions................. 46 Block transfer mode ................................ 150 Boot mode............................................... 764 Boundary scan......................................... 844 Boundary scan (JTAG) ........................... 827 Branch instructions ................................... 44 BRR ................ 445, 891, 904, 916, 927, 940 Buffer operation ...................................... 343 Bus arbitration......................................... 132 Bus controller (BSC)............................... 129
A
A/D conversion time............................... 724 A/D converter ......................................... 717 A/D converter activation......................... 359 A20 gate.................................................. 680 ABRKCR...........85, 890, 904, 915, 926, 933 Absolute address....................................... 49 Activation by interrupt............................ 155 Activation by software............................ 155 ADCR ..............722, 895, 907, 919, 930, 944 ADCSR............721, 895, 907, 919, 930, 944 Additional pulse...................................... 255 ADDR..............720, 894, 907, 919, 930, 944 Address map ............................................. 67 Address space ........................................... 26 Addressing modes..................................... 48 ADI ......................................................... 727 Arithmetic operations instructions............ 38 ASSR ...............668, 884, 898, 910, 920, 942
C
Carrier frequency .................................... 250 Cascaded connection............................... 402 Chain transfer.......................................... 151 Clock pulse generator ............................. 849 Clocked synchronous mode .................... 472 CMI......................................................... 406 CMIA ...................................................... 406 CMIAY ................................................... 406 CMIB ...................................................... 406 CMIBY ................................................... 406 Communications protocol ....................... 799 Compare-match count mode ................... 402 Condition field .......................................... 47 Condition-code register............................. 30 Conversion cycle..................................... 269 CPU........................................................... 19 CPU operating modes ............................... 22 CRA ........................................................ 140 CRB ........................................................ 140 Crystal resonator ..................................... 850
B
BARA ................86, 890, 904, 915, 926, 933 BARB ................86, 890, 904, 915, 926, 933 BARC ................86, 890, 904, 915, 926, 933 Basic pulse.............................................. 254 BCR .................130, 894, 906, 918, 929, 933 Bit manipulation instructions.................... 42
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D
DACNT ...........261, 888, 902, 913, 924, 936 DACR..............264, 888, 902, 913, 928, 936 DADRA...........262, 888, 892, 902, 928, 936 DADRB ...........263, 888, 892, 902, 928, 936 DAR........................................................ 140 Data direction register ............................ 159 Data register............................................ 159 Data transfer controller (DTC) ............... 135 Data transfer instructions.......................... 37 DDCSWR........530, 890, 903, 915, 926, 941 Direct transitions .................................... 878 Download pass/fail result parameter....... 754 DTC vector table .................................... 144 DTCERA .........141, 890, 903, 915, 926, 933 DTCERB .........141, 890, 903, 915, 926, 934 DTCERC .........141, 890, 903, 915, 926, 934 DTCERD .........141, 890, 903, 915, 926, 934 DTCERE .........141, 890, 903, 915, 926, 934 DTVECR .........142, 890, 903, 915, 926, 934
Flash MAT configuration ....................... 739 Flash multipurpose address area parameter ................................................ 758 Flash multipurpose data destination area parameter ................................................ 758 Flash pass/fail result parameter............... 762 Flash programming/erasing frequency control parameter .................................... 756 FLWAR .......... 655, 884, 898, 910, 921, 942 FMATS ........... 751, 888, 902, 913, 924, 945 FOVI ....................................................... 298 FPCS ............... 749, 888, 902, 913, 924, 945 Framing error .......................................... 462 FRC................. 280, 891, 904, 916, 927, 937 Free-running count operation.................. 336 FRPR .............. 674, 884, 898, 910, 921, 942 FTDAR ........... 752, 888, 902, 913, 924, 945 FWPR ............. 672, 884, 898, 910, 921, 942
G
General registers ....................................... 28
E
EBLKR............657, 883, 897, 909, 920, 942 Effective address ...................................... 52 Effective address extension ...................... 47 ERI1........................................................ 496 ERI2........................................................ 496 ERRI....................................................... 710 Error protection ...................................... 793 Exception handling ................................... 69 Exception handling vector table ......... 70, 72 Extended control register.......................... 29 External clock......................................... 851 External trigger....................................... 726
H
Hardware protection ............................... 791 Hardware standby mode ......................... 874 HBAR ............. 665, 883, 897, 909, 920, 942 HICR0............. 619, 886, 900, 912, 922, 944 HICR1............. 622, 886, 900, 912, 923, 944 HICR2............. 625, 886, 900, 912, 923, 944 HICR3............. 628, 886, 900, 912, 923, 944 HISEL ............. 653, 886, 900, 912, 922, 944 Host interface LPC interface (LPC)........ 613
F
FCCS ...............746, 888, 902, 913, 924, 944 FECS ...............749, 888, 902, 913, 924, 945 FKEY...............750, 888, 902, 913, 924, 945 Flash erase block select parameter ......... 761
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I
I/O ports .................................................. 159 I2C bus data format ................................. 535 I2C bus interface (IIC)............................. 505 ICCR ............... 517, 894, 914, 918, 930, 940 ICDR............... 510, 894, 907, 918, 930, 940
ICIA........................................................ 298 ICIB ........................................................ 298 ICIC ........................................................ 298 ICID........................................................ 298 ICIX........................................................ 406 ICMR...............514, 894, 907, 919, 930, 940 ICRA..................83, 890, 903, 915, 926, 933 ICRB..................83, 890, 903, 915, 926, 933 ICRC..................83, 890, 903, 915, 926, 933 ICRD..................83, 888, 901, 913, 924, 933 ICSR ................526, 894, 907, 918, 930, 940 ICXR................531, 889, 903, 914, 925, 940 IDR ..................632, 883, 897, 909, 920, 944 IER.....................90, 893, 906, 918, 929, 933 IER16.................90, 890, 904, 915, 926, 933 IICI ......................................................... 569 Immediate ................................................. 50 Input capture ........................................... 292 Input capture function............................. 339 Input capture operation ........................... 404 Input pull-up MOSs ................................ 159 Instruction set ........................................... 35 Interface.................................................. 427 Internal block diagram................................ 3 Interrupt control modes........................... 109 Interrupt controller.................................... 79 Interrupt exception handling..................... 76 Interrupt exception handling sequence ................................................. 117 Interrupt exception handling vector table ........................................................ 102 Interrupt mask bit...................................... 30 Interval timer mode................................. 421 IrDA........................................................ 492 IRQ15 to IRQ0 interrupts ......................... 99 ISCR16H ...........87, 890, 904, 915, 926, 933 ISCR16L............88, 891, 904, 915, 926, 933 ISCRH ...............89, 890, 903, 915, 926, 933 ISCRL................89, 890, 903, 915, 926, 933 ISR.....................91, 890, 903, 915, 926, 933
ISR16 ................ 91, 890, 904, 915, 926, 933 ISSR.................. 97, 891, 904, 916, 926, 933 ISSR16 .............. 97, 891, 904, 916, 926, 933
K
KBBR ............. 592, 889, 903, 914, 925, 941 KBCOMP........ 453, 890, 903, 915, 926, 940 KBCR1............ 585, 888, 902, 914, 925, 941 KBCR2............ 587, 890, 903, 914, 925, 941 KBCRH........... 588, 889, 903, 914, 925, 941 KBCRL ........... 590, 889, 903, 914, 925, 941 KBTR.............. 592, 888, 902, 914, 925, 941 Keyboard buffer controller...................... 581 KIN15 to KIN0 interrupts ....................... 100 KMIMR ............ 93, 888, 895, 901, 913, 924 KMIMRA.......... 93, 888, 895, 901, 913, 924 KMPCR .......... 181, 888, 901, 913, 924, 934
L
LADR3.... 628, 629, 886, 899, 911, 922, 943 LADR4............ 631, 883, 897, 909, 920, 944 List of registers ....................................... 881 LMCCR .......... 662, 883, 897, 909, 920, 942 LMCST ........... 658, 883, 897, 909, 920, 942 Logic operations instructions .................... 40 LPWRCR ........ 862, 891, 904, 916, 926, 945 LSI internal states in each operating mode ....................................................... 868
M
MDCR............... 60, 894, 906, 918, 929, 945 Medium-speed mode............................... 870 Memory indirect........................................ 51 Mode comparison.................................... 738 Mode transition diagram ......................... 867 Module stop mode................................... 878
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MPCR..............676, 883, 897, 909, 920, 942 MRA....................................................... 138 MRB ....................................................... 139 MSTPCRA ......865, 887, 901, 913, 924, 945 MSTPCRH ......864, 891, 904, 916, 927, 945 MSTPCRL.......864, 891, 904, 916, 927, 945 Multiprocessor communication function................................................... 466
N
NMI interrupt............................................ 99 Noise canceler ........................................ 567 Normal mode ............................ 22, 148, 156 Number of DTC execution states ........... 154
O
OCIA ...................................................... 298 OCIB ...................................................... 298 OCR........................................................ 927 OCRA..............280, 891, 904, 916, 927, 937 OCRAF............281, 892, 905, 916, 927, 937 OCRAR ...........281, 892, 905, 916, 927, 937 OCRB ..............280, 892, 904, 916, 927, 937 OCRDM ..........281, 892, 905, 916, 927, 937 ODR.........633, 883, 897, 909, 920, 922, 943 On-board programming .......................... 764 On-board programming mode ................ 735 Operating modes....................................... 59 Operation field.......................................... 47 Output compare ...................................... 291 Overflow................................................. 420 Overrun error .......................................... 462 OVI......................................................... 406 OVIY ...................................................... 406
P
P1DDR ............164, 893, 905, 917, 929, 934
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P1DR............... 165, 893, 905, 917, 929, 934 P1PCR............. 165, 893, 905, 917, 928, 934 P2DDR............ 167, 893, 905, 917, 929, 934 P2DR............... 168, 893, 905, 917, 929, 934 P2PCR............. 168, 893, 905, 917, 928, 934 P3DDR............ 171, 893, 905, 917, 929, 934 P3DR............... 172, 893, 906, 917, 929, 934 P3PCR............. 172, 893, 905, 917, 928, 934 P4DDR............ 174, 893, 906, 917, 929, 934 P4DR............... 175, 893, 906, 917, 929, 934 P5DDR............ 178, 893, 906, 917, 929, 934 P5DR............... 178, 893, 906, 917, 929, 934 P6DDR............ 180, 893, 906, 917, 929, 934 P6DR............... 181, 893, 906, 917, 929, 934 P6NCCS.......... 183, 884, 898, 910, 921, 934 P6NCE ............ 182, 884, 898, 910, 921, 934 P6NCMC ........ 182, 884, 898, 910, 921, 934 P7PIN.............. 189, 893, 906, 918, 929, 934 P8DDR............ 191, 893, 906, 917, 929, 934 P8DR............... 192, 893, 906, 918, 929, 934 P9DDR............ 196, 893, 906, 918, 929, 935 P9DR............... 197, 893, 906, 918, 929, 935 P9PCR............. 197, 885, 899, 910, 921, 934 PADDR........... 201, 893, 905, 917, 928, 935 PAODR........... 202, 893, 905, 917, 928, 935 PAPIN............. 202, 893, 905, 917, 928, 935 Parity error .............................................. 462 PBDDR ........... 204, 893, 906, 918, 929, 935 PBODR ........... 205, 893, 906, 917, 929, 935 PBPIN ............. 205, 893, 906, 917, 929, 935 PCDDR ........... 209, 887, 900, 912, 923, 935 PCNCCS ......... 212, 884, 898, 910, 921, 935 PCNCE ........... 211, 884, 898, 910, 921, 935 PCNCMC........ 211, 884, 898, 910, 921, 935 PCNOCR ........ 215, 885, 899, 911, 921, 935 PCODR ........... 210, 887, 900, 912, 923, 935 PCPIN ............. 210, 887, 900, 912, 923, 935 PCSR .............. 265, 891, 904, 916, 926, 936 PDDDR........... 217, 887, 900, 912, 923, 935 PDNOCR ........ 223, 885, 899, 911, 921, 935
PDODR............218, 887, 900, 912, 923, 935 PDPIN..............218, 887, 900, 912, 923, 935 PEPCR.............225, 886, 900, 912, 923, 935 PEPIN ..............225, 886, 900, 912, 923, 935 Periodic count operation ......................... 336 PFNOCR..........231, 885, 899, 911, 921, 935 PFODR ............228, 886, 900, 912, 923, 935 PFPIN ..............228, 886, 900, 912, 923, 935 PGDDR............233, 886, 900, 912, 923, 936 PGNCCS..........236, 885, 898, 910, 921, 935 PGNCE ............235, 885, 898, 910, 921, 935 PGNCMC ........235, 885, 898, 910, 921, 935 PGNOCR.........242, 885, 899, 910, 921, 935 PGODR............234, 886, 900, 912, 923, 935 PGPIN..............234, 886, 900, 912, 923, 936 Phase counting mode .............................. 352 Pin arrangement.......................................... 4 Pin functions ............................................. 10 Power-down modes ................................ 859 Procedure program ................................. 783 Processing states ....................................... 54 Program counter ....................................... 29 Program-counter relative .......................... 50 Programmer mode .................................. 796 Programming/erasing interface parameter ................................................ 753 Programming/erasing interface register .................................................... 746 Protection................................................ 791 PTCNT0 ..........243, 885, 898, 910, 921, 936 PTCNT1 ..........244, 885, 899, 910, 921, 936 PTCNT2 ..........245, 885, 899, 910, 921, 936 PWDPRB.........252, 894, 907, 918, 930, 936 PWDR......................251, 894, 907, 918, 936 PWM conversion period ......................... 250 PWM modes ........................................... 347 PWOERB ........252, 894, 907, 918, 930, 936 PWSL ..............250, 894, 907, 918, 930, 936
R
RAM ....................................................... 733 RAMAR.......... 671, 884, 898, 910, 921, 942 RAMASSR ..... 669, 884, 898, 910, 920, 942 RAMBAR ....... 667, 884, 898, 909, 920, 942 RBUFAR ........ 654, 883, 897, 909, 920, 942 RDR ................ 431, 891, 904, 916, 927, 940 Register addresses........................... 883, 933 Register bits ............................................ 897 Register configuration............................... 27 Register direct ........................................... 48 Register field............................................. 47 Register indirect ........................................ 48 Register indirect with displacement .......... 49 Register indirect with post-increment ....... 49 Register indirect with pre-decrement ........ 49 Register selection condition .................... 920 Register states in each operating mode ... 909 Repeat mode ........................................... 149 Reset ......................................................... 74 Reset exception handling .......................... 74 Resolution ............................................... 250 RSR......................................................... 431 RXI1 ....................................................... 496 RXI2 ....................................................... 496
S
SAR................. 511, 889, 903, 914, 930, 940 SAR1............... 670, 884, 898, 910, 921, 942 SAR2............... 671, 884, 898, 910, 921, 942 SARX.............. 512, 894, 907, 918, 930, 940 SBYCR ........... 860, 891, 904, 916, 926, 945 Scan mode............................................... 723 SCMR ............. 444, 891, 904, 916, 927, 940 SCR................. 436, 891, 904, 916, 927, 940 SDBPR.................................................... 832 SDBSR.................................................... 832
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SDIDR .................................................... 842 SDIR....................................................... 830 Serial communication interface (SCI) .... 427 Serial communication interface specifications .......................................... 797 Serial data reception ....................... 462, 477 Serial data transmission .................. 460, 474 Serial formats.......................................... 535 Shift instructions....................................... 41 Single mode ............................................ 723 SIRQCR...........640, 886, 899, 911, 922, 943 Sleep mode ............................................. 871 Smart card............................................... 427 SMI......................................................... 712 SMR.................432, 891, 904, 916, 927, 940 Software protection................................. 793 Software standby mode .......................... 872 SSR..................439, 891, 904, 916, 927, 940 Stack pointer............................................. 28 Stack status ............................................... 77 STCR .................63, 893, 906, 918, 929, 945 STR..................634, 886, 897, 911, 922, 943 Subactive mode ...................................... 877 Subsleep mode........................................ 876 Synchronous operation ........................... 341 SYSCR ..............61, 894, 906, 918, 929, 945 SYSCR2 ..........185, 891, 904, 916, 926, 934 SYSCR3 ............66, 887, 901, 913, 924, 945 System control instructions ...................... 45
T
TAP controller ........................................ 842 TCI0V..................................................... 358 TCI1U..................................................... 358 TCI1V..................................................... 358 TCI2U..................................................... 358 TCI2V..................................................... 358 TCNT..............................331, 383, 415, 923, .........................................930, 937, 938, 939
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TCNT_0.......... 383, 894, 906, 918, 930, 937 TCONRI ......... 395, 896, 907, 919, 932, 939 TCONRS......... 396, 896, 908, 919, 932, 939 TCORA........... 383, 894, 906, 918, 929, 938 TCORB ........... 384, 894, 906, 918, 930, 938 TCORC ........... 394, 896, 907, 919, 931, 939 TCR ............................... 286, 311, 384, 923, ........................................ 927, 929, 937, 938 TCRXY........... 396, 889, 902, 914, 925, 939 TCSR .............. 283, 389, 927, 929, 937, 938 TDR ................ 432, 891, 904, 916, 927, 940 TEI1 ........................................................ 496 TEI2 ........................................................ 496 TGI0A..................................................... 358 TGI0B ..................................................... 358 TGI0C ..................................................... 358 TGI0D..................................................... 358 TGI1A..................................................... 358 TGI1B ..................................................... 358 TGI2A..................................................... 358 TGI2B ..................................................... 358 TGR ................ 331, 887, 901, 913, 923, 937 TGRA ............. 883, 897, 909, 920, 923, 938 TICRF ............. 394, 895, 907, 919, 931, 938 TICRR............. 394, 895, 907, 919, 931, 938 TIER ............... 282, 891, 904, 916, 927, 937 TIOR............... 317, 883, 897, 909, 920, 937 TISR................ 395, 889, 902, 914, 925, 939 TMDR............. 315, 883, 897, 909, 920, 937 TOCR.............. 287, 892, 905, 916, 927, 937 Toggle output.......................................... 338 Trap instruction exception handling ......... 76 TRAPA instruction ................................... 76 TSR......... 328, 432, 883, 897, 909, 923, 937 TSTR............... 331, 888, 902, 914, 924, 938 TSYR .............. 332, 888, 902, 914, 924, 938 TWR ............... 633, 885, 899, 911, 922, 943 TXI1........................................................ 496 TXI2........................................................ 496
U
UCMDTR ........676, 884, 898, 910, 921, 942 User boot MAT....................................... 795 User boot memory MAT ........................ 735 User boot mode....................................... 779 User MAT....................................... 735, 795 User program mode ................................ 768
W
Watch mode ............................................ 875 Watchdog timer (WDT) .......................... 413 Watchdog timer mode............................. 420 Waveform output by compare match...... 337 WOVI...................................................... 423 WSCR ............. 131, 894, 906, 918, 929, 933 WUE15 to WUE0 interrupts ................... 100 WUEMR ........... 94, 886, 900, 912, 923, 933 WUEMRB ........ 94, 886, 900, 912, 923, 933
V
Vector number for the software activation interrupt .................................................. 142
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Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2114R Group
Publication Date: Rev.1.00, Oct 31, 2003 Rev.3.00, Jul. 14, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd.
2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> 2-796-3115, Fax: <82> 2-796-2145
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